# Ch400 epoch descriptor table (20 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 20 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 5328 11264 480 sh3_zsrt139a60_tex_lpddr.mem 0x200000 262144 0x55070afa feeder_sh3_zsrt139a60.mem 493 54 0 sh3_zsrt139a60_pal.mem 0x32ed74c4
1 11671 10240 480 sh3_zsrt139a61_tex_lpddr.mem 0x200000 262144 0x26a88b77 feeder_sh3_zsrt139a61.mem 1060 117 0 sh3_zsrt139a61_pal.mem 0x3cd88c98
2 12757 10240 480 sh3_zsrt139a62_tex_lpddr.mem 0x200000 262144 0x26a88b77 feeder_sh3_zsrt139a62.mem 529 58 1 sh3_zsrt139a62_pal.mem 0x3cd88c98
3 15277 12288 480 sh3_zsrt139a63_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139a63.mem 781 86 0 sh3_zsrt139a63_pal.mem 0x4812d6f2
4 16217 11264 480 sh3_zsrt139a64_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a64.mem 1231 136 0 sh3_zsrt139a64_pal.mem 0x5cbf8bb4
5 16643 11264 480 sh3_zsrt139a65_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a65.mem 1231 136 1 sh3_zsrt139a65_pal.mem 0x5cbf8bb4
6 17069 11264 480 sh3_zsrt139a66_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a66.mem 763 84 1 sh3_zsrt139a66_pal.mem 0x5cbf8bb4
7 17339 11264 480 sh3_zsrt139a67_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a67.mem 1231 136 1 sh3_zsrt139a67_pal.mem 0x5cbf8bb4
8 17765 11264 480 sh3_zsrt139a68_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a68.mem 709 78 1 sh3_zsrt139a68_pal.mem 0x5cbf8bb4
9 19136 11264 480 sh3_zsrt139a69_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a69.mem 1231 136 1 sh3_zsrt139a69_pal.mem 0x5cbf8bb4
10 19562 11264 480 sh3_zsrt139a610_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a610.mem 1231 136 1 sh3_zsrt139a610_pal.mem 0x5cbf8bb4
11 20246 11264 480 sh3_zsrt139a611_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a611.mem 952 105 1 sh3_zsrt139a611_pal.mem 0x5cbf8bb4
12 20579 11264 480 sh3_zsrt139a612_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a612.mem 1231 136 1 sh3_zsrt139a612_pal.mem 0x5cbf8bb4
13 21005 11264 480 sh3_zsrt139a613_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a613.mem 1096 121 1 sh3_zsrt139a613_pal.mem 0x5cbf8bb4
14 21599 11264 480 sh3_zsrt139a614_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a614.mem 169 18 1 sh3_zsrt139a614_pal.mem 0x5cbf8bb4
15 26066 11264 480 sh3_zsrt139a615_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139a615.mem 61 6 0 sh3_zsrt139a615_pal.mem 0x44679578
16 30859 10240 480 sh3_zsrt139a616_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139a616.mem 619 68 0 sh3_zsrt139a616_pal.mem 0x47405cb0
17 31075 13824 480 sh3_zsrt139a617_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a617.mem 1231 136 0 sh3_zsrt139a617_pal.mem 0x566e7c38
18 31820 13824 480 sh3_zsrt139a618_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a618.mem 862 95 1 sh3_zsrt139a618_pal.mem 0x566e7c38
19 32391 13824 480 sh3_zsrt139a619_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a619.mem 709 78 1 sh3_zsrt139a619_pal.mem 0x566e7c38
