# ============================================================================
# retroDE_ps2 — Quartus Settings File for the DE25-Nano
# top_psmct32_raster_demo board wrapper (current as of Ch176).
#
# Sourced from sibling retroDE_splash.qsf for device/family/board pinout
# (DE25-Nano = Terasic Agilex 5 board, A5EB013BB23BE4SCS, VPBGA package).
#
# Pin scope by chapter:
#   - Ch150  CLOCK2_50, KEY[1:0], SW[3:0], LED[7:0], CLOCK0/1_50.
#   - Ch161  PLL `.ip` (`ip/pll/pll.qip`) + `USE_PLL_IP=1` macro.
#   - Ch164  HDMI ADV7513 24-bit RGB + sync data path: HDMI_TX_CLK,
#            HDMI_TX_D[23:0], HDMI_TX_HS, HDMI_TX_VS, HDMI_TX_DE.
#            See "HDMI ADV7513 transmitter pins" block below.
#   - Ch165  ADV7513 control / wake-up pins: HDMI_I2C_SCL,
#            HDMI_I2C_SDA (open-drain), HDMI_TX_INT (interrupt),
#            HDMI_MCLK (audio reference). Drives the Terasic-derived
#            I²C wake-up FSM (rtl/platform/I2C_HDMI_Config.v +
#            I2C_Controller.v). See "ADV7513 control / wake-up pins"
#            block below.
#   - Ch166  Sticky NACK watchdog from I2C_HDMI_Config.v surfaces on
#            LED[4] (active-LOW; lit = bus error latched). No new
#            top-level pins — internal driver only. LED ledger and
#            triage live at docs/hardware/de25_nano_bringup.md.
#   - Ch168  Deployment parity for the splash on-board loader:
#            - post_flow.tcl restored to the canonical retroDE shape
#              (HPS-merge + split + JIC + plain RBF), with each step
#              wrapped in `catch` so the HPS-less fabric design can't
#              gate the build; the plain RBF still emits and is
#              copied to a stable deploy name.
#            - WEAK_PULL_UP_RESISTOR on HDMI_I2C_SCL/SDA matches
#              retroDE_a2600 / retroDE_nes.
#            - Stable artifact: output_files/retroDE_ps2.core.rbf
#              (what core_loader.sh consumes on the board).
#            - HARDWARE PROOF (board test): plain RBF loaded cleanly
#              through `core_loader.sh` → `fpga0: operating`; all
#              status LEDs lit as expected → qsys integration NOT
#              required; loader pipeline confirmed.
#   - Ch169  Video-timing baseline (VGA 640x480 @ 60Hz):
#            - IOPLL `pll.ip` outclk_0 retuned 50 MHz → 25.175 MHz
#              (the VGA spec pixel clock; PLL achieves it via
#              integer M=20/N=1/C=40 divider chain).
#            - Board wrapper overrides PCRTC timing on the
#              `top_psmct32_raster_demo_bram` instantiation:
#              H_ACTIVE=640, H_FRONT=16, H_SYNC=96, H_BACK=48;
#              V_ACTIVE=480, V_FRONT=10, V_SYNC=2, V_BACK=33.
#              16x8 PCRTC frame paints in the upper-left of a real
#              VGA raster the monitor can lock to.
#            - Inner wrapper gains H_FRONT/H_SYNC/H_BACK/V_FRONT/
#              V_SYNC/V_BACK as parameters (defaults preserve the
#              Ch123 1-pixel-border behavior for non-board TBs).
#            - Sim board TB watchdog bumped 20 ms → 30 ms (the
#              VGA frame is ~8 ms simulated vs the Ch168 toy
#              ~4 µs frame).
#            - HARDWARE TEST OUTCOME: monitor still no signal, AND
#              fpga-manager-loaded plain RBF was hosing HPS (SSH
#              died, board required power-cycle). Diagnosis: ps2
#              fabric runs (LEDs lit) but had no HPS bridge
#              endpoints, so HPS-side transactions stalled into
#              the void. Ch170 fixes this — the video-timing
#              fix from Ch169 stays.
#   - Ch170  Platform-shell parity (loader-safe ps2 core):
#            - qsys/ copied verbatim from retroDE_Atari2600/qsys/
#              (byte-identical boilerplate across all cores).
#              qsys_top.qsys + hps_subsys/ + peripheral_subsys/
#              + the generated .qip/.ip artifacts.
#            - Top wrapper gains HPS_* (~24 ports) + LPDDR4A_*
#              (~12 ports) port block (~74 pins).
#            - `qsys_top soc_inst (...)` instantiated in the top
#              with all HPS/LPDDR4A wired through, f2sdram tied
#              off, h2f_irq tied to 0, PIO surfaces tied to
#              SW/KEY (matches a2600 wiring exactly).
#            - clk_100_clk fed from raw CLOCK2_50 (the qsys bridge
#              clock domain is fully independent from the ps2
#              pixel PLL @ 25.175 MHz).
#            - New `rtl/platform/ps2_hps_bridge_null.sv` — minimal
#              AXI4 slave for the hps2fpga bridge. Same port
#              signature as splash_hps_bridge.sv so a future
#              real ps2 bridge can drop in. Identity register
#              window at 0x000-0x00F: CORE_ID=0x70533200,
#              ABI_VERSION=0x00000100, CORE_STATUS=0x00000001,
#              CORE_CAPS=0. All other reads return 0; all writes
#              ACK'd-and-ignored with full AXI4 handshake so
#              HPS-side transactions can't stall the bus.
#            - QSF gains: 196-line verbatim HPS+LPDDR4A pin
#              assignment block (sourced from a2600.qsf), 5
#              IP_FILE + 3 QSYS_FILE entries, the new SV source.
#            - Board sim TB updated to tie off the new HPS+LPDDR4A
#              ports (sim doesn't model HPS hard IP behavior).
#   - Ch171  Bigger test card on hardware (320x240 four-quadrant):
#            - VRAM_BYTES bumped 8 KiB → 512 KiB at the board wrapper
#              instantiation (power-of-2 cap on the bram_stub depth;
#              320*240*4 = 307,200 bytes needs ≥256 KiB; 512 KiB is
#              the next power-of-2 and leaves headroom).
#            - bake.py reworked to emit two parallel fixture sets:
#              bios.mem + payload.mem (Ch171 production, 320x240
#              R/G/B/W quadrants, used by synth/board) and
#              bios_ch146.mem + payload_ch146.mem (legacy 16x8 set
#              used by the pre-Ch171 sim TBs that do per-pixel
#              assertions). Bootlet writes DISPLAY1 = (DW=319,
#              DH=239) so the PCRTC scans the full 320x240 from
#              VRAM.
#            - New `tb_top_psmct32_raster_demo_bram_ch171` spot-checks
#              the Ch171 pattern at 8 (x,y) probes inside the
#              quadrants + at the x=159/160 and y=119/120 boundaries.
#              Sim regression: 144 → 145 PASS.
#            - Quartus deltas vs Ch170 baseline: ALMs nearly flat,
#              BRAM bits +307,200×8 ≈ +2.4 Mbit (35% of total M20K).
#   - Ch172  Raster-FIFO backpressure (proper architectural fix for the
#            Ch171 4th-sprite drop):
#            - gs_stub exposes new `raster_fifo_full` output (the
#              internal Ch87 FIFO's `fifo_full`).
#            - gif_packed_stub gains a `raster_fifo_full` input that
#              gates `in_ready` LOW outside S_IMAGE: stall happens
#              at the qword-acceptance handshake (Codex caution
#              honored — no half-committed parser state).
#            - Both top wrappers (top_psmct32_raster_demo +
#              top_psmct32_raster_demo_bram) wire gs_stub.
#              raster_fifo_full → gif_packed_stub.raster_fifo_full.
#            - 27 sibling TBs that don't model the raster FIFO tie
#              the new port to 1'b0 (the existing image_data_ready
#              tie-off pattern from Ch110).
#            - New tb_gs_raster_backpressure_stress proves: 8
#              SPRITEs in flight (4× FIFO capacity) → in_ready
#              goes LOW for ~7K cycles total → all 8 sprites land
#              in VRAM → raster_overflow stays LOW.
#            - FIFO_DEPTH reverted 4 → 2 (the Ch87 original) so
#              backpressure is the only safety net; stress TB
#              would crash if the gate ever breaks.
#   - Ch173  HPS↔fabric status bridge (read-only):
#            - New `rtl/platform/ps2_hps_bridge.sv` replaces
#              `ps2_hps_bridge_null` on the hps2fpga AXI slave port.
#              Port signature is a strict superset of the null
#              bridge so the swap is drop-in at the top.
#            - Register map honors the retroDE common ABI v1.0
#              (see retroDE_splash/software/input_common.h):
#              CORE_ID=0x50533200 at 0x000, ABI_VERSION at 0x004,
#              CORE_STATUS at 0x008 (live core_halt / dma_done_seen
#              / frame_seen / hdmi_init_done / hdmi_i2c_error /
#              raster_overflow bits), CORE_CAPS at 0x00C, CORE_CTRL
#              + CORE_PULSE at 0x010/0x014 (read-zero stubs in
#              Ch173). PS2-specific diagnostics at 0x020+:
#              FRAME_COUNT (0x020), DMA_DONE_COUNT (0x024),
#              RASTER_OVERFLOW_COUNT (0x028 — should stay 0 under
#              Ch172 backpressure).
#            - Writes ACK'd with OKAY response and discarded across
#              the whole map (Codex Ch173 caution honored).
#            - Status inputs are CDC'd from design_clk into the
#              CLOCK2_50 bridge clock via 2-FF synchronizers; edge
#              detect happens on the synchronized signals.
#            - Inner wrappers (top_psmct32_raster_demo +
#              top_psmct32_raster_demo_bram) gain `raster_overflow`
#              output that surfaces gs_stub's existing
#              raster_overflow flag; the board top wires it into
#              the bridge.
#            - New `sim/tb/platform/tb_ps2_hps_bridge.sv` unit-tests
#              the bridge directly: AXI reads at every register,
#              edge-counter behavior verified, OOB reads return 0,
#              writes ACK'd-and-discarded. Sim 146 → 147 PASS.
#            - Hardware-confirmed: HPS reads at base 0x40000000
#              return CORE_ID=0x50533200, CORE_STATUS=0x1F (loaded
#              + halt + dma_done + frame_seen + hdmi_init),
#              RASTER_OVERFLOW_COUNT=0.
#   - Ch174  HPS counters become real frame/DMA odometers:
#            - Replaces Ch173's edge-of-sticky counter source with
#              an *event-toggle* primitive. The inner wrappers add
#              `frame_toggle` / `dma_done_toggle` outputs (flip-
#              flops in the design_clk domain that toggle on every
#              PCRTC end-of-frame / DMAC `EV_DMA_DONE` pulse). The
#              bridge 2-FF syncs each toggle to CLOCK2_50 and
#              XOR-edge-detects against its previous sample — each
#              edge of the synced toggle = one event.
#            - Motivation: a 1-cycle 25 MHz pulse (40 ns) is
#              borderline against a 50 MHz 2-FF synchronizer and
#              would occasionally miss frames on hardware. The
#              toggle stays at its new value for the full inter-
#              event interval (~16.7 ms for frames), so the
#              synchronizer has megacycles of slack and cannot
#              miss an event.
#            - Sticky `frame_seen` / `dma_done_seen` remain the
#              CORE_STATUS bit sources (bit 3 / bit 2) — only the
#              counter inputs changed. Bridge header carries an
#              explicit warning against "simplifying" this back
#              into raw pulse synchronizers.
#            - Bridge TB grows two regressions: rising the sticky
#              source MUST NOT advance the counter (Ch174 CDC-
#              safety check), and the toggle path counts both
#              rising and falling edges as events. Sim 147 → 147
#              PASS (bridge TB updated in place; no new TB).
#   - Ch175  ps2 promoted to first-class retroDE core:
#            - Pure manifest-only deployment — zero source changes
#              in retroDE_ps2 OR retroDE_splash. Single .cfg
#              stanza on the DE25-Nano: backend=splash,
#              core_id=0x50533200, min_abi=0x100, media=none.
#            - Codex's first-guess backend=splash accepted by
#              retrodesd without modification; rom_simple fallback
#              never needed.
#            - Hardware-confirmed end-to-end: retrodesd hot-swap
#              from nes to ps2 via OSD, fabric_mgr loads RBF,
#              ABI probe validates, splash backend's "OSD force-
#              open, supervisor-first" runs.
#            - Side win: clean ABI_VERSION readback at 0x40000004
#              via retrodesd's mmap'd volatile uint32 loads
#              pins the earlier devmem2 bus errors as a tool
#              quirk, not a bridge defect.
#   - Ch176  CORE_CTRL writable + CORE_PULSE counter-clear pulse:
#            - Completes the minimal ABI contract — read-only was
#              Ch173; writable control is the natural other half.
#              Bit layout follows retroDE_splash/software/
#              input_common.h verbatim (no new bits invented).
#            - CORE_CTRL @ 0x010 is now writable + readable. bit 0
#              RESET is functional and drives a new `core_reset_req`
#              output port; the board top 2-FF syncs it into
#              design_clk and ANDs it into core_rst_n. bits 1
#              ROM_LOADED and 2 PAUSE are pure latches (ABI-shape
#              only — PS2 has no ROM/pause lifecycle yet). bits
#              [31:3] are ignored on write.
#            - CORE_PULSE @ 0x014 is write-only (always reads 0).
#              bit 3 HDMI_CLR fires a synchronous CLOCK2_50 pulse
#              that zeros FRAME_COUNT / DMA_DONE_COUNT /
#              RASTER_OVERFLOW_COUNT (PS2 widens the shared "HDMI
#              diagnostic clear" name to "video/bridge diagnostic
#              clear" — explicit per Codex Ch176 naming note).
#              bits [0..2] DIRTY_CLR / SS_DONE_CLR / VIDEO_REC
#              ACK and ignore for now.
#            - RESET deliberately does NOT zero the counters —
#              CORE_PULSE.HDMI_CLR is the explicit knob for that.
#              Counters live in CLOCK2_50 and survive the design-
#              domain reset; useful for measuring frame activity
#              across a reset event.
#            - Bridge TB grows two new sections (9 + 10): CORE_CTRL
#              round-trip latching including bit-mask drop test
#              (writing 0xFFFFFFFF reads back 0x07), reset
#              assert/release observed on the new output port,
#              HDMI_CLR clears all three counters synchronously,
#              no-op pulses leave counters alone, post-clear
#              toggle path still increments.
#
# Deferred to Ch177+:
#   - LPDDR4 / SDRAM / HPS / CAM / UART / GPIO assignments
#   - CRTC-grade output-delay constraints on the HDMI pins
#     (replaces the Ch164 `set_false_path -to` scaffold; lands once
#     the ADV7513 setup/hold window is locked from the bring-up
#     datasheet pass).
# ============================================================================

set_global_assignment -name FAMILY "Agilex 5"
set_global_assignment -name DEVICE A5EB013BB23BE4SCS
set_global_assignment -name DEVICE_FILTER_PACKAGE VPBGA
set_global_assignment -name TOP_LEVEL_ENTITY de25_nano_psmct32_raster_demo_top
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

# ----------------------------------------------------------------------------
# Clocks
# ----------------------------------------------------------------------------
set_instance_assignment -name IO_STANDARD "1.1-V" -to CLOCK0_50 -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLOCK1_50 -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLOCK2_50 -entity de25_nano_psmct32_raster_demo_top
set_location_assignment PIN_DJ35 -to CLOCK0_50
set_location_assignment PIN_V16 -to CLOCK1_50
set_location_assignment PIN_BF23 -to CLOCK2_50

# ----------------------------------------------------------------------------
# Buttons (active-low)
# ----------------------------------------------------------------------------
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY[0] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to KEY[1] -entity de25_nano_psmct32_raster_demo_top
set_location_assignment PIN_C8 -to KEY[0]
set_location_assignment PIN_C11 -to KEY[1]

# ----------------------------------------------------------------------------
# DIP switches (placeholder — wrapper ties them off)
# ----------------------------------------------------------------------------
set_instance_assignment -name IO_STANDARD "1.1-V" -to SW[0] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to SW[1] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to SW[2] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to SW[3] -entity de25_nano_psmct32_raster_demo_top
set_location_assignment PIN_DK24 -to SW[0]
set_location_assignment PIN_DD24 -to SW[1]
set_location_assignment PIN_DD27 -to SW[2]
set_location_assignment PIN_DF27 -to SW[3]

# ----------------------------------------------------------------------------
# LEDs (active-low; wrapper drives:
#   LED[0] = ~core_halt        (lit = EE halted, good)
#   LED[1] = ~dma_done_seen    (lit = DMA finished, good)
#   LED[2] = ~frame_seen       (lit = PCRTC frame, good)
#   LED[3] = ~hdmi_init_done   (Ch165, lit = HDMI configured, good)
#   LED[4] = ~hdmi_i2c_error   (Ch166, lit = NACK watchdog latched, BAD)
#   LED[7:5] = HIGH = OFF
# See docs/hardware/de25_nano_bringup.md for the full LED ledger + triage.
# ----------------------------------------------------------------------------
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[0] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[1] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[2] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[3] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[4] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[5] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[6] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "1.1-V" -to LED[7] -entity de25_nano_psmct32_raster_demo_top
set_location_assignment PIN_DF35 -to LED[0]
set_location_assignment PIN_DJ32 -to LED[1]
set_location_assignment PIN_DN22 -to LED[2]
set_location_assignment PIN_DP23 -to LED[3]
set_location_assignment PIN_DN25 -to LED[4]
set_location_assignment PIN_DP25 -to LED[5]
set_location_assignment PIN_DJ27 -to LED[6]
set_location_assignment PIN_DP30 -to LED[7]

# ----------------------------------------------------------------------------
# Abstract VIDEO_* pins — sim/TB compat only (Ch164: VIRTUAL_PIN)
# ----------------------------------------------------------------------------
# VIDEO_R/G/B/HSYNC/VSYNC/DE are kept as VIRTUAL_PIN ON because the
# Ch149 board TB references them via hierarchical probe; the real
# bitstream output pins are HDMI_TX_* (Ch164 — see below) which the
# wrapper drives from the same VIDEO_* signals. Keeping VIDEO_*
# virtualized prevents Quartus from auto-placing them on arbitrary
# package pins (potentially driving real signals on LPDDR4 / HPS /
# etc.).
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[0] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[1] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[2] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[3] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[4] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[5] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[6] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_R[7] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[0] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[1] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[2] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[3] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[4] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[5] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[6] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_G[7] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[0] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[1] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[2] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[3] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[4] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[5] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[6] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_B[7] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_HSYNC -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_VSYNC -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name VIRTUAL_PIN ON -to VIDEO_DE -entity de25_nano_psmct32_raster_demo_top

# ----------------------------------------------------------------------------
# HDMI ADV7513 transmitter pins (Ch164 — real package pins)
# ----------------------------------------------------------------------------
# Pinout sourced from `retroDE_nes/retroDE_nes.qsf` for the same
# DE25-Nano (Terasic Agilex 5) board. ADV7513 24-bit RGB + sync
# input is driven directly by the wrapper's VIDEO_* signals; the
# pixel clock is `design_clk` (50 MHz post-PLL).
#
# IO standards mirror retroDE_nes: HDMI_TX_CLK uses 1.1-V (matches
# the on-board level shifter); the data + sync pins use 3.3-V LVCMOS.
#
# Companion ADV7513 pins (HDMI_I2C_SCL / HDMI_I2C_SDA / HDMI_TX_INT
# / HDMI_MCLK) are intentionally NOT yet pinned — the chip stays in
# standby on power-up and ignores its 24-bit RGB input until the
# Ch165+ I²C wake-up FSM lands.
set_instance_assignment -name IO_STANDARD "1.1-V" -to HDMI_TX_CLK -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_HS -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_VS -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_DE -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[0] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[1] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[2] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[3] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[4] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[5] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[6] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[7] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[8] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[9] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[10] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[11] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[12] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[13] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[14] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[15] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[16] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[17] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[18] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[19] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[20] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[21] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[22] -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_D[23] -entity de25_nano_psmct32_raster_demo_top
set_location_assignment PIN_DJ24 -to HDMI_TX_CLK
set_location_assignment PIN_BR11 -to HDMI_TX_HS
set_location_assignment PIN_BR14 -to HDMI_TX_VS
set_location_assignment PIN_CJ2 -to HDMI_TX_DE
set_location_assignment PIN_AV19 -to HDMI_TX_D[0]
set_location_assignment PIN_AT11 -to HDMI_TX_D[1]
set_location_assignment PIN_BE11 -to HDMI_TX_D[2]
set_location_assignment PIN_AV14 -to HDMI_TX_D[3]
set_location_assignment PIN_AT19 -to HDMI_TX_D[4]
set_location_assignment PIN_AT14 -to HDMI_TX_D[5]
set_location_assignment PIN_AV16 -to HDMI_TX_D[6]
set_location_assignment PIN_AV11 -to HDMI_TX_D[7]
set_location_assignment PIN_BH11 -to HDMI_TX_D[8]
set_location_assignment PIN_BE14 -to HDMI_TX_D[9]
set_location_assignment PIN_BE19 -to HDMI_TX_D[10]
set_location_assignment PIN_BH14 -to HDMI_TX_D[11]
set_location_assignment PIN_BV6 -to HDMI_TX_D[12]
set_location_assignment PIN_BJ23 -to HDMI_TX_D[13]
set_location_assignment PIN_BV4 -to HDMI_TX_D[14]
set_location_assignment PIN_BU23 -to HDMI_TX_D[15]
set_location_assignment PIN_BH16 -to HDMI_TX_D[16]
set_location_assignment PIN_DA1 -to HDMI_TX_D[17]
set_location_assignment PIN_BH19 -to HDMI_TX_D[18]
set_location_assignment PIN_CP2 -to HDMI_TX_D[19]
set_location_assignment PIN_CM1 -to HDMI_TX_D[20]
set_location_assignment PIN_DA2 -to HDMI_TX_D[21]
set_location_assignment PIN_CP1 -to HDMI_TX_D[22]
set_location_assignment PIN_CU2 -to HDMI_TX_D[23]

# ----------------------------------------------------------------------------
# ADV7513 control / wake-up pins (Ch165)
# ----------------------------------------------------------------------------
# I²C bus: SCL master-driven, SDA two-wire open-drain. Both lines have
# external pull-ups on the DE25-Nano board. HDMI_TX_INT is the chip's
# open-drain interrupt output (active-low; HPD + monitor-sense events).
# HDMI_MCLK is the audio sample-rate reference; the demo drives it
# from CLOCK2_50 (the chip ignores audio while video-only is
# configured by the wake-up LUT).
#
# Pin locations sourced from `retroDE_nes/retroDE_nes.qsf` for the
# same DE25-Nano board.
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_I2C_SCL -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_I2C_SDA -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_TX_INT -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to HDMI_MCLK -entity de25_nano_psmct32_raster_demo_top
# Ch168 — match retroDE_a2600 / retroDE_nes parity: enable internal weak
# pull-up on the I²C lines so SCL/SDA idle HIGH even before external
# board pull-ups are reliable. The bus is open-drain (master drives LOW
# or releases to 1'bz); without a pull-up either internal or external,
# released cycles read as 'x' in some Quartus IO models.
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HDMI_I2C_SCL -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HDMI_I2C_SDA -entity de25_nano_psmct32_raster_demo_top
set_location_assignment PIN_BT1 -to HDMI_I2C_SCL
set_location_assignment PIN_BW2 -to HDMI_I2C_SDA
set_location_assignment PIN_CF2 -to HDMI_TX_INT
set_location_assignment PIN_CF1 -to HDMI_MCLK

# ----------------------------------------------------------------------------
# Ch170 — HPS + LPDDR4A pin assignments (verbatim from
# retroDE_Atari2600/retroDE_a2600.qsf). These wire the qsys_top
# instance's hps_io_* and emif_hps_emif_* ports through to the
# physical package pins on the DE25-Nano. Required so the produced
# .core.rbf is "shaped" like every other retroDE core and survives
# runtime fabric reload through core_loader.sh without hosing the
# HPS-running splash environment. To re-sync from a2600 in future:
#   grep -E "^set_(instance|location)_assignment.*-to (HPS_|LPDDR4A_)" \
#     ../../../../retroDE_Atari2600/retroDE_a2600.qsf
# ----------------------------------------------------------------------------
set_instance_assignment -name IO_STANDARD "1.1-V TRUE DIFFERENTIAL SIGNALING" -to LPDDR4A_REFCLK_p
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CS_n
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CA[0]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CA[1]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CA[2]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CA[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CA[4]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CA[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_CK
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_CKE
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_CK_n
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DM[0]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DM[1]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DM[2]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DM[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[0]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[1]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[2]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[4]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[5]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[6]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[7]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[8]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[9]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[10]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[11]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[12]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[13]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[14]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[15]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[16]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[17]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[18]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[19]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[20]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[21]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[22]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[23]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[24]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[25]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[26]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[27]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[28]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[29]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[30]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_DQ[31]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS_n[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS_n[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS_n[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4A_DQS_n[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4A_RESET_n
set_instance_assignment -name IO_STANDARD "1.1-V" -to LPDDR4A_RZQ
set_location_assignment PIN_B55  -to LPDDR4A_REFCLK_p
set_location_assignment PIN_B58  -to LPDDR4A_CS_n
set_location_assignment PIN_B66  -to LPDDR4A_CA[0]
set_location_assignment PIN_A68  -to LPDDR4A_CA[1]
set_location_assignment PIN_B68  -to LPDDR4A_CA[2]
set_location_assignment PIN_A70  -to LPDDR4A_CA[3]
set_location_assignment PIN_B63  -to LPDDR4A_CA[4]
set_location_assignment PIN_A66  -to LPDDR4A_CA[5]
set_location_assignment PIN_J42  -to LPDDR4A_CK
set_location_assignment PIN_A61  -to LPDDR4A_CKE
set_location_assignment PIN_G42  -to LPDDR4A_CK_n
set_location_assignment PIN_J59  -to LPDDR4A_DM[0]
set_location_assignment PIN_T59  -to LPDDR4A_DM[1]
set_location_assignment PIN_J27  -to LPDDR4A_DM[2]
set_location_assignment PIN_A25  -to LPDDR4A_DM[3]
set_location_assignment PIN_T62  -to LPDDR4A_DQ[0]
set_location_assignment PIN_T56  -to LPDDR4A_DQ[1]
set_location_assignment PIN_G56  -to LPDDR4A_DQ[2]
set_location_assignment PIN_E56  -to LPDDR4A_DQ[3]
set_location_assignment PIN_G65  -to LPDDR4A_DQ[4]
set_location_assignment PIN_J65  -to LPDDR4A_DQ[5]
set_location_assignment PIN_M56  -to LPDDR4A_DQ[6]
set_location_assignment PIN_M62  -to LPDDR4A_DQ[7]
set_location_assignment PIN_W62  -to LPDDR4A_DQ[8]
set_location_assignment PIN_M65  -to LPDDR4A_DQ[9]
set_location_assignment PIN_M51  -to LPDDR4A_DQ[10]
set_location_assignment PIN_T51  -to LPDDR4A_DQ[11]
set_location_assignment PIN_AB48 -to LPDDR4A_DQ[12]
set_location_assignment PIN_W48  -to LPDDR4A_DQ[13]
set_location_assignment PIN_T65  -to LPDDR4A_DQ[14]
set_location_assignment PIN_AB62 -to LPDDR4A_DQ[15]
set_location_assignment PIN_G24  -to LPDDR4A_DQ[16]
set_location_assignment PIN_E24  -to LPDDR4A_DQ[17]
set_location_assignment PIN_J35  -to LPDDR4A_DQ[18]
set_location_assignment PIN_T32  -to LPDDR4A_DQ[19]
set_location_assignment PIN_M32  -to LPDDR4A_DQ[20]
set_location_assignment PIN_T24  -to LPDDR4A_DQ[21]
set_location_assignment PIN_G35  -to LPDDR4A_DQ[22]
set_location_assignment PIN_M24  -to LPDDR4A_DQ[23]
set_location_assignment PIN_A22  -to LPDDR4A_DQ[24]
set_location_assignment PIN_A23  -to LPDDR4A_DQ[25]
set_location_assignment PIN_A33  -to LPDDR4A_DQ[26]
set_location_assignment PIN_B33  -to LPDDR4A_DQ[27]
set_location_assignment PIN_B30  -to LPDDR4A_DQ[28]
set_location_assignment PIN_A36  -to LPDDR4A_DQ[29]
set_location_assignment PIN_A20  -to LPDDR4A_DQ[30]
set_location_assignment PIN_B22  -to LPDDR4A_DQ[31]
set_location_assignment PIN_G62  -to LPDDR4A_DQS[0]
set_location_assignment PIN_AB56 -to LPDDR4A_DQS[1]
set_location_assignment PIN_G32  -to LPDDR4A_DQS[2]
set_location_assignment PIN_B28  -to LPDDR4A_DQS[3]
set_location_assignment PIN_E62  -to LPDDR4A_DQS_n[0]
set_location_assignment PIN_W56  -to LPDDR4A_DQS_n[1]
set_location_assignment PIN_E32  -to LPDDR4A_DQS_n[2]
set_location_assignment PIN_A30  -to LPDDR4A_DQS_n[3]
set_location_assignment PIN_M48  -to LPDDR4A_RESET_n
set_location_assignment PIN_T48  -to LPDDR4A_RZQ
# Ch319 — FPGA-private LPDDR4B pin map (verbatim from de25_lpddr4_bw, same DE25-Nano device).
set_instance_assignment -name IO_STANDARD "1.1-V TRUE DIFFERENTIAL SIGNALING" -to LPDDR4B_REFCLK_p
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CS_n
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CA[0]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CA[1]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CA[2]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CA[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CA[4]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CA[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_CK
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_CKE
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_CK_n
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DM[0]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DM[1]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DM[2]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DM[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[0]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[1]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[2]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[4]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[5]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[6]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[7]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[8]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[9]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[10]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[11]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[12]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[13]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[14]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[15]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[16]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[17]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[18]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[19]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[20]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[21]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[22]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[23]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[24]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[25]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[26]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[27]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[28]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[29]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[30]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_DQ[31]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS_n[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS_n[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS_n[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.1-V LVSTL" -to LPDDR4B_DQS_n[3]
set_instance_assignment -name IO_STANDARD "1.1-V LVSTL" -to LPDDR4B_RESET_n
set_instance_assignment -name IO_STANDARD "1.1-V" -to LPDDR4B_RZQ
set_location_assignment PIN_DK39 -to LPDDR4B_REFCLK_p
set_location_assignment PIN_DD42 -to LPDDR4B_CS_n
set_location_assignment PIN_DJ51 -to LPDDR4B_CA[0]
set_location_assignment PIN_DF51 -to LPDDR4B_CA[1]
set_location_assignment PIN_DD51 -to LPDDR4B_CA[2]
set_location_assignment PIN_DD48 -to LPDDR4B_CA[3]
set_location_assignment PIN_DK48 -to LPDDR4B_CA[4]
set_location_assignment PIN_DJ48 -to LPDDR4B_CA[5]
set_location_assignment PIN_DP47 -to LPDDR4B_CK
set_location_assignment PIN_DJ42 -to LPDDR4B_CKE
set_location_assignment PIN_DN45 -to LPDDR4B_CK_n
set_location_assignment PIN_DJ59 -to LPDDR4B_DM[0]
set_location_assignment PIN_DP66 -to LPDDR4B_DM[1]
set_location_assignment PIN_DP10 -to LPDDR4B_DM[2]
set_location_assignment PIN_DJ12 -to LPDDR4B_DM[3]
set_location_assignment PIN_DJ65 -to LPDDR4B_DQ[0]
set_location_assignment PIN_DF65 -to LPDDR4B_DQ[1]
set_location_assignment PIN_DD59 -to LPDDR4B_DQ[2]
set_location_assignment PIN_DJ56 -to LPDDR4B_DQ[3]
set_location_assignment PIN_DD56 -to LPDDR4B_DQ[4]
set_location_assignment PIN_DK56 -to LPDDR4B_DQ[5]
set_location_assignment PIN_DD65 -to LPDDR4B_DQ[6]
set_location_assignment PIN_DD62 -to LPDDR4B_DQ[7]
set_location_assignment PIN_DN73 -to LPDDR4B_DQ[8]
set_location_assignment PIN_DN74 -to LPDDR4B_DQ[9]
set_location_assignment PIN_DP60 -to LPDDR4B_DQ[10]
set_location_assignment PIN_DN58 -to LPDDR4B_DQ[11]
set_location_assignment PIN_DN61 -to LPDDR4B_DQ[12]
set_location_assignment PIN_DP61 -to LPDDR4B_DQ[13]
set_location_assignment PIN_DN68 -to LPDDR4B_DQ[14]
set_location_assignment PIN_DP70 -to LPDDR4B_DQ[15]
set_location_assignment PIN_DN10 -to LPDDR4B_DQ[16]
set_location_assignment PIN_DN17 -to LPDDR4B_DQ[17]
set_location_assignment PIN_DP20 -to LPDDR4B_DQ[18]
set_location_assignment PIN_DN20 -to LPDDR4B_DQ[19]
set_location_assignment PIN_DP7 -to LPDDR4B_DQ[20]
set_location_assignment PIN_DP22 -to LPDDR4B_DQ[21]
set_location_assignment PIN_DN3 -to LPDDR4B_DQ[22]
set_location_assignment PIN_DN7 -to LPDDR4B_DQ[23]
set_location_assignment PIN_DD9 -to LPDDR4B_DQ[24]
set_location_assignment PIN_DD12 -to LPDDR4B_DQ[25]
set_location_assignment PIN_DJ21 -to LPDDR4B_DQ[26]
set_location_assignment PIN_DD21 -to LPDDR4B_DQ[27]
set_location_assignment PIN_DF21 -to LPDDR4B_DQ[28]
set_location_assignment PIN_DD18 -to LPDDR4B_DQ[29]
set_location_assignment PIN_DJ9 -to LPDDR4B_DQ[30]
set_location_assignment PIN_DK9 -to LPDDR4B_DQ[31]
set_location_assignment PIN_DK62 -to LPDDR4B_DQS[0]
set_location_assignment PIN_DP68 -to LPDDR4B_DQS[1]
set_location_assignment PIN_DP15 -to LPDDR4B_DQS[2]
set_location_assignment PIN_DK18 -to LPDDR4B_DQS[3]
set_location_assignment PIN_DJ62 -to LPDDR4B_DQS_n[0]
set_location_assignment PIN_DN66 -to LPDDR4B_DQS_n[1]
set_location_assignment PIN_DN15 -to LPDDR4B_DQS_n[2]
set_location_assignment PIN_DJ18 -to LPDDR4B_DQS_n[3]
set_location_assignment PIN_DN55 -to LPDDR4B_RESET_n
set_location_assignment PIN_DP58 -to LPDDR4B_RZQ
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_CLK_25
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_MDC
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_MDIO
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_RX_CLK
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_RX_CTL
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_RX_DATA[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_RX_DATA[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_RX_DATA[2]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_RX_DATA[3]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_TX_CLK
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_TX_CTL
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_TX_DATA[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_TX_DATA[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_TX_DATA[2]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_ENET_TX_DATA[3]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_GSENSOR_I2C_EN
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_GSENSOR_INT
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_I2C_SCL
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_I2C_SDA
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_KEY
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_LED
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_SD_CLK
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_SD_CMD
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_SD_DATA[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_SD_DATA[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_SD_DATA[2]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_SD_DATA[3]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_UART_RX
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_UART_TX
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_CLK
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[0]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[1]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[2]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[3]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[4]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[5]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[6]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DATA[7]
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_DIR
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_NXT
set_instance_assignment -name IO_STANDARD "1.8-V" -to HPS_USB_STP
set_location_assignment PIN_AN67 -to HPS_CLK_25
set_location_assignment PIN_D71  -to HPS_ENET_MDC
set_location_assignment PIN_C74  -to HPS_ENET_MDIO
set_location_assignment PIN_BL75 -to HPS_ENET_RX_CLK
set_location_assignment PIN_AP74 -to HPS_ENET_RX_CTL
set_location_assignment PIN_BD74 -to HPS_ENET_RX_DATA[0]
set_location_assignment PIN_AN71 -to HPS_ENET_RX_DATA[1]
set_location_assignment PIN_AJ74 -to HPS_ENET_RX_DATA[2]
set_location_assignment PIN_AJ75 -to HPS_ENET_RX_DATA[3]
set_location_assignment PIN_BP75 -to HPS_ENET_TX_CLK
set_location_assignment PIN_BL74 -to HPS_ENET_TX_CTL
set_location_assignment PIN_BG74 -to HPS_ENET_TX_DATA[0]
set_location_assignment PIN_AP75 -to HPS_ENET_TX_DATA[1]
set_location_assignment PIN_BD75 -to HPS_ENET_TX_DATA[2]
set_location_assignment PIN_AM74 -to HPS_ENET_TX_DATA[3]
set_location_assignment PIN_P75  -to HPS_GSENSOR_I2C_EN
set_location_assignment PIN_Y75  -to HPS_GSENSOR_INT
set_location_assignment PIN_N72  -to HPS_I2C_SCL
set_location_assignment PIN_L75  -to HPS_I2C_SDA
set_location_assignment PIN_F75  -to HPS_KEY
set_location_assignment PIN_AD71 -to HPS_LED
set_location_assignment PIN_AC74 -to HPS_SD_CLK
set_location_assignment PIN_AK69 -to HPS_SD_CMD
set_location_assignment PIN_AF75 -to HPS_SD_DATA[0]
set_location_assignment PIN_AC75 -to HPS_SD_DATA[1]
set_location_assignment PIN_AN64 -to HPS_SD_DATA[2]
set_location_assignment PIN_Y74  -to HPS_SD_DATA[3]
set_location_assignment PIN_AD72 -to HPS_UART_RX
set_location_assignment PIN_N71  -to HPS_UART_TX
set_location_assignment PIN_BC64 -to HPS_USB_CLK
set_location_assignment PIN_AN72 -to HPS_USB_DATA[0]
set_location_assignment PIN_AY69 -to HPS_USB_DATA[1]
set_location_assignment PIN_BC71 -to HPS_USB_DATA[2]
set_location_assignment PIN_AU74 -to HPS_USB_DATA[3]
set_location_assignment PIN_AY71 -to HPS_USB_DATA[4]
set_location_assignment PIN_AU75 -to HPS_USB_DATA[5]
set_location_assignment PIN_BC72 -to HPS_USB_DATA[6]
set_location_assignment PIN_BP74 -to HPS_USB_DATA[7]
set_location_assignment PIN_AY67 -to HPS_USB_DIR
set_location_assignment PIN_BA75 -to HPS_USB_NXT
set_location_assignment PIN_BC67 -to HPS_USB_STP

# ----------------------------------------------------------------------------
# Source files — matches synth/de25_nano/top_psmct32_raster_demo/files.f.
# Paths are relative to the Quartus project directory; create the project
# at the repo root so these resolve.
# ----------------------------------------------------------------------------
# Ch159 VRAM-shape sources (file ordering matters for elaboration of
# the package consumers): legacy `vram_stub` is kept on the project
# for back-compat, but the Ch149 board wrapper now instantiates
# `top_psmct32_raster_demo_bram` (BRAM-backed). Quartus only
# elaborates the VRAM module that the actually-instantiated top
# wrapper depends on; the unused module is trimmed.
# Ch151 — PLL sim stub. When the real Quartus IOPLL is in use (define
# USE_PLL_IP and add the IP's .qip / .ip to the project), the board
# wrapper's `\`ifdef` swaps to the real IP module and this stub is
# unreferenced. Quartus will warn about the unreferenced module but
# trim it cleanly. To remove the stub from the project entirely,
# delete this line and uncomment the `set_global_assignment -name
# QIP_FILE` line below pointing at the real IP.
# Ch165 — Terasic-derived ADV7513 I²C wake-up FSM + the
# bit-banging I²C controller it drives. Both files are plain
# Verilog (the I2C_Controller has the canonical Terasic
# state-machine + 23-step transaction layout); imported via
# VERILOG_FILE rather than SYSTEMVERILOG_FILE.
# Ch161 — real Quartus IOPLL: 50 MHz refclk → 30 MHz outclk_0,
# generated from synth/.../ip/pll.ip via quartus_ipgenerate.
# The .qip below imports the IP's synth/sim files into the
# project; USE_PLL_IP=1 (set further down as a Verilog macro)
# tells the wrapper's `\`ifdef USE_PLL_IP` to instantiate the
# real `pll` module (matching the Ch151 stub's signature) in
# place of `de25_nano_pll_stub`.

# ----------------------------------------------------------------------------
# SDC — referenced by basename so the path resolves whether the
# Quartus project runs from the repo root OR (the Ch152 build
# script's choice) from a per-build work dir that symlinks the
# SDC alongside the QSF.
# ----------------------------------------------------------------------------

# ----------------------------------------------------------------------------
# Preprocessor macros
#
# BIOS / payload .mem paths — the bios_rom_stub / ee_ram_stub instances
# inside the Ch146 wrapper expand these macros at the $readmemh call.
# Paths are project-relative (Quartus runs from the project root). Ch147's
# bake.py produces both files; run `make -C sim top_psmct32_raster_demo_mem`
# before launching Quartus.
#
# To wire in Terasic's reset_release IP, also define
# USE_TERASIC_RESET_RELEASE_IP and add the IP file from the DE25-Nano
# Resource CD. Default-off keeps the RTL self-contained.
#
# Ch151 — to wire in a real Quartus IOPLL, define USE_PLL_IP and add
# the IP's .qip via `set_global_assignment -name QIP_FILE`. The board
# wrapper's `\`ifdef USE_PLL_IP` swaps the sim stub for the real
# `pll` module (signature: refclk / rst / outclk_0 / locked). With
# USE_PLL_IP undefined, the de25_nano_pll_stub passes refclk through
# and asserts `locked` after a 32-cycle warm-up — sufficient for
# elaborate-only / lint-only Quartus runs.
# ----------------------------------------------------------------------------
# ----------------------------------------------------------------------------
# Board demo image: the TEXTURED-TRIANGLE demo — a texture sampled across a
# non-axis-aligned triangle (U/V interpolated per-pixel, fed to the texel-fetch
# path; DECAL). Combines brick-1 texturing with brick-3 triangle geometry. Just
# compile in Quartus as usual; no scripts, no toggles. The .mem fixtures are
# committed (regenerate any time with
# `python3 sim/data/top_psmct32_raster_demo/bake.py`).
#   - Other demos: point the two paths below at bios_triangle/payload_triangle
#     (Gouraud triangle + depth), bios_zbuffer (sprite depth), bios_alpha (alpha),
#     bios_textured (textured PSMCT32 sprite), bios_tritex (textured triangle),
#     bios_clut (Ch296 PSMT8 INDEXED texture + CLUT), or bios_clut4 (Ch297
#     PSMT4 4-bit INDEXED texture + CLUT) — keep GS_RMW_DEMO=1.
#   - Flat 320x240 test card: point them at bios.mem / payload.mem and delete
#     the GS_RMW_DEMO line.
# GS_RMW_DEMO selects the read-modify-write demo profile (VRAM read port live +
# small framebuffer) shared by the texture / alpha / depth / triangle / CLUT demos.
# Ch301 default: the PERSPECTIVE-CORRECT textured-triangle demo
# (bios_persp/payload_persp) — a receding "floor" quad (2 TME TRIANGLEs)
# textured with a 4x4-cell checkerboard. Texture coords via ST (S=u/w, T=v/w) +
# RGBAQ.Q (=1/w); top edge FAR (w=8), bottom NEAR (w=1). GS_PERSP_DEMO sets
# PERSPECTIVE_CORRECT=1 on the bram top so the rasterizer recovers per-pixel
# (u,v)=(S/Q,T/Q) through the pipelined reciprocal LUT (gs_persp_uv, NO per-pixel
# divider) — the checkerboard COMPRESSES toward the far (top) edge; an affine
# build would space the cells evenly. Texture is LINEAR PSMCT32
# (PSMCT32_SWIZZLE=0), so perspective is isolated from the swizzle family.
#   - To revert to the Ch300 SWIZZLED PSMCT32 demo: point the two paths at
#     bios_swz32/payload_swz32 and use GS_SWZ32_DEMO instead of GS_PERSP_DEMO.
#   - Other swizzle demos: bios_swz8/swz4 + GS_SWZ8_DEMO/GS_SWZ4_DEMO. Linear
#     demos (bios_clut/textured/alpha/zbuffer/triangle/tritex) keep GS_RMW_DEMO
#     and drop the GS_*_DEMO line entirely.
# >>> DE25_PROFILE_FIXTURE (managed by scripts/select_de25_profile.sh — do not hand-edit) >>>
set_global_assignment -name VERILOG_MACRO "TOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE=\"sim/data/top_psmct32_raster_demo/bios_sh3_zs640c6.mem\""
set_global_assignment -name VERILOG_MACRO "TOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE=\"sim/data/top_psmct32_raster_demo/payload_sh3_zs640c6.mem\""
# <<< DE25_PROFILE_FIXTURE <<<
set_global_assignment -name VERILOG_MACRO "GS_RMW_DEMO=1"
# Ch305: MULTI-PRIMITIVE tiled scene over the 2x2 grid (3 combined prims per tile:
# opaque blue bg @ far Z, opaque red @ mid Z, translucent white @ near Z). Proves
# draw order + depth + alpha across tile seams (bios_tile_multiprim/payload_tile_multiprim).
# To go back to the single-primitive 2x2 grid: bios_tile2x2/payload_tile2x2 + GS_TILE2X2_DEMO.
# Ch306: SCISSOR-clipped tiled scene = Ch305 scene + SCISSOR_1 [9..22]x[6..20]
# (crosses both tile seams). Pixels outside the rect stay the clear color.
# Back to the unclipped multi-prim scene: bios_tile_multiprim/payload_tile_multiprim + GS_TILE_MULTIPRIM_DEMO.
# Ch307: texture WRAP modes = Ch305 tiled path + two textured prims, one REPEAT
# (texture tiles 2x -> two white stripes), one CLAMP (edge stretched -> one white
# stripe + long blue). Back to scissor: bios_tile_scissor + GS_TILE_SCISSOR_DEMO.
# Ch308: PSMCT16 tile color = Ch305 scene with the on-chip tile color RAM +
# framebuffer in 16-bit RGB5A1 (FRAME stays PSMCT32 for combined eligibility;
# DISPFB1.PSM=PSMCT16 + TILE_COLOR_PSMCT16=1). Back to wrap: bios_tile_wrap + GS_TILE_WRAP_DEMO.
# Ch309: ALPHA mode expansion = Ch305 scene with P1 ADDITIVE (Cs+Cd, magenta over
# blue) + P0/P2 source-over. Two blend modes coexist (ALPHA_MODES_ENABLE=1).
# Back to PSMCT16: bios_tile_psmct16 + GS_TILE_PSMCT16_DEMO.
# Ch310: BILINEAR in combined path = 4x4 blue/white checker magnified, LEFT tri
# TEX1.MMAG=0 (nearest, blocky), RIGHT tri MMAG=1 (linear, smoothed). 4-tap
# sampler stalls the per-pixel FSM ~9 cyc. Back to alpha: bios_tile_alpha + GS_TILE_ALPHA_DEMO.
# Ch311: per-tile BIN BUFFER = 3 prims (P0 all-tiles / P1 2-tiles / P2 1-tile);
# a binning pass precomputes per-tile prim lists, render walks the bin. Same image
# as Ch305 re-test. Back to bilinear: bios_tile_bilinear + GS_TILE_BILINEAR_DEMO.
# Ch312: 4x4 GRID (16 tiles, 64x64) via the bin buffer. P0 4-tile / P1 6-tile
# cross-seam / P2 1-tile + empty tiles. VRAM 32 KiB (PSMCT32 FB). Back to 2x2:
# bios_tile_bin + GS_TILE_BIN_DEMO.
# Ch313: FULL PSMCT16 FRAMEBUFFER — same 4x4 (64x64) scene but FRAME.PSM=PSMCT16,
# so the whole render/flush/scanout path is RGB5A1. A 64x64 PSMCT16 FB is 8 KiB
# (HALF the 16 KiB PSMCT32 FB) -> VRAM 16 KiB (vs Ch312's 32 KiB). This fit should
# show the framebuffer-memory SAVING (fewer RAM blocks). Back to the PSMCT32 4x4:
# bios_tile_bin4x4 + GS_TILE_BIN4X4_DEMO.
# Ch314: PALETTIZED BILINEAR — 4x4 PSMT8 INDEX checker (idx 0/1) + CLUT (0=blue,
# 1=white). LEFT tri MMAG=0 (nearest, blocky), RIGHT tri MMAG=1 (bilinear). Each
# bilinear tap CLUTs its index to a color THEN interpolates colors
# (CLUT-before-interp), so the RIGHT tri shows blue<->white midtones, the LEFT
# does not. Back to full-PSMCT16-FB: bios_tile_psmct16fb + GS_TILE_PSMCT16FB_DEMO.
# Ch315: PRIMITIVE/BIN CAPACITY — 4x4 grid, TILE_FIFO_DEPTH=8 (was 4), 7 prims; SIX
# overlap in tile t0 (bin depth 6 > old 4) + 1 corner prim in t15. The fit vs Ch312
# (depth-4 4x4) gives the resource SLOPE per capacity slot. Board: blue triangle in the
# top-left tile (6 prims deep) + blue corner triangle + green empties. Back to
# palettized-bilinear: bios_tile_palbilinear + GS_TILE_PALBILINEAR_DEMO.
# Ch316: LEADING-EMPTY-TILE fix — ONE prim ONLY in the last tile t15; tiles t0..t14
# empty and precede it. Proves the fix on silicon: early empty tiles show the GREEN
# clear (not black) and the renderer still reaches t15 (blue triangle bottom-right).
# Back to capacity: bios_tile_cap + GS_TILE_CAP_DEMO.
# ------------------------------------------------------------------------------
# Ch318: LPDDR framebuffer WRITE path on hardware. ONE bitstream — no rebuild to
# change mode. Scene = the full-PSMCT16-FB 4x4 demo (so the tile flush is PSMCT16,
# which the LPDDR AXI writer captures); GS_LPDDR_FB instantiates the writer and drives
# the qsys f2sdram port. ALL test controls are RUNTIME, via HPS bridge registers
# (defaults safe: arm OFF, canary ON, base 0x8000_0000) — the booted core is inert
# until the HPS arms it. Drive it with the ps2 LPDDR test script (see docs).
# Ch322 — LPDDR-backed TEXTURE demo (tritex scene). GS_LPDDR_TEX_DEMO selects the
# tritex u_demo profile; GS_LPDDR_TEX wires the prefilled LPDDR texture cache + HPS
# write-probe + 3:1 read arb + 2:1 write arb (all inert without the macro). To return
# to the Ch321 128x128 LPDDR scanout demo: restore GS_TILE_LPDDR128_DEMO=1, drop the
# two Ch322 macros, and point the .mem paths back at bios/payload_tile_lpddr128.
# >>> DE25_PROFILE_SCENE (managed by scripts/select_de25_profile.sh — do not hand-edit) >>>
set_global_assignment -name VERILOG_MACRO "GS_SH3_LPDDR_FB=1"
set_global_assignment -name VERILOG_MACRO "GS_SH3_LPDDR_FB_Z=1"
set_global_assignment -name VERILOG_MACRO "GS_SH3_LPDDR_FB_640=1"
set_global_assignment -name VERILOG_MACRO "GS_LPDDR_TEX=1"
# <<< DE25_PROFILE_SCENE <<<
set_global_assignment -name VERILOG_MACRO "GS_LPDDR_FB=1"
# Ch319 Brick 1 — bring up the FPGA-private LPDDR4B EMIF (EMIF_Qsys) + prove calibration.
# AXI user port tied off this brick; LED[7] lit = LPDDR4B calibrated.
set_global_assignment -name VERILOG_MACRO "GS_LPDDR4B_FB=1"
# Ch302: COMBINED textured+alpha+depth probe (bios_combined/payload_combined).
# One TME+ABE+ZTE triangle over a green Z-bg: top half passes depth (translucent
# texture blended over green), bottom half occluded (green). To revert to the
# Ch301b perspective floor: point the two paths at bios_persp_floor/payload_persp_floor
# and use GS_PERSP_DEMO instead of GS_COMBINED_DEMO.
# Ch301b: the persp-FLOOR fixture (trapezoid from ONE projected plane -> a
# recognizable receding checkerboard). Same GS_PERSP_DEMO profile as the Ch301
# divide-stress fixture (bios_persp/payload_persp); only the *.mem differ.

# Ch161 — swap the Ch151 PLL stub for the real Quartus IOPLL IP
# (synth/.../ip/pll.ip + pll.qip). Defining `USE_PLL_IP` flips
# the wrapper's `\`ifdef` so `module pll` (the IP-generated
# IOPLL with refclk/rst/outclk_0/locked ports) is instantiated
# in place of `de25_nano_pll_stub`. The IP is configured for
# 50 MHz refclk → 30 MHz outclk_0 — the actual hardware-running
# design clock now matches the Ch160 SDC's down-clock target,
# so the .sof is genuinely 30 MHz on the DE25-Nano (not just
# constrained to look like 30 MHz).
set_global_assignment -name VERILOG_MACRO "USE_PLL_IP=1"
# Ch170 — gate the qsys_top + ps2_hps_bridge_null instantiation
# into the synth path. Sim leaves USE_QSYS_TOP undefined, so the
# inline ninit_done stub drives instead of qsys, and the bridge
# block is `ifdef-ed out (avoids elaborating a black-hole AXI
# master from qsys_top_bb.v in sim).
set_global_assignment -name VERILOG_MACRO "USE_QSYS_TOP=1"

# ----------------------------------------------------------------------------
# Ch170 — preserve the f2sdram path through the HPS Sundancemesa MPFE.
# When the f2sdram AXI master is tied off (we don't use the HPS-side
# DDR from our fabric), Quartus's optimizer tries to remove the
# bridge — but the MPFE is a hardened primitive that can't be
# optimized, so synthesis fails with
# "F2SDRAM_RDATA is not legally connected and/or configured".
# These preserves tell Quartus to keep the f2sdram registers and
# fanout-free nodes alive. Verbatim from retroDE_Atari2600.qsf.
# ----------------------------------------------------------------------------
set_instance_assignment -name PRESERVE_REGISTER ON -to soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_mpfe|sundancemesa_mpfe_ready_latency_adp_inst_f2sdram|* -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE ON -to soc_inst|subsys_hps|agilex_hps|intel_agilex_5_soc_inst|sm_mpfe|*f2sdram* -entity de25_nano_psmct32_raster_demo_top

# ----------------------------------------------------------------------------
# Init clock for FPGA configuration (matches retroDE_splash convention)
# ----------------------------------------------------------------------------
# ----------------------------------------------------------------------------
# Ch170 — HPS-first configuration scheme (sourced from
# retroDE_Atari2600/retroDE_a2600.qsf). REQUIRED for the agilex_hps
# IP's LPDDR4 EMIF + f2sdram bridge to elaborate; without
# `HPS_INITIALIZATION "HPS FIRST"` the Sundancemesa MPFE primitive
# fails synth with "F2SDRAM_RDATA is not legally connected and/or
# configured" because the IP expects HPS-driven boot-time setup, not
# fabric-driven config.
# ----------------------------------------------------------------------------
set_global_assignment -name HPS_INITIALIZATION "HPS FIRST"
# Area-focused synthesis — the fitter is constrained by LAB placement, so
# optimize for area and permit arithmetic/resource sharing.  Ch439f compiled
# AUTO_RESOURCE_SHARING=OFF from fresh synthesis through route and produced an
# identical netlist, resource count, placement, and timing path; sharing was
# therefore not the source of the tap-to-texture-cache STA arc.
# AGGRESSIVE AREA keeps the long texture-address combinational paths (e.g. vert_count -> u_texcache RAM)
# placed compactly enough to meet the 25 MHz design clock (+0.631 ns). A global switch to BALANCED closed
# the EMIF path but blew that design-clock path to -6.119 ns (a 6.7 ns placement swing), so DON'T change the
# global mode. Instead close the one 310 MHz EMIF miss surgically via the MAX_FANOUT below.
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE AREA"
# Ch415: the 8K Z-req FIFO read-address register u_zc_emit|u_req|raddr_hi1_q fans out to ~6 spread M20K blocks
# and missed 310 MHz EMIF setup by 103 ps (Quartus TMC-20551 asked for more register duplication, which the
# AGGRESSIVE AREA global mode suppresses). Force duplication of JUST this register so each copy drives a nearby
# block cluster -> shorter routing. Surgical (no global area/placement disruption); ~a few ALMs.
set_instance_assignment -name MAX_FANOUT 3 -to "u_zc_emit|u_req|raddr_hi1_q*"
set_global_assignment -name AUTO_RESOURCE_SHARING ON
# Ch357 (Codex) — historical: at that netlist seed 1 gave -0.019 (quasi-static EMIF-lock only), seed 2 was worse.
# Ch443d (Codex) — after the AW/W/R buffers + F_SETTLE drain multicycle froze the functional netlist at 6319d7c,
# the residual failure was a placement/route-marginal EMIF path (zc_emit QUAD_WIDTH4 Z-req FIFO read, ~-0.087,
# 3.132ns data / -0.100 skew vs 3.225ns period). A bounded 4-seed sweep (fit+STA, AGGRESSIVE AREA kept) resolved it:
#   seed2 -0.087 | seed3 +0.132 (0 violated, ALL classes >=0) | seed4 +0.062 | seed5 -0.130.
# SEED 3 is the reproducibility setting: EMIF setup +0.132 (>= +0.100 margin), no AWREADY/texcache-fill/drain/
# scanout-diag violations, RAM 317/358, ALM 85%. This is a fitter placement seed, NOT an RTL/timing-mode change.
set_global_assignment -name SEED 3
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_125MHZ
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name USE_HPS_COLD_RESET SDM_IO11
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name LAST_QUARTUS_VERSION "26.1.0 Pro Edition"

# ----------------------------------------------------------------------------
# Ch168 — HPS-first boot artifact generation (matches retroDE_nes /
# retroDE_splash). Runs `post_flow.tcl` after Assembler to produce
# `output_files/<rev>.core.rbf` (fabric-only RBF for the on-board loader),
# the merged `_hps.sof`, the `_hps.jic` for QSPI flash, and the `.hps.rbf`.
# The script resolves the shared HPS u-boot SPL hex relative to its own
# location (../../../../retroDE_splash/software/u-boot/spl/u-boot-spl-dtb.hex).
# ----------------------------------------------------------------------------
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:post_flow.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/debug/trace_pkg.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/bios_rom_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/ee_ram_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/ee_memory_map_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ee/ee_core_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/ee_gs_priv_bridge_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dmac/dmac_reg_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gif_packed_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_grad_divider.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_prim_list_feeder.sv
# Brick 1 — texture sampler (instantiated inside gs_stub). Without these the
# textured build fails to elaborate; harmless to the flat build (TME=0).
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_texel_addr.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_texture_unit.sv
# Ch301 — perspective-correct texture interpolation (pipelined reciprocal LUT +
# per-pixel divide), instantiated inside gs_stub when PERSPECTIVE_CORRECT=1.
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_reciprocal_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_persp_uv.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_tile_ram.sv
# Brick 2a — alpha-blend (transparency) unit, instantiated inside gs_stub.
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_alpha_blend.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_color_blend.sv
# Ch317/Ch318 — LPDDR framebuffer paths. gs_lpddr_axi_master (+ gs_async_fifo) is the
# board write path (GS_LPDDR_FB); gs_lpddr_fb_writer is the Ch317 sim model, gen-guarded
# OFF (LPDDR_FB_ENABLE=0) in the board build but listed so the source set is complete.
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_async_fifo.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_axi_master.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_fb_writer.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_rd_probe.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_scanout.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_rd_arb.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_scanout_lb.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_texture_cache.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_wr_probe.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_wr_arb.sv
# Ch323 — tile COLOR+Z spill/reload (instantiated under GS_TILE_SPILL; idle otherwise).
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_z_flush_writer.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_tile_reload.sv
# Ch357 — persistent-Z ROP (instantiated under GS_SH3_LPDDR_FB_Z; idle otherwise). map_pkg first (package).
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_map_pkg.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_z_rmw.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_axi_w_regbuf.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_axi_aw_regbuf.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_axi_r_regbuf.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_zc_emit.sv
# ----------------------------------------------------------------------------
# Design RTL added during the EE/qbert chapters (Ch287+) that reached the demo
# hierarchy (via ee_memory_map_stub) but were only added to the SIM build, not
# this synth QSF — so the board project was missing them. Restores the synth
# RTL set to match the sim's proven set so elaboration finds every entity.
# ----------------------------------------------------------------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/debug/trace_sink_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dmac/ee_dmac_ctrl_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dmac/ee_dmac_passive_chan_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ee/ee_biu_mmio_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ee/ee_bootstrap_mmio_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ee/ee_fetch_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/clut_loader_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/clut_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gif_path_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/intc/intc_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/iop/iop_core_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/iop/iop_dmac_reg_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/iop/iop_exec_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/iop/iop_fetch_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/iop/iop_memory_map_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/iop/iop_ram_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/platform_video_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/boot_install_agent_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/sif_dma_ack_peer_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/sif_dma_ee_ack_peer_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/sif_dma_ee_ram_bridge_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/sif_dma_iop_ram_bridge_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/sif_dma_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/sif_mailbox_peer_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sif/sif_mailbox_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gif_image_xfer_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/vram_normalize_pkg.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/vram_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/vram_bram_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_pcrtc_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_swizzle_psmct32_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_swizzle_psmct16_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_swizzle_psmt8_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_swizzle_psmt4_stub.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/top_psmct32_raster_demo.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/top_psmct32_raster_demo_bram.sv
set_global_assignment -name VERILOG_FILE rtl/platform/I2C_Controller.v
set_global_assignment -name VERILOG_FILE rtl/platform/I2C_HDMI_Config.v
# Ch170 — minimal null AXI4 slave for the qsys hps2fpga bridge.
set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/ps2_hps_bridge_null.sv
# Ch173 — real read-only status bridge replacing the null bridge on
# the hps2fpga AXI slave. Read-only AXI4 register surface:
#   0x000 CORE_ID=0x50533200, 0x004 ABI_VERSION=0x100, 0x008 CORE_STATUS,
#   0x00C CORE_CAPS, 0x010/0x014 CORE_CTRL/CORE_PULSE (read-zero stubs),
#   0x020 FRAME_COUNT, 0x024 DMA_DONE_COUNT, 0x028 RASTER_OVERFLOW_COUNT.
set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/ps2_hps_bridge.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/clut_stage_cdc.sv
# Ch250 — PS2-fabric input consumer. Brings sio2_input_stub onto the
# synth top so bridge_input_p1_raw reaches a live fabric reader (Ch234
# built this module sim-only; Ch241 documented that the synth top
# elided the path; Ch250 ends that elision). The stub's IOP-side
# read/write ports are tied to zero in the top because no IOP execution
# fabric is on silicon yet — only the parallel `p1_sony_word_o` tap is
# consumed (drives LED[5/6/7]).
set_global_assignment -name SYSTEMVERILOG_FILE rtl/iop/sio2_input_stub.sv

# Ch229 — design-clock shadow RAM mirroring the bridge's tile_mem via
# a toggle-based CDC. Bridge broadcasts {tile_wr_toggle, index, data}
# on each AXI write into 0x1000..0x1FFF; the Ch245 platform-OSD char-
# BRAM read adapter in the top selects high/low 16-bit cells from the
# 32-bit shadow words this module exposes. (Ch228..Ch244 retroDE_ps2-
# local `osd_overlay_stub.sv` retired in Ch249.)
set_global_assignment -name SYSTEMVERILOG_FILE rtl/platform/tile_ram_cdc.sv

# Ch245 — adopt shared platform OSD stack. Referenced directly from
# retroDE_splash (the platform chassis), matching how every sibling
# core (NES, Atari2600, ao486, CoCo2, GB) consumes it. Do NOT copy —
# any platform-side fix must reach this core through git in
# retroDE_splash.
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../retroDE_splash/rtl/platform/osd_overlay.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../retroDE_splash/rtl/platform/osd_font_rom.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../retroDE_splash/rtl/platform/osd_menu_fsm.sv
set_global_assignment -name MIF_FILE ../../../../retroDE_splash/rtl/platform/cp437_8x8.mem

# Ch248 — replace the Ch226 fake DS2 bridge stub with the shared
# platform DS2 controller. Sibling cores (NES, etc.) instantiate this
# same RTL and feed `ds2_connected/error/buttons` into their bridge so
# retrodesd's ds2_poll_thread can see the wired controller.
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../retroDE_splash/rtl/platform/ds2_controller.sv

# Ch248 — DS2 wired-controller GPIO pin assignments. Match NES/splash
# verbatim (same DE25-Nano GPIO header, same `3.3-V LVCMOS` I/O
# standard, same weak pull-up on DATA — the controller drives that
# line through an open-drain that needs a pull-up to idle high).
set_location_assignment PIN_H16 -to GPIO_0_DS2_CLK
set_location_assignment PIN_Y1 -to GPIO_0_DS2_CMD
set_location_assignment PIN_C2 -to GPIO_0_DS2_DATA
set_location_assignment PIN_P1 -to GPIO_0_DS2_ATTN
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0_DS2_CLK -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0_DS2_CMD -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0_DS2_DATA -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0_DS2_ATTN -entity de25_nano_psmct32_raster_demo_top
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPIO_0_DS2_DATA -entity de25_nano_psmct32_raster_demo_top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/de25_nano_pll_stub.sv
# Ch170 — reference the .ip source (not the cached .qip output) so
# Quartus regenerates the PLL when the frequency in pll.ip changes.
# Otherwise edits to pll.ip's gui_output_clock_frequency0 silently
# get ignored because Quartus picks up the stale generated artifacts.
set_global_assignment -name IP_FILE ip/pll.ip
# Ch170 — canonical retroDE qsys platform shell. The .ip files are the
# generated PLL/reset/clkgate components inside qsys_top, plus the HPS
# hard-IP wrapper and the LPDDR4 EMIF; the .qsys files are the Platform
# Designer system definitions Quartus regenerates at synthesis time when
# any of them changes. Mirrors retroDE_Atari2600 / retroDE_nes verbatim.
set_global_assignment -name IP_FILE qsys/ip/qsys_top/clk_100.ip
set_global_assignment -name IP_FILE qsys/ip/qsys_top/rst_in.ip
set_global_assignment -name IP_FILE qsys/ip/qsys_top/user_rst_clkgate_0.ip
set_global_assignment -name IP_FILE qsys/hps_subsys/ip/hps_subsys/agilex_hps.ip
set_global_assignment -name IP_FILE qsys/hps_subsys/ip/qsys_top/emif_io96b_hps.ip
# peripheral_subsys IP components (sysid + PIOs + Nios CPU + clk/rst).
# Missing any of these makes peripheral_subsys instantiate "undefined
# entity" stubs and elaboration fails.
set_global_assignment -name IP_FILE qsys/peripheral_subsys/ip/peripheral_subsys/sysid.ip
set_global_assignment -name IP_FILE qsys/peripheral_subsys/ip/peripheral_subsys/led_pio.ip
set_global_assignment -name IP_FILE qsys/peripheral_subsys/ip/peripheral_subsys/button_pio.ip
set_global_assignment -name IP_FILE qsys/peripheral_subsys/ip/peripheral_subsys/dipsw_pio.ip
set_global_assignment -name IP_FILE qsys/peripheral_subsys/ip/peripheral_subsys/pb_cpu_0.ip
set_global_assignment -name IP_FILE qsys/peripheral_subsys/ip/peripheral_subsys/periph_clk.ip
set_global_assignment -name IP_FILE qsys/peripheral_subsys/ip/peripheral_subsys/periph_rst_in.ip
set_global_assignment -name QSYS_FILE qsys/qsys_top.qsys
set_global_assignment -name QSYS_FILE qsys/hps_subsys/hps_subsys.qsys
set_global_assignment -name QSYS_FILE qsys/peripheral_subsys/peripheral_subsys.qsys
# Ch319 — FPGA-private LPDDR4B EMIF (EMIF_Qsys), cloned from de25_lpddr4_bw/ao486 (same device).
set_global_assignment -name QSYS_FILE ip/emif_lpddr4b/EMIF_Qsys.qsys
set_global_assignment -name IP_FILE ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0.ip
set_global_assignment -name IP_FILE ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip
set_global_assignment -name IP_FILE ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_iopll_0.ip
set_global_assignment -name IP_FILE ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_reset_in.ip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/de25_nano_psmct32_raster_demo_top.sv
set_global_assignment -name SDC_FILE de25_nano_psmct32_raster_demo_top.sdc
