Info: Generated by version: 25.3.1 build 100
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_iopll_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_iopll_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: EMIF_Qsys_iopll_0.iopll_0: Able to implement PLL with user settings
Info: EMIF_Qsys_iopll_0: "Transforming system: EMIF_Qsys_iopll_0"
Info: EMIF_Qsys_iopll_0: "Naming system components in system: EMIF_Qsys_iopll_0"
Info: EMIF_Qsys_iopll_0: "Processing generation queue"
Info: EMIF_Qsys_iopll_0: "Generating: EMIF_Qsys_iopll_0"
Info: EMIF_Qsys_iopll_0: "Generating: EMIF_Qsys_iopll_0_altera_iopll_2100_iatcmyy"
Info: EMIF_Qsys_iopll_0: Done "EMIF_Qsys_iopll_0" with 2 modules, 6 files
Info: Finished: Create HDL design files for synthesis
