Info: Generated by version: 26.1 build 110
Info: Starting: Create simulation model
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
Info: EMIF_Qsys_emif_ddr4a_0: "Transforming system: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Naming system components in system: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Processing generation queue"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei"
Info: cal_0: "Generating: cal_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq"
Info: jamb: "Generating: jamb"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_jtag_interface"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_bytes_to_packets"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_packets_to_bytes"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_packets_to_master"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_reset_controller"
Info: EMIF_Qsys_emif_ddr4a_0: Done "EMIF_Qsys_emif_ddr4a_0" with 15 modules, 159 files
Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for specified device family. Use VCS-MX or another supported simulator.
Info: Generating the following file(s) for MODELSIM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	common/modelsim_files.tcl
Info: Generating the following file(s) for RIVIERA simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	common/riviera_files.tcl
Info: Generating the following file(s) for VCSMX simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	common/vcsmx_files.tcl
Info: Generating the following file(s) for XCELIUM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	common/xcelium_files.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create simulation model
Info: Starting: Create simulation script
Info: sim-script-gen --system-file=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ --use-relative-paths=true
Warning: Skipping generation of synopsys/vcs/vcs_setup.sh since VCS 2-step flow is not supported for specified device family. Use VCS-MX or another supported simulator.
Info: Generating the following file(s) for MODELSIM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	mentor/msim_setup.tcl
Info: 	mentor/run_msim_setup.tcl
Info: Generating the following file(s) for RIVIERA simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	aldec/rivierapro_setup.tcl
Info: 	aldec/run_rivierapro_setup.tcl
Info: Generating the following file(s) for VCSMX simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	synopsys/vcsmx/_device_synopsys_sim.setup
Info: 	synopsys/vcsmx/synopsys_sim.setup
Info: 	synopsys/vcsmx/vcsmx_setup.sh
Info: Generating the following file(s) for XCELIUM simulator in /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/ directory:
Info: 	xcelium/cds.lib
Info: 	xcelium/hdl.var
Info: 	xcelium/xcelium_setup.sh
Info: 	13 .cds.lib files in xcelium/cds_libs/ directory
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0/sim/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create simulation script
Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --block-symbol-file --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ao486/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
Info: EMIF_Qsys_emif_ddr4a_0: "Transforming system: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Naming system components in system: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Processing generation queue"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei"
Info: cal_0: "Generating: cal_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq"
Info: jamb: "Generating: jamb"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_jtag_interface"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_bytes_to_packets"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_packets_to_bytes"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_packets_to_master"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_reset_controller"
Info: EMIF_Qsys_emif_ddr4a_0: Done "EMIF_Qsys_emif_ddr4a_0" with 15 modules, 165 files
Info: Finished: Create HDL design files for synthesis
