Info: Generated by version: 25.3.1 build 100
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0 --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.
Info: EMIF_Qsys_emif_ddr4a_0: "Transforming system: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Naming system components in system: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Processing generation queue"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_411_5rak7ri"
Info: cal_0: "Generating: cal_0"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_411_yhgkgsq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_231_ihlvdea"
Info: jamb: "Generating: jamb"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_jtag_interface"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_bytes_to_packets"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_st_packets_to_bytes"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_avalon_packets_to_master"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a"
Info: EMIF_Qsys_emif_ddr4a_0: "Generating: altera_reset_controller"
Info: EMIF_Qsys_emif_ddr4a_0: Done "EMIF_Qsys_emif_ddr4a_0" with 15 modules, 165 files
Info: Finished: Create HDL design files for synthesis
