	component EMIF_Qsys_emif_io96b_lpddr4_0 is
		port (
			s0_axi4_clock_in    : in    std_logic                      := 'X';             -- clk
			core_init_n         : in    std_logic                      := 'X';             -- reset_n
			s0_axi4_reset_n     : out   std_logic;                                         -- reset_n
			s0_axi4_awaddr      : in    std_logic_vector(29 downto 0)  := (others => 'X'); -- awaddr
			s0_axi4_awburst     : in    std_logic_vector(1 downto 0)   := (others => 'X'); -- awburst
			s0_axi4_awid        : in    std_logic_vector(6 downto 0)   := (others => 'X'); -- awid
			s0_axi4_awlen       : in    std_logic_vector(7 downto 0)   := (others => 'X'); -- awlen
			s0_axi4_awlock      : in    std_logic                      := 'X';             -- awlock
			s0_axi4_awqos       : in    std_logic_vector(3 downto 0)   := (others => 'X'); -- awqos
			s0_axi4_awsize      : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- awsize
			s0_axi4_awvalid     : in    std_logic                      := 'X';             -- awvalid
			s0_axi4_awuser      : in    std_logic_vector(13 downto 0)  := (others => 'X'); -- awuser
			s0_axi4_awprot      : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- awprot
			s0_axi4_awready     : out   std_logic;                                         -- awready
			s0_axi4_araddr      : in    std_logic_vector(29 downto 0)  := (others => 'X'); -- araddr
			s0_axi4_arburst     : in    std_logic_vector(1 downto 0)   := (others => 'X'); -- arburst
			s0_axi4_arid        : in    std_logic_vector(6 downto 0)   := (others => 'X'); -- arid
			s0_axi4_arlen       : in    std_logic_vector(7 downto 0)   := (others => 'X'); -- arlen
			s0_axi4_arlock      : in    std_logic                      := 'X';             -- arlock
			s0_axi4_arqos       : in    std_logic_vector(3 downto 0)   := (others => 'X'); -- arqos
			s0_axi4_arsize      : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- arsize
			s0_axi4_arvalid     : in    std_logic                      := 'X';             -- arvalid
			s0_axi4_aruser      : in    std_logic_vector(13 downto 0)  := (others => 'X'); -- aruser
			s0_axi4_arprot      : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- arprot
			s0_axi4_arready     : out   std_logic;                                         -- arready
			s0_axi4_wdata       : in    std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
			s0_axi4_wstrb       : in    std_logic_vector(31 downto 0)  := (others => 'X'); -- wstrb
			s0_axi4_wlast       : in    std_logic                      := 'X';             -- wlast
			s0_axi4_wvalid      : in    std_logic                      := 'X';             -- wvalid
			s0_axi4_wready      : out   std_logic;                                         -- wready
			s0_axi4_bready      : in    std_logic                      := 'X';             -- bready
			s0_axi4_bid         : out   std_logic_vector(6 downto 0);                      -- bid
			s0_axi4_bresp       : out   std_logic_vector(1 downto 0);                      -- bresp
			s0_axi4_bvalid      : out   std_logic;                                         -- bvalid
			s0_axi4_rready      : in    std_logic                      := 'X';             -- rready
			s0_axi4_rdata       : out   std_logic_vector(255 downto 0);                    -- rdata
			s0_axi4_rid         : out   std_logic_vector(6 downto 0);                      -- rid
			s0_axi4_rlast       : out   std_logic;                                         -- rlast
			s0_axi4_rresp       : out   std_logic_vector(1 downto 0);                      -- rresp
			s0_axi4_rvalid      : out   std_logic;                                         -- rvalid
			s0_axi4lite_clock   : in    std_logic                      := 'X';             -- clk
			s0_axi4lite_reset_n : in    std_logic                      := 'X';             -- reset_n
			s0_axi4lite_awaddr  : in    std_logic_vector(26 downto 0)  := (others => 'X'); -- awaddr
			s0_axi4lite_awprot  : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- awprot
			s0_axi4lite_awvalid : in    std_logic                      := 'X';             -- awvalid
			s0_axi4lite_awready : out   std_logic;                                         -- awready
			s0_axi4lite_araddr  : in    std_logic_vector(26 downto 0)  := (others => 'X'); -- araddr
			s0_axi4lite_arprot  : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- arprot
			s0_axi4lite_arvalid : in    std_logic                      := 'X';             -- arvalid
			s0_axi4lite_arready : out   std_logic;                                         -- arready
			s0_axi4lite_wdata   : in    std_logic_vector(31 downto 0)  := (others => 'X'); -- wdata
			s0_axi4lite_wstrb   : in    std_logic_vector(3 downto 0)   := (others => 'X'); -- wstrb
			s0_axi4lite_wvalid  : in    std_logic                      := 'X';             -- wvalid
			s0_axi4lite_wready  : out   std_logic;                                         -- wready
			s0_axi4lite_bready  : in    std_logic                      := 'X';             -- bready
			s0_axi4lite_bresp   : out   std_logic_vector(1 downto 0);                      -- bresp
			s0_axi4lite_bvalid  : out   std_logic;                                         -- bvalid
			s0_axi4lite_rready  : in    std_logic                      := 'X';             -- rready
			s0_axi4lite_rdata   : out   std_logic_vector(31 downto 0);                     -- rdata
			s0_axi4lite_rresp   : out   std_logic_vector(1 downto 0);                      -- rresp
			s0_axi4lite_rvalid  : out   std_logic;                                         -- rvalid
			mem_0_cs            : out   std_logic_vector(0 downto 0);                      -- mem_cs
			mem_0_ca            : out   std_logic_vector(5 downto 0);                      -- mem_ca
			mem_0_cke           : out   std_logic_vector(0 downto 0);                      -- mem_cke
			mem_0_dq            : inout std_logic_vector(31 downto 0)  := (others => 'X'); -- mem_dq
			mem_0_dqs_t         : inout std_logic_vector(3 downto 0)   := (others => 'X'); -- mem_dqs_t
			mem_0_dqs_c         : inout std_logic_vector(3 downto 0)   := (others => 'X'); -- mem_dqs_c
			mem_0_dmi           : inout std_logic_vector(3 downto 0)   := (others => 'X'); -- mem_dmi
			mem_0_ck_t          : out   std_logic_vector(0 downto 0);                      -- mem_ck_t
			mem_0_ck_c          : out   std_logic_vector(0 downto 0);                      -- mem_ck_c
			mem_0_reset_n       : out   std_logic;                                         -- mem_reset_n
			oct_rzqin_0         : in    std_logic                      := 'X';             -- oct_rzqin
			ref_clk             : in    std_logic                      := 'X'              -- clk
		);
	end component EMIF_Qsys_emif_io96b_lpddr4_0;

