<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="EMIF_Qsys" kind="EMIF_Qsys" version="1.0" fabric="QSYS">
 <!-- Format version 25.3.1 100 (Future versions may contain additional information.) -->
 <!-- 2026.03.02.19:16:04 -->
 <!-- A collection of modules and connections -->
 <parameter name="AUTO_GENERATION_ID">
  <type>java.lang.Integer</type>
  <value>0</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>GENERATION_ID</sysinfo_type>
 </parameter>
 <parameter name="AUTO_UNIQUE_ID">
  <type>java.lang.String</type>
  <value></value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>UNIQUE_ID</sysinfo_type>
 </parameter>
 <parameter name="AUTO_DEVICE_FAMILY">
  <type>java.lang.String</type>
  <value>Agilex 5</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
 </parameter>
 <parameter name="AUTO_DEVICE">
  <type>java.lang.String</type>
  <value>A5EB013BB23BE4SCS</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>DEVICE</sysinfo_type>
 </parameter>
 <parameter name="AUTO_DEVICE_SPEEDGRADE">
  <type>java.lang.String</type>
  <value>4</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
 </parameter>
 <parameter name="AUTO_BOARD">
  <type>java.lang.String</type>
  <value>default</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>BOARD</sysinfo_type>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_S0_AXI4_CPU_INFO_ID">
  <type>java.lang.String</type>
  <value></value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CPU_INFO_ID</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_s0_axi4</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_S0_AXI4LITE_CLOCK_CLOCK_RATE">
  <type>java.lang.Long</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CLOCK_RATE</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_s0_axi4lite_clock</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_S0_AXI4LITE_CLOCK_CLOCK_DOMAIN">
  <type>java.lang.Integer</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_s0_axi4lite_clock</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_S0_AXI4LITE_CLOCK_RESET_DOMAIN">
  <type>java.lang.Integer</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_s0_axi4lite_clock</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_S0_AXI4LITE_CPU_INFO_ID">
  <type>java.lang.String</type>
  <value></value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CPU_INFO_ID</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_s0_axi4lite</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_REF_CLK_CLOCK_RATE">
  <type>java.lang.Long</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CLOCK_RATE</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_ref_clk</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_REF_CLK_CLOCK_DOMAIN">
  <type>java.lang.Integer</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_ref_clk</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_EMIF_LPDDR4B_REF_CLK_RESET_DOMAIN">
  <type>java.lang.Integer</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
  <sysinfo_arg>emif_lpddr4b_ref_clk</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_IOPLL_REFCLK_CLOCK_RATE">
  <type>java.lang.Long</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CLOCK_RATE</sysinfo_type>
  <sysinfo_arg>iopll_refclk</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_IOPLL_REFCLK_CLOCK_DOMAIN">
  <type>java.lang.Integer</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
  <sysinfo_arg>iopll_refclk</sysinfo_arg>
 </parameter>
 <parameter name="AUTO_IOPLL_REFCLK_RESET_DOMAIN">
  <type>java.lang.Integer</type>
  <value>-1</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>RESET_DOMAIN</sysinfo_type>
  <sysinfo_arg>iopll_refclk</sysinfo_arg>
 </parameter>
 <parameter name="deviceFamily">
  <type>java.lang.String</type>
  <value>Agilex 5</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>false</visible>
  <valid>true</valid>
  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
 </parameter>
 <parameter name="generateLegacySim">
  <type>boolean</type>
  <value>false</value>
  <derived>false</derived>
  <enabled>true</enabled>
  <visible>true</visible>
  <valid>true</valid>
 </parameter>
 <module
   name="clock_310m"
   kind="altera_clock_bridge"
   version="19.2.0"
   entity="EMIF_Qsys_clock_bridge_0"
   library="EMIF_Qsys_clock_bridge_0"
   path="clock_310m"
   hpath="clock_310m"
   className="altera_generic_component">
  <!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
  <parameter name="componentDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
   <value><![CDATA[<componentDefinition>
    <boundary>
        <interfaces>
            <interface>
                <name>in_clk</name>
                <type>clock</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>in_clk</name>
                        <role>clk</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>clockRate</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>out_clk</name>
                <type>clock</type>
                <isStart>true</isStart>
                <ports>
                    <port>
                        <name>out_clk</name>
                        <role>clk</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedDirectClock</key>
                            <value>in_clk</value>
                        </entry>
                        <entry>
                            <key>clockRate</key>
                            <value>310000000</value>
                        </entry>
                        <entry>
                            <key>clockRateKnown</key>
                            <value>true</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
        </interfaces>
    </boundary>
    <originalModuleInfo>
        <className>altera_clock_bridge</className>
        <version>19.2.0</version>
        <displayName>Clock Bridge IP</displayName>
    </originalModuleInfo>
    <systemInfoParameterDescriptors>
        <descriptors>
            <descriptor>
                <parameterDefaultValue>0</parameterDefaultValue>
                <parameterName>DERIVED_CLOCK_RATE</parameterName>
                <parameterType>java.lang.Long</parameterType>
                <systemInfoArgs>in_clk</systemInfoArgs>
                <systemInfotype>CLOCK_RATE</systemInfotype>
            </descriptor>
        </descriptors>
    </systemInfoParameterDescriptors>
    <systemInfos>
        <connPtSystemInfos>
            <entry>
                <key>in_clk</key>
                <value>
                    <connectionPointName>in_clk</connectionPointName>
                    <suppliedSystemInfos/>
                    <consumedSystemInfos>
                        <entry>
                            <key>CLOCK_RATE</key>
                            <value>310000000</value>
                        </entry>
                    </consumedSystemInfos>
                </value>
            </entry>
            <entry>
                <key>out_clk</key>
                <value>
                    <connectionPointName>out_clk</connectionPointName>
                    <suppliedSystemInfos>
                        <entry>
                            <key>CLOCK_RATE</key>
                            <value>310000000</value>
                        </entry>
                    </suppliedSystemInfos>
                    <consumedSystemInfos/>
                </value>
            </entry>
        </connPtSystemInfos>
    </systemInfos>
</componentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generationInfoDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
   <value><![CDATA[<generationInfoDefinition>
    <hdlLibraryName>EMIF_Qsys_clock_bridge_0</hdlLibraryName>
    <fileSets>
        <fileSet>
            <fileSetName>EMIF_Qsys_clock_bridge_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_clock_bridge_0</fileSetFixedName>
            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_clock_bridge_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_clock_bridge_0</fileSetFixedName>
            <fileSetKind>SIM_VERILOG</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_clock_bridge_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_clock_bridge_0</fileSetFixedName>
            <fileSetKind>SIM_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_clock_bridge_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_clock_bridge_0</fileSetFixedName>
            <fileSetKind>CDC</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_clock_bridge_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_clock_bridge_0</fileSetFixedName>
            <fileSetKind>CDC_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
    </fileSets>
</generationInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hlsFile">
   <type>java.lang.String</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="logicalView">
   <type>java.lang.String</type>
   <value>ip/EMIF_Qsys/EMIF_Qsys_clock_bridge_0.ip</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="defaultBoundary">
   <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
   <value><![CDATA[<boundaryDefinition>
    <interfaces>
        <interface>
            <name>in_clk</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>in_clk</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>out_clk</name>
            <type>clock</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>out_clk</name>
                    <role>clk</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedDirectClock</key>
                        <value>in_clk</value>
                    </entry>
                    <entry>
                        <key>clockRate</key>
                        <value>310000000</value>
                    </entry>
                    <entry>
                        <key>clockRateKnown</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
    </interfaces>
</boundaryDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="moduleAssignmentDefinition">
   <type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
   <value><![CDATA[<assignmentDefinition>
    <assignmentValueMap/>
</assignmentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="svInterfaceDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hdlParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
   <value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="transformParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
   <value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuInfo">
   <type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="bspCpu">
   <type>java.lang.Boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="liveModuleName">
   <type>java.lang.String</type>
   <value>clock_bridge_0</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuHashInfo">
   <type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
   <value><![CDATA[<cpuHashInfoDefinition>
    <cpuHashInfoMap/>
</cpuHashInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="DERIVED_CLOCK_RATE">
   <type>java.lang.Long</type>
   <value>310000000</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RATE</sysinfo_type>
   <sysinfo_arg>in_clk</sysinfo_arg>
  </parameter>
  <parameter name="AUTO_DEVICE_FAMILY">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="AUTO_DEVICE">
   <type>java.lang.String</type>
   <value>A5EB013BB23BE4SCS</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <interface name="in_clk" kind="clock_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRateKnown">
    <type>java.lang.Boolean</type>
    <value>true</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRate">
    <type>java.lang.Long</type>
    <value>310000000</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>in_clk</name>
    <direction>Input</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
  <interface name="out_clk" kind="clock_source" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedDirectClock">
    <type>java.lang.String</type>
    <value>in_clk</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRate">
    <type>long</type>
    <value>310000000</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRateKnown">
    <type>boolean</type>
    <value>true</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>true</isStart>
   <port>
    <name>out_clk</name>
    <direction>Output</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
 </module>
 <module
   name="emif_lpddr4b"
   kind="emif_io96b_lpddr4"
   version="4.0.0"
   entity="EMIF_Qsys_emif_ddr4a_0"
   library="EMIF_Qsys_emif_ddr4a_0"
   path="emif_lpddr4b"
   hpath="emif_lpddr4b"
   className="altera_generic_component">
  <!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
  <parameter name="componentDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
   <value><![CDATA[<componentDefinition>
    <boundary>
        <interfaces>
            <interface>
                <name>s0_axi4_clock_in</name>
                <type>clock</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>s0_axi4_clock_in</name>
                        <role>clk</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>clockRate</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>core_init_n</name>
                <type>reset</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>core_init_n</name>
                        <role>reset_n</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>synchronousEdges</key>
                            <value>NONE</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>s0_axi4_ctrl_ready</name>
                <type>reset</type>
                <isStart>true</isStart>
                <ports>
                    <port>
                        <name>s0_axi4_reset_n</name>
                        <role>reset_n</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>associatedDirectReset</key>
                        </entry>
                        <entry>
                            <key>associatedResetSinks</key>
                            <value>none</value>
                        </entry>
                        <entry>
                            <key>synchronousEdges</key>
                            <value>NONE</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>s0_axi4</name>
                <type>axi4</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>s0_axi4_awaddr</name>
                        <role>awaddr</role>
                        <direction>Input</direction>
                        <width>30</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awburst</name>
                        <role>awburst</role>
                        <direction>Input</direction>
                        <width>2</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awid</name>
                        <role>awid</role>
                        <direction>Input</direction>
                        <width>7</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awlen</name>
                        <role>awlen</role>
                        <direction>Input</direction>
                        <width>8</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awlock</name>
                        <role>awlock</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awqos</name>
                        <role>awqos</role>
                        <direction>Input</direction>
                        <width>4</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awsize</name>
                        <role>awsize</role>
                        <direction>Input</direction>
                        <width>3</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awvalid</name>
                        <role>awvalid</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awuser</name>
                        <role>awuser</role>
                        <direction>Input</direction>
                        <width>14</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awprot</name>
                        <role>awprot</role>
                        <direction>Input</direction>
                        <width>3</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_awready</name>
                        <role>awready</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_araddr</name>
                        <role>araddr</role>
                        <direction>Input</direction>
                        <width>30</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arburst</name>
                        <role>arburst</role>
                        <direction>Input</direction>
                        <width>2</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arid</name>
                        <role>arid</role>
                        <direction>Input</direction>
                        <width>7</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arlen</name>
                        <role>arlen</role>
                        <direction>Input</direction>
                        <width>8</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arlock</name>
                        <role>arlock</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arqos</name>
                        <role>arqos</role>
                        <direction>Input</direction>
                        <width>4</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arsize</name>
                        <role>arsize</role>
                        <direction>Input</direction>
                        <width>3</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arvalid</name>
                        <role>arvalid</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_aruser</name>
                        <role>aruser</role>
                        <direction>Input</direction>
                        <width>14</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arprot</name>
                        <role>arprot</role>
                        <direction>Input</direction>
                        <width>3</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_arready</name>
                        <role>arready</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_wdata</name>
                        <role>wdata</role>
                        <direction>Input</direction>
                        <width>256</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_wstrb</name>
                        <role>wstrb</role>
                        <direction>Input</direction>
                        <width>32</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_wlast</name>
                        <role>wlast</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_wvalid</name>
                        <role>wvalid</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_wready</name>
                        <role>wready</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_bready</name>
                        <role>bready</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_bid</name>
                        <role>bid</role>
                        <direction>Output</direction>
                        <width>7</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_bresp</name>
                        <role>bresp</role>
                        <direction>Output</direction>
                        <width>2</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_bvalid</name>
                        <role>bvalid</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_rready</name>
                        <role>rready</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_rdata</name>
                        <role>rdata</role>
                        <direction>Output</direction>
                        <width>256</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_rid</name>
                        <role>rid</role>
                        <direction>Output</direction>
                        <width>7</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_rlast</name>
                        <role>rlast</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_rresp</name>
                        <role>rresp</role>
                        <direction>Output</direction>
                        <width>2</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4_rvalid</name>
                        <role>rvalid</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>mem_capacity_gbits</key>
                            <value>8.0</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                            <value>s0_axi4_clock_in</value>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                            <value>s0_axi4_ctrl_ready</value>
                        </entry>
                        <entry>
                            <key>optionalAssociatedReset</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>trustzoneAware</key>
                            <value>true</value>
                        </entry>
                        <entry>
                            <key>wakeupSignals</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>uniqueIdSupport</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>poison</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>traceSignals</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>isTranslator</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>maximumOutstandingReads</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>maximumOutstandingWrites</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>maximumOutstandingTransactions</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>dataCheck</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>addressCheck</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>securityAttribute</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>userData</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>readAcceptanceCapability</key>
                            <value>64</value>
                        </entry>
                        <entry>
                            <key>writeAcceptanceCapability</key>
                            <value>64</value>
                        </entry>
                        <entry>
                            <key>combinedAcceptanceCapability</key>
                            <value>64</value>
                        </entry>
                        <entry>
                            <key>readDataReorderingDepth</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>bridgesToMaster</key>
                        </entry>
                        <entry>
                            <key>dfhFeatureGuid</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhGroupId</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhParameterId</key>
                        </entry>
                        <entry>
                            <key>dfhParameterName</key>
                        </entry>
                        <entry>
                            <key>dfhParameterVersion</key>
                        </entry>
                        <entry>
                            <key>dfhParameterData</key>
                        </entry>
                        <entry>
                            <key>dfhParameterDataLength</key>
                        </entry>
                        <entry>
                            <key>dfhFeatureMajorVersion</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhFeatureMinorVersion</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhFeatureId</key>
                            <value>35</value>
                        </entry>
                        <entry>
                            <key>dfhFeatureType</key>
                            <value>3</value>
                        </entry>
                        <entry>
                            <key>noNarrowTransfer</key>
                            <value>false</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>s0_axi4lite_clock</name>
                <type>clock</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>s0_axi4lite_clock</name>
                        <role>clk</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>clockRate</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>s0_axi4lite_reset_n</name>
                <type>reset</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>s0_axi4lite_reset_n</name>
                        <role>reset_n</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                            <value>s0_axi4lite_clock</value>
                        </entry>
                        <entry>
                            <key>synchronousEdges</key>
                            <value>DEASSERT</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>s0_axi4lite</name>
                <type>axi4lite</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>s0_axi4lite_awaddr</name>
                        <role>awaddr</role>
                        <direction>Input</direction>
                        <width>27</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_awprot</name>
                        <role>awprot</role>
                        <direction>Input</direction>
                        <width>3</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_awvalid</name>
                        <role>awvalid</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_awready</name>
                        <role>awready</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_araddr</name>
                        <role>araddr</role>
                        <direction>Input</direction>
                        <width>27</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_arprot</name>
                        <role>arprot</role>
                        <direction>Input</direction>
                        <width>3</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_arvalid</name>
                        <role>arvalid</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_arready</name>
                        <role>arready</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_wdata</name>
                        <role>wdata</role>
                        <direction>Input</direction>
                        <width>32</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_wstrb</name>
                        <role>wstrb</role>
                        <direction>Input</direction>
                        <width>4</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_wvalid</name>
                        <role>wvalid</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_wready</name>
                        <role>wready</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_bready</name>
                        <role>bready</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_bresp</name>
                        <role>bresp</role>
                        <direction>Output</direction>
                        <width>2</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_bvalid</name>
                        <role>bvalid</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_rready</name>
                        <role>rready</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_rdata</name>
                        <role>rdata</role>
                        <direction>Output</direction>
                        <width>32</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_rresp</name>
                        <role>rresp</role>
                        <direction>Output</direction>
                        <width>2</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>s0_axi4lite_rvalid</name>
                        <role>rvalid</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                            <value>s0_axi4lite_clock</value>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                            <value>s0_axi4lite_reset_n</value>
                        </entry>
                        <entry>
                            <key>optionalAssociatedReset</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>trustzoneAware</key>
                            <value>true</value>
                        </entry>
                        <entry>
                            <key>wakeupSignals</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>uniqueIdSupport</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>poison</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>traceSignals</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>isTranslator</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>maximumOutstandingReads</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>maximumOutstandingWrites</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>maximumOutstandingTransactions</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>dataCheck</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>addressCheck</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>securityAttribute</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>userData</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>readAcceptanceCapability</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>writeAcceptanceCapability</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>combinedAcceptanceCapability</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>readDataReorderingDepth</key>
                            <value>1</value>
                        </entry>
                        <entry>
                            <key>bridgesToMaster</key>
                        </entry>
                        <entry>
                            <key>dfhFeatureGuid</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhGroupId</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhParameterId</key>
                        </entry>
                        <entry>
                            <key>dfhParameterName</key>
                        </entry>
                        <entry>
                            <key>dfhParameterVersion</key>
                        </entry>
                        <entry>
                            <key>dfhParameterData</key>
                        </entry>
                        <entry>
                            <key>dfhParameterDataLength</key>
                        </entry>
                        <entry>
                            <key>dfhFeatureMajorVersion</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhFeatureMinorVersion</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>dfhFeatureId</key>
                            <value>35</value>
                        </entry>
                        <entry>
                            <key>dfhFeatureType</key>
                            <value>3</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>mem_0</name>
                <type>conduit</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>mem_0_cs</name>
                        <role>mem_cs</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>mem_0_ca</name>
                        <role>mem_ca</role>
                        <direction>Output</direction>
                        <width>6</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>mem_0_cke</name>
                        <role>mem_cke</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>mem_0_dq</name>
                        <role>mem_dq</role>
                        <direction>Bidir</direction>
                        <width>32</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>mem_0_dqs_t</name>
                        <role>mem_dqs_t</role>
                        <direction>Bidir</direction>
                        <width>4</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>mem_0_dqs_c</name>
                        <role>mem_dqs_c</role>
                        <direction>Bidir</direction>
                        <width>4</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>mem_0_dmi</name>
                        <role>mem_dmi</role>
                        <direction>Bidir</direction>
                        <width>4</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                        </entry>
                        <entry>
                            <key>prSafe</key>
                            <value>false</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>mem_ck_0</name>
                <type>conduit</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>mem_0_ck_t</name>
                        <role>mem_ck_t</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                    <port>
                        <name>mem_0_ck_c</name>
                        <role>mem_ck_c</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                        </entry>
                        <entry>
                            <key>prSafe</key>
                            <value>false</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>mem_reset_n</name>
                <type>conduit</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>mem_0_reset_n</name>
                        <role>mem_reset_n</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                        </entry>
                        <entry>
                            <key>prSafe</key>
                            <value>false</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>oct_0</name>
                <type>conduit</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>oct_rzqin_0</name>
                        <role>oct_rzqin</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                        </entry>
                        <entry>
                            <key>prSafe</key>
                            <value>false</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>ref_clk</name>
                <type>clock</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>ref_clk</name>
                        <role>clk</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>clockRate</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
        </interfaces>
    </boundary>
    <originalModuleInfo>
        <className>emif_io96b_lpddr4</className>
        <version>4.0.0</version>
        <displayName>LPDDR4 External Memory Interfaces (EMIF) IP</displayName>
    </originalModuleInfo>
    <systemInfoParameterDescriptors>
        <descriptors>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_BOARD</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>BOARD</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_BOARD_TRAIT</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>BOARD_TRAIT</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_BASE_DIE</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>BASE_DEVICE</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_DIE_REVISIONS</parameterName>
                <parameterType>[Ljava.lang.String;</parameterType>
                <systemInfotype>DEVICE_DIE_REVISIONS</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_FAMILY</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE_FAMILY</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_GROUP</parameterName>
                <parameterType>[Ljava.lang.String;</parameterType>
                <systemInfoArgs>DEVICE_GROUP</systemInfoArgs>
                <systemInfotype>DEVICE_INFO</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_IOBANK_REVISION</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_POWER_MODEL</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>DEVICE_POWER_MODEL</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_SPEEDGRADE</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_DEVICE_TEMPERATURE_GRADE</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>DEVICE_TEMPERATURE_GRADE</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>SYSINFO_SUPPORTS_VID</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>SUPPORTS_VID</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
        </descriptors>
    </systemInfoParameterDescriptors>
    <systemInfos>
        <connPtSystemInfos>
            <entry>
                <key>s0_axi4</key>
                <value>
                    <connectionPointName>s0_axi4</connectionPointName>
                    <suppliedSystemInfos>
                        <entry>
                            <key>ADDRESS_MAP</key>
                            <value>&lt;address-map&gt;&lt;slave name='s0_axi4' start='0x0' end='0x40000000' datawidth='256' /&gt;&lt;/address-map&gt;</value>
                        </entry>
                        <entry>
                            <key>ADDRESS_WIDTH</key>
                            <value>30</value>
                        </entry>
                        <entry>
                            <key>MAX_SLAVE_DATA_WIDTH</key>
                            <value>256</value>
                        </entry>
                    </suppliedSystemInfos>
                    <consumedSystemInfos/>
                </value>
            </entry>
        </connPtSystemInfos>
    </systemInfos>
</componentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generationInfoDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
   <value><![CDATA[<generationInfoDefinition>
    <hdlLibraryName>EMIF_Qsys_emif_ddr4a_0</hdlLibraryName>
    <fileSets>
        <fileSet>
            <fileSetName>EMIF_Qsys_emif_ddr4a_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_emif_ddr4a_0</fileSetFixedName>
            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_emif_ddr4a_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_emif_ddr4a_0</fileSetFixedName>
            <fileSetKind>SIM_VERILOG</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_emif_ddr4a_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_emif_ddr4a_0</fileSetFixedName>
            <fileSetKind>SIM_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_emif_ddr4a_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_emif_ddr4a_0</fileSetFixedName>
            <fileSetKind>CDC</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_emif_ddr4a_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_emif_ddr4a_0</fileSetFixedName>
            <fileSetKind>CDC_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
    </fileSets>
</generationInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hlsFile">
   <type>java.lang.String</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="logicalView">
   <type>java.lang.String</type>
   <value>ip/EMIF_Qsys/EMIF_Qsys_emif_ddr4a_0.ip</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="defaultBoundary">
   <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
   <value><![CDATA[<boundaryDefinition>
    <interfaces>
        <interface>
            <name>s0_axi4_clock_in</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>s0_axi4_clock_in</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>core_init_n</name>
            <type>reset</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>core_init_n</name>
                    <role>reset_n</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>NONE</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>s0_axi4_ctrl_ready</name>
            <type>reset</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>s0_axi4_reset_n</name>
                    <role>reset_n</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedDirectReset</key>
                    </entry>
                    <entry>
                        <key>associatedResetSinks</key>
                        <value>none</value>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>NONE</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>s0_axi4</name>
            <type>axi4</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>s0_axi4_awaddr</name>
                    <role>awaddr</role>
                    <direction>Input</direction>
                    <width>30</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awburst</name>
                    <role>awburst</role>
                    <direction>Input</direction>
                    <width>2</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awid</name>
                    <role>awid</role>
                    <direction>Input</direction>
                    <width>7</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awlen</name>
                    <role>awlen</role>
                    <direction>Input</direction>
                    <width>8</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awlock</name>
                    <role>awlock</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awqos</name>
                    <role>awqos</role>
                    <direction>Input</direction>
                    <width>4</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awsize</name>
                    <role>awsize</role>
                    <direction>Input</direction>
                    <width>3</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awvalid</name>
                    <role>awvalid</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awuser</name>
                    <role>awuser</role>
                    <direction>Input</direction>
                    <width>14</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awprot</name>
                    <role>awprot</role>
                    <direction>Input</direction>
                    <width>3</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_awready</name>
                    <role>awready</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_araddr</name>
                    <role>araddr</role>
                    <direction>Input</direction>
                    <width>30</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arburst</name>
                    <role>arburst</role>
                    <direction>Input</direction>
                    <width>2</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arid</name>
                    <role>arid</role>
                    <direction>Input</direction>
                    <width>7</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arlen</name>
                    <role>arlen</role>
                    <direction>Input</direction>
                    <width>8</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arlock</name>
                    <role>arlock</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arqos</name>
                    <role>arqos</role>
                    <direction>Input</direction>
                    <width>4</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arsize</name>
                    <role>arsize</role>
                    <direction>Input</direction>
                    <width>3</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arvalid</name>
                    <role>arvalid</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_aruser</name>
                    <role>aruser</role>
                    <direction>Input</direction>
                    <width>14</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arprot</name>
                    <role>arprot</role>
                    <direction>Input</direction>
                    <width>3</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_arready</name>
                    <role>arready</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_wdata</name>
                    <role>wdata</role>
                    <direction>Input</direction>
                    <width>256</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_wstrb</name>
                    <role>wstrb</role>
                    <direction>Input</direction>
                    <width>32</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_wlast</name>
                    <role>wlast</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_wvalid</name>
                    <role>wvalid</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_wready</name>
                    <role>wready</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_bready</name>
                    <role>bready</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_bid</name>
                    <role>bid</role>
                    <direction>Output</direction>
                    <width>7</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_bresp</name>
                    <role>bresp</role>
                    <direction>Output</direction>
                    <width>2</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_bvalid</name>
                    <role>bvalid</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_rready</name>
                    <role>rready</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_rdata</name>
                    <role>rdata</role>
                    <direction>Output</direction>
                    <width>256</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_rid</name>
                    <role>rid</role>
                    <direction>Output</direction>
                    <width>7</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_rlast</name>
                    <role>rlast</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_rresp</name>
                    <role>rresp</role>
                    <direction>Output</direction>
                    <width>2</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4_rvalid</name>
                    <role>rvalid</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>mem_capacity_gbits</key>
                        <value>8.0</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                        <value>s0_axi4_clock_in</value>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                        <value>s0_axi4_ctrl_ready</value>
                    </entry>
                    <entry>
                        <key>trustzoneAware</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>wakeupSignals</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>uniqueIdSupport</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>poison</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>traceSignals</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>isTranslator</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>maximumOutstandingReads</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>maximumOutstandingWrites</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>maximumOutstandingTransactions</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>dataCheck</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>addressCheck</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>securityAttribute</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>userData</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>readAcceptanceCapability</key>
                        <value>64</value>
                    </entry>
                    <entry>
                        <key>writeAcceptanceCapability</key>
                        <value>64</value>
                    </entry>
                    <entry>
                        <key>combinedAcceptanceCapability</key>
                        <value>64</value>
                    </entry>
                    <entry>
                        <key>readDataReorderingDepth</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>bridgesToMaster</key>
                    </entry>
                    <entry>
                        <key>dfhFeatureGuid</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhGroupId</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhParameterId</key>
                    </entry>
                    <entry>
                        <key>dfhParameterName</key>
                    </entry>
                    <entry>
                        <key>dfhParameterVersion</key>
                    </entry>
                    <entry>
                        <key>dfhParameterData</key>
                    </entry>
                    <entry>
                        <key>dfhParameterDataLength</key>
                    </entry>
                    <entry>
                        <key>dfhFeatureMajorVersion</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhFeatureMinorVersion</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhFeatureId</key>
                        <value>35</value>
                    </entry>
                    <entry>
                        <key>dfhFeatureType</key>
                        <value>3</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>s0_axi4lite_clock</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>s0_axi4lite_clock</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>s0_axi4lite_reset_n</name>
            <type>reset</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>s0_axi4lite_reset_n</name>
                    <role>reset_n</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                        <value>s0_axi4lite_clock</value>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>DEASSERT</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>s0_axi4lite</name>
            <type>axi4lite</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>s0_axi4lite_awaddr</name>
                    <role>awaddr</role>
                    <direction>Input</direction>
                    <width>27</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_awprot</name>
                    <role>awprot</role>
                    <direction>Input</direction>
                    <width>3</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_awvalid</name>
                    <role>awvalid</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_awready</name>
                    <role>awready</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_araddr</name>
                    <role>araddr</role>
                    <direction>Input</direction>
                    <width>27</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_arprot</name>
                    <role>arprot</role>
                    <direction>Input</direction>
                    <width>3</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_arvalid</name>
                    <role>arvalid</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_arready</name>
                    <role>arready</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_wdata</name>
                    <role>wdata</role>
                    <direction>Input</direction>
                    <width>32</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_wstrb</name>
                    <role>wstrb</role>
                    <direction>Input</direction>
                    <width>4</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_wvalid</name>
                    <role>wvalid</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_wready</name>
                    <role>wready</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_bready</name>
                    <role>bready</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_bresp</name>
                    <role>bresp</role>
                    <direction>Output</direction>
                    <width>2</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_bvalid</name>
                    <role>bvalid</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_rready</name>
                    <role>rready</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_rdata</name>
                    <role>rdata</role>
                    <direction>Output</direction>
                    <width>32</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_rresp</name>
                    <role>rresp</role>
                    <direction>Output</direction>
                    <width>2</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>s0_axi4lite_rvalid</name>
                    <role>rvalid</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                        <value>s0_axi4lite_clock</value>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                        <value>s0_axi4lite_reset_n</value>
                    </entry>
                    <entry>
                        <key>trustzoneAware</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>wakeupSignals</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>uniqueIdSupport</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>poison</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>traceSignals</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>isTranslator</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>maximumOutstandingReads</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>maximumOutstandingWrites</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>maximumOutstandingTransactions</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>dataCheck</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>addressCheck</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>securityAttribute</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>userData</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>readAcceptanceCapability</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>writeAcceptanceCapability</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>combinedAcceptanceCapability</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>readDataReorderingDepth</key>
                        <value>1</value>
                    </entry>
                    <entry>
                        <key>bridgesToMaster</key>
                    </entry>
                    <entry>
                        <key>dfhFeatureGuid</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhGroupId</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhParameterId</key>
                    </entry>
                    <entry>
                        <key>dfhParameterName</key>
                    </entry>
                    <entry>
                        <key>dfhParameterVersion</key>
                    </entry>
                    <entry>
                        <key>dfhParameterData</key>
                    </entry>
                    <entry>
                        <key>dfhParameterDataLength</key>
                    </entry>
                    <entry>
                        <key>dfhFeatureMajorVersion</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhFeatureMinorVersion</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>dfhFeatureId</key>
                        <value>35</value>
                    </entry>
                    <entry>
                        <key>dfhFeatureType</key>
                        <value>3</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>mem_0</name>
            <type>conduit</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>mem_0_cs</name>
                    <role>mem_cs</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>mem_0_ca</name>
                    <role>mem_ca</role>
                    <direction>Output</direction>
                    <width>6</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>mem_0_cke</name>
                    <role>mem_cke</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>mem_0_dq</name>
                    <role>mem_dq</role>
                    <direction>Bidir</direction>
                    <width>32</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>mem_0_dqs_t</name>
                    <role>mem_dqs_t</role>
                    <direction>Bidir</direction>
                    <width>4</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>mem_0_dqs_c</name>
                    <role>mem_dqs_c</role>
                    <direction>Bidir</direction>
                    <width>4</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>mem_0_dmi</name>
                    <role>mem_dmi</role>
                    <direction>Bidir</direction>
                    <width>4</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                    </entry>
                    <entry>
                        <key>prSafe</key>
                        <value>false</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>mem_ck_0</name>
            <type>conduit</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>mem_0_ck_t</name>
                    <role>mem_ck_t</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
                <port>
                    <name>mem_0_ck_c</name>
                    <role>mem_ck_c</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                    </entry>
                    <entry>
                        <key>prSafe</key>
                        <value>false</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>mem_reset_n</name>
            <type>conduit</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>mem_0_reset_n</name>
                    <role>mem_reset_n</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                    </entry>
                    <entry>
                        <key>prSafe</key>
                        <value>false</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>oct_0</name>
            <type>conduit</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>oct_rzqin_0</name>
                    <role>oct_rzqin</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                    </entry>
                    <entry>
                        <key>prSafe</key>
                        <value>false</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>ref_clk</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>ref_clk</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
    </interfaces>
</boundaryDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="moduleAssignmentDefinition">
   <type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
   <value><![CDATA[<assignmentDefinition>
    <assignmentValueMap/>
</assignmentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="svInterfaceDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hdlParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
   <value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="transformParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
   <value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuInfo">
   <type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="bspCpu">
   <type>java.lang.Boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="liveModuleName">
   <type>java.lang.String</type>
   <value>EMIF_Qsys_emif_ddr4a_0</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuHashInfo">
   <type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
   <value><![CDATA[<cpuHashInfoDefinition>
    <cpuHashInfoMap/>
</cpuHashInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="SYSINFO_BOARD">
   <type>java.lang.String</type>
   <value>default</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>BOARD</sysinfo_type>
  </parameter>
  <parameter name="SYSINFO_BOARD_TRAIT">
   <type>java.lang.String</type>
   <value></value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>BOARD_TRAIT</sysinfo_type>
  </parameter>
  <parameter name="SYSINFO_DEVICE">
   <type>java.lang.String</type>
   <value>A5EB013BB23BE4SCS</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE</sysinfo_type>
  </parameter>
  <parameter name="SYSINFO_DEVICE_BASE_DIE">
   <type>java.lang.String</type>
   <value>SM4REVB</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>PART_TRAIT</sysinfo_type>
   <sysinfo_arg>BASE_DEVICE</sysinfo_arg>
  </parameter>
  <parameter name="SYSINFO_DEVICE_DIE_REVISIONS">
   <type>[Ljava.lang.String;</type>
   <value>MAIN_SM4_REVB</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_DIE_REVISIONS</sysinfo_type>
  </parameter>
  <parameter name="SYSINFO_DEVICE_FAMILY">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="SYSINFO_DEVICE_GROUP">
   <type>[Ljava.lang.String;</type>
   <value>B</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_INFO</sysinfo_type>
   <sysinfo_arg>DEVICE_GROUP</sysinfo_arg>
  </parameter>
  <parameter name="SYSINFO_DEVICE_IOBANK_REVISION">
   <type>java.lang.String</type>
   <value>IO96B_REVB1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>PART_TRAIT</sysinfo_type>
   <sysinfo_arg>DEVICE_IOBANK_REVISION</sysinfo_arg>
  </parameter>
  <parameter name="SYSINFO_DEVICE_POWER_MODEL">
   <type>java.lang.String</type>
   <value>STANDARD_POWER_FIXED</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>PART_TRAIT</sysinfo_type>
   <sysinfo_arg>DEVICE_POWER_MODEL</sysinfo_arg>
  </parameter>
  <parameter name="SYSINFO_DEVICE_SPEEDGRADE">
   <type>java.lang.String</type>
   <value>4</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
  </parameter>
  <parameter name="SYSINFO_DEVICE_TEMPERATURE_GRADE">
   <type>java.lang.String</type>
   <value>EXTENDED</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>PART_TRAIT</sysinfo_type>
   <sysinfo_arg>DEVICE_TEMPERATURE_GRADE</sysinfo_arg>
  </parameter>
  <parameter name="SYSINFO_SUPPORTS_VID">
   <type>java.lang.String</type>
   <value>0</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>PART_TRAIT</sysinfo_type>
   <sysinfo_arg>SUPPORTS_VID</sysinfo_arg>
  </parameter>
  <parameter name="AUTO_DEVICE_FAMILY">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="AUTO_DEVICE">
   <type>java.lang.String</type>
   <value>A5EB013BB23BE4SCS</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <interface name="s0_axi4_clock_in" kind="clock_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>s0_axi4_clock_in</name>
    <direction>Input</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
  <interface name="core_init_n" kind="reset_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="synchronousEdges">
    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
    <value>NONE</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>reset</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>core_init_n</name>
    <direction>Input</direction>
    <width>1</width>
    <role>reset_n</role>
   </port>
  </interface>
  <interface name="s0_axi4_ctrl_ready" kind="reset_source" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedDirectReset">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedResetSinks">
    <type>[Ljava.lang.String;</type>
    <value>none</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="synchronousEdges">
    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
    <value>NONE</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>reset</type>
   <span>0</span>
   <isStart>true</isStart>
   <port>
    <name>s0_axi4_reset_n</name>
    <direction>Output</direction>
    <width>1</width>
    <role>reset_n</role>
   </port>
  </interface>
  <interface name="s0_axi4" kind="altera_axi4_slave" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <assignment>
    <name>mem_capacity_gbits</name>
    <value>8.0</value>
   </assignment>
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value>s0_axi4_clock_in</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedReset">
    <type>java.lang.String</type>
    <value>s0_axi4_ctrl_ready</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="optionalAssociatedReset">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="trustzoneAware">
    <type>boolean</type>
    <value>true</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="wakeupSignals">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="uniqueIdSupport">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="poison">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="traceSignals">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="isTranslator">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="maximumOutstandingReads">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="maximumOutstandingWrites">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="maximumOutstandingTransactions">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dataCheck">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="addressCheck">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="securityAttribute">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="userData">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="readAcceptanceCapability">
    <type>java.lang.Integer</type>
    <value>64</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="writeAcceptanceCapability">
    <type>java.lang.Integer</type>
    <value>64</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="combinedAcceptanceCapability">
    <type>java.lang.Integer</type>
    <value>64</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="readDataReorderingDepth">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="bridgesToMaster">
    <type>com.altera.entityinterfaces.IConnectionPoint</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureGuid">
    <type>java.math.BigInteger</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhGroupId">
    <type>java.lang.Integer</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterId">
    <type>[Ljava.lang.Integer;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterName">
    <type>[Ljava.lang.String;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterVersion">
    <type>[Ljava.lang.Integer;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterData">
    <type>[Ljava.lang.String;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterDataLength">
    <type>[Ljava.lang.Integer;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureMajorVersion">
    <type>java.lang.Integer</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureMinorVersion">
    <type>java.lang.Integer</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureId">
    <type>java.lang.Integer</type>
    <value>35</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureType">
    <type>java.lang.Integer</type>
    <value>3</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="noNarrowTransfer">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="addressSpan">
    <type>java.math.BigInteger</type>
    <value>1073741824</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <type>axi4</type>
   <span>1073741824</span>
   <isStart>false</isStart>
   <port>
    <name>s0_axi4_awaddr</name>
    <direction>Input</direction>
    <width>30</width>
    <role>awaddr</role>
   </port>
   <port>
    <name>s0_axi4_awburst</name>
    <direction>Input</direction>
    <width>2</width>
    <role>awburst</role>
   </port>
   <port>
    <name>s0_axi4_awid</name>
    <direction>Input</direction>
    <width>7</width>
    <role>awid</role>
   </port>
   <port>
    <name>s0_axi4_awlen</name>
    <direction>Input</direction>
    <width>8</width>
    <role>awlen</role>
   </port>
   <port>
    <name>s0_axi4_awlock</name>
    <direction>Input</direction>
    <width>1</width>
    <role>awlock</role>
   </port>
   <port>
    <name>s0_axi4_awqos</name>
    <direction>Input</direction>
    <width>4</width>
    <role>awqos</role>
   </port>
   <port>
    <name>s0_axi4_awsize</name>
    <direction>Input</direction>
    <width>3</width>
    <role>awsize</role>
   </port>
   <port>
    <name>s0_axi4_awvalid</name>
    <direction>Input</direction>
    <width>1</width>
    <role>awvalid</role>
   </port>
   <port>
    <name>s0_axi4_awuser</name>
    <direction>Input</direction>
    <width>14</width>
    <role>awuser</role>
   </port>
   <port>
    <name>s0_axi4_awprot</name>
    <direction>Input</direction>
    <width>3</width>
    <role>awprot</role>
   </port>
   <port>
    <name>s0_axi4_awready</name>
    <direction>Output</direction>
    <width>1</width>
    <role>awready</role>
   </port>
   <port>
    <name>s0_axi4_araddr</name>
    <direction>Input</direction>
    <width>30</width>
    <role>araddr</role>
   </port>
   <port>
    <name>s0_axi4_arburst</name>
    <direction>Input</direction>
    <width>2</width>
    <role>arburst</role>
   </port>
   <port>
    <name>s0_axi4_arid</name>
    <direction>Input</direction>
    <width>7</width>
    <role>arid</role>
   </port>
   <port>
    <name>s0_axi4_arlen</name>
    <direction>Input</direction>
    <width>8</width>
    <role>arlen</role>
   </port>
   <port>
    <name>s0_axi4_arlock</name>
    <direction>Input</direction>
    <width>1</width>
    <role>arlock</role>
   </port>
   <port>
    <name>s0_axi4_arqos</name>
    <direction>Input</direction>
    <width>4</width>
    <role>arqos</role>
   </port>
   <port>
    <name>s0_axi4_arsize</name>
    <direction>Input</direction>
    <width>3</width>
    <role>arsize</role>
   </port>
   <port>
    <name>s0_axi4_arvalid</name>
    <direction>Input</direction>
    <width>1</width>
    <role>arvalid</role>
   </port>
   <port>
    <name>s0_axi4_aruser</name>
    <direction>Input</direction>
    <width>14</width>
    <role>aruser</role>
   </port>
   <port>
    <name>s0_axi4_arprot</name>
    <direction>Input</direction>
    <width>3</width>
    <role>arprot</role>
   </port>
   <port>
    <name>s0_axi4_arready</name>
    <direction>Output</direction>
    <width>1</width>
    <role>arready</role>
   </port>
   <port>
    <name>s0_axi4_wdata</name>
    <direction>Input</direction>
    <width>256</width>
    <role>wdata</role>
   </port>
   <port>
    <name>s0_axi4_wstrb</name>
    <direction>Input</direction>
    <width>32</width>
    <role>wstrb</role>
   </port>
   <port>
    <name>s0_axi4_wlast</name>
    <direction>Input</direction>
    <width>1</width>
    <role>wlast</role>
   </port>
   <port>
    <name>s0_axi4_wvalid</name>
    <direction>Input</direction>
    <width>1</width>
    <role>wvalid</role>
   </port>
   <port>
    <name>s0_axi4_wready</name>
    <direction>Output</direction>
    <width>1</width>
    <role>wready</role>
   </port>
   <port>
    <name>s0_axi4_bready</name>
    <direction>Input</direction>
    <width>1</width>
    <role>bready</role>
   </port>
   <port>
    <name>s0_axi4_bid</name>
    <direction>Output</direction>
    <width>7</width>
    <role>bid</role>
   </port>
   <port>
    <name>s0_axi4_bresp</name>
    <direction>Output</direction>
    <width>2</width>
    <role>bresp</role>
   </port>
   <port>
    <name>s0_axi4_bvalid</name>
    <direction>Output</direction>
    <width>1</width>
    <role>bvalid</role>
   </port>
   <port>
    <name>s0_axi4_rready</name>
    <direction>Input</direction>
    <width>1</width>
    <role>rready</role>
   </port>
   <port>
    <name>s0_axi4_rdata</name>
    <direction>Output</direction>
    <width>256</width>
    <role>rdata</role>
   </port>
   <port>
    <name>s0_axi4_rid</name>
    <direction>Output</direction>
    <width>7</width>
    <role>rid</role>
   </port>
   <port>
    <name>s0_axi4_rlast</name>
    <direction>Output</direction>
    <width>1</width>
    <role>rlast</role>
   </port>
   <port>
    <name>s0_axi4_rresp</name>
    <direction>Output</direction>
    <width>2</width>
    <role>rresp</role>
   </port>
   <port>
    <name>s0_axi4_rvalid</name>
    <direction>Output</direction>
    <width>1</width>
    <role>rvalid</role>
   </port>
  </interface>
  <interface name="s0_axi4lite_clock" kind="clock_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>s0_axi4lite_clock</name>
    <direction>Input</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
  <interface name="s0_axi4lite_reset_n" kind="reset_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value>s0_axi4lite_clock</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="synchronousEdges">
    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
    <value>DEASSERT</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>reset</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>s0_axi4lite_reset_n</name>
    <direction>Input</direction>
    <width>1</width>
    <role>reset_n</role>
   </port>
  </interface>
  <interface name="s0_axi4lite" kind="altera_axi4lite_slave" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value>s0_axi4lite_clock</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedReset">
    <type>java.lang.String</type>
    <value>s0_axi4lite_reset_n</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="optionalAssociatedReset">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="trustzoneAware">
    <type>boolean</type>
    <value>true</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="wakeupSignals">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="uniqueIdSupport">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="poison">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="traceSignals">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="isTranslator">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="maximumOutstandingReads">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="maximumOutstandingWrites">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="maximumOutstandingTransactions">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dataCheck">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="addressCheck">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="securityAttribute">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="userData">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="readAcceptanceCapability">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="writeAcceptanceCapability">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="combinedAcceptanceCapability">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="readDataReorderingDepth">
    <type>java.lang.Integer</type>
    <value>1</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="bridgesToMaster">
    <type>com.altera.entityinterfaces.IConnectionPoint</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureGuid">
    <type>java.math.BigInteger</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhGroupId">
    <type>java.lang.Integer</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterId">
    <type>[Ljava.lang.Integer;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterName">
    <type>[Ljava.lang.String;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterVersion">
    <type>[Ljava.lang.Integer;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterData">
    <type>[Ljava.lang.String;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhParameterDataLength">
    <type>[Ljava.lang.Integer;</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureMajorVersion">
    <type>java.lang.Integer</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureMinorVersion">
    <type>java.lang.Integer</type>
    <value>0</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureId">
    <type>java.lang.Integer</type>
    <value>35</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="dfhFeatureType">
    <type>java.lang.Integer</type>
    <value>3</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="addressSpan">
    <type>java.math.BigInteger</type>
    <value>134217728</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <type>axi4lite</type>
   <span>134217728</span>
   <isStart>false</isStart>
   <port>
    <name>s0_axi4lite_awaddr</name>
    <direction>Input</direction>
    <width>27</width>
    <role>awaddr</role>
   </port>
   <port>
    <name>s0_axi4lite_awprot</name>
    <direction>Input</direction>
    <width>3</width>
    <role>awprot</role>
   </port>
   <port>
    <name>s0_axi4lite_awvalid</name>
    <direction>Input</direction>
    <width>1</width>
    <role>awvalid</role>
   </port>
   <port>
    <name>s0_axi4lite_awready</name>
    <direction>Output</direction>
    <width>1</width>
    <role>awready</role>
   </port>
   <port>
    <name>s0_axi4lite_araddr</name>
    <direction>Input</direction>
    <width>27</width>
    <role>araddr</role>
   </port>
   <port>
    <name>s0_axi4lite_arprot</name>
    <direction>Input</direction>
    <width>3</width>
    <role>arprot</role>
   </port>
   <port>
    <name>s0_axi4lite_arvalid</name>
    <direction>Input</direction>
    <width>1</width>
    <role>arvalid</role>
   </port>
   <port>
    <name>s0_axi4lite_arready</name>
    <direction>Output</direction>
    <width>1</width>
    <role>arready</role>
   </port>
   <port>
    <name>s0_axi4lite_wdata</name>
    <direction>Input</direction>
    <width>32</width>
    <role>wdata</role>
   </port>
   <port>
    <name>s0_axi4lite_wstrb</name>
    <direction>Input</direction>
    <width>4</width>
    <role>wstrb</role>
   </port>
   <port>
    <name>s0_axi4lite_wvalid</name>
    <direction>Input</direction>
    <width>1</width>
    <role>wvalid</role>
   </port>
   <port>
    <name>s0_axi4lite_wready</name>
    <direction>Output</direction>
    <width>1</width>
    <role>wready</role>
   </port>
   <port>
    <name>s0_axi4lite_bready</name>
    <direction>Input</direction>
    <width>1</width>
    <role>bready</role>
   </port>
   <port>
    <name>s0_axi4lite_bresp</name>
    <direction>Output</direction>
    <width>2</width>
    <role>bresp</role>
   </port>
   <port>
    <name>s0_axi4lite_bvalid</name>
    <direction>Output</direction>
    <width>1</width>
    <role>bvalid</role>
   </port>
   <port>
    <name>s0_axi4lite_rready</name>
    <direction>Input</direction>
    <width>1</width>
    <role>rready</role>
   </port>
   <port>
    <name>s0_axi4lite_rdata</name>
    <direction>Output</direction>
    <width>32</width>
    <role>rdata</role>
   </port>
   <port>
    <name>s0_axi4lite_rresp</name>
    <direction>Output</direction>
    <width>2</width>
    <role>rresp</role>
   </port>
   <port>
    <name>s0_axi4lite_rvalid</name>
    <direction>Output</direction>
    <width>1</width>
    <role>rvalid</role>
   </port>
  </interface>
  <interface name="mem_0" kind="conduit_end" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedReset">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="prSafe">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>conduit</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>mem_0_cs</name>
    <direction>Output</direction>
    <width>1</width>
    <role>mem_cs</role>
   </port>
   <port>
    <name>mem_0_ca</name>
    <direction>Output</direction>
    <width>6</width>
    <role>mem_ca</role>
   </port>
   <port>
    <name>mem_0_cke</name>
    <direction>Output</direction>
    <width>1</width>
    <role>mem_cke</role>
   </port>
   <port>
    <name>mem_0_dq</name>
    <direction>Bidir</direction>
    <width>32</width>
    <role>mem_dq</role>
   </port>
   <port>
    <name>mem_0_dqs_t</name>
    <direction>Bidir</direction>
    <width>4</width>
    <role>mem_dqs_t</role>
   </port>
   <port>
    <name>mem_0_dqs_c</name>
    <direction>Bidir</direction>
    <width>4</width>
    <role>mem_dqs_c</role>
   </port>
   <port>
    <name>mem_0_dmi</name>
    <direction>Bidir</direction>
    <width>4</width>
    <role>mem_dmi</role>
   </port>
  </interface>
  <interface name="mem_ck_0" kind="conduit_end" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedReset">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="prSafe">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>conduit</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>mem_0_ck_t</name>
    <direction>Output</direction>
    <width>1</width>
    <role>mem_ck_t</role>
   </port>
   <port>
    <name>mem_0_ck_c</name>
    <direction>Output</direction>
    <width>1</width>
    <role>mem_ck_c</role>
   </port>
  </interface>
  <interface name="mem_reset_n" kind="conduit_end" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedReset">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="prSafe">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>conduit</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>mem_0_reset_n</name>
    <direction>Output</direction>
    <width>1</width>
    <role>mem_reset_n</role>
   </port>
  </interface>
  <interface name="oct_0" kind="conduit_end" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedReset">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="prSafe">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>conduit</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>oct_rzqin_0</name>
    <direction>Input</direction>
    <width>1</width>
    <role>oct_rzqin</role>
   </port>
  </interface>
  <interface name="ref_clk" kind="clock_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>ref_clk</name>
    <direction>Input</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
 </module>
 <module
   name="iopll"
   kind="altera_iopll"
   version="20.0.0"
   entity="EMIF_Qsys_iopll_0"
   library="EMIF_Qsys_iopll_0"
   path="iopll"
   hpath="iopll"
   className="altera_generic_component">
  <!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
  <assignment>
   <name>embeddedsw.dts.compatible</name>
   <value>altr,pll</value>
  </assignment>
  <assignment>
   <name>embeddedsw.dts.group</name>
   <value>clock</value>
  </assignment>
  <assignment>
   <name>embeddedsw.dts.vendor</name>
   <value>altr</value>
  </assignment>
  <parameter name="componentDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
   <value><![CDATA[<componentDefinition>
    <boundary>
        <interfaces>
            <interface>
                <name>refclk</name>
                <type>clock</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>refclk</name>
                        <role>clk</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>input</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>clockRate</key>
                            <value>50000000</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>locked</name>
                <type>conduit</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>locked</name>
                        <role>export</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>output</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>associatedReset</key>
                        </entry>
                        <entry>
                            <key>prSafe</key>
                            <value>false</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>reset</name>
                <type>reset</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>rst</name>
                        <role>reset</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>input</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                        </entry>
                        <entry>
                            <key>synchronousEdges</key>
                            <value>NONE</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>outclk0</name>
                <type>clock</type>
                <isStart>true</isStart>
                <ports>
                    <port>
                        <name>outclk_0</name>
                        <role>clk</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>output</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedDirectClock</key>
                        </entry>
                        <entry>
                            <key>clockRate</key>
                            <value>310000000</value>
                        </entry>
                        <entry>
                            <key>clockRateKnown</key>
                            <value>true</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>outclk1</name>
                <type>clock</type>
                <isStart>true</isStart>
                <ports>
                    <port>
                        <name>outclk_1</name>
                        <role>clk</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap>
                        <entry>
                            <key>ui.blockdiagram.direction</key>
                            <value>output</value>
                        </entry>
                    </assignmentValueMap>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedDirectClock</key>
                        </entry>
                        <entry>
                            <key>clockRate</key>
                            <value>155000000</value>
                        </entry>
                        <entry>
                            <key>clockRateKnown</key>
                            <value>true</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
        </interfaces>
    </boundary>
    <originalModuleInfo>
        <className>altera_iopll</className>
        <version>20.0.0</version>
        <displayName>IOPLL FPGA IP</displayName>
    </originalModuleInfo>
    <systemInfoParameterDescriptors>
        <descriptors>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_info_device_component</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_info_device_family</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfotype>DEVICE_FAMILY</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_info_device_speed_grade</parameterName>
                <parameterType>[Ljava.lang.String;</parameterType>
                <systemInfoArgs>REAL_SPEED_GRADE</systemInfoArgs>
                <systemInfotype>DEVICE_INFO</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_part_trait_iobank_rev</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>DEVICE_IOBANK_REVISION</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
            <descriptor>
                <parameterDefaultValue></parameterDefaultValue>
                <parameterName>system_part_trait_speed_grade</parameterName>
                <parameterType>java.lang.String</parameterType>
                <systemInfoArgs>DEVICE_SPEEDGRADE</systemInfoArgs>
                <systemInfotype>PART_TRAIT</systemInfotype>
            </descriptor>
        </descriptors>
    </systemInfoParameterDescriptors>
    <systemInfos>
        <connPtSystemInfos>
            <entry>
                <key>outclk0</key>
                <value>
                    <connectionPointName>outclk0</connectionPointName>
                    <suppliedSystemInfos>
                        <entry>
                            <key>CLOCK_RATE</key>
                            <value>310000000</value>
                        </entry>
                    </suppliedSystemInfos>
                    <consumedSystemInfos/>
                </value>
            </entry>
            <entry>
                <key>outclk1</key>
                <value>
                    <connectionPointName>outclk1</connectionPointName>
                    <suppliedSystemInfos>
                        <entry>
                            <key>CLOCK_RATE</key>
                            <value>155000000</value>
                        </entry>
                    </suppliedSystemInfos>
                    <consumedSystemInfos/>
                </value>
            </entry>
        </connPtSystemInfos>
    </systemInfos>
</componentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generationInfoDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
   <value><![CDATA[<generationInfoDefinition>
    <hdlLibraryName>EMIF_Qsys_iopll_0</hdlLibraryName>
    <fileSets>
        <fileSet>
            <fileSetName>EMIF_Qsys_iopll_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_iopll_0</fileSetFixedName>
            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_iopll_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_iopll_0</fileSetFixedName>
            <fileSetKind>SIM_VERILOG</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_iopll_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_iopll_0</fileSetFixedName>
            <fileSetKind>SIM_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_iopll_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_iopll_0</fileSetFixedName>
            <fileSetKind>CDC</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_iopll_0</fileSetName>
            <fileSetFixedName>EMIF_Qsys_iopll_0</fileSetFixedName>
            <fileSetKind>CDC_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
    </fileSets>
</generationInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hlsFile">
   <type>java.lang.String</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="logicalView">
   <type>java.lang.String</type>
   <value>ip/EMIF_Qsys/EMIF_Qsys_iopll_0.ip</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="defaultBoundary">
   <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
   <value><![CDATA[<boundaryDefinition>
    <interfaces>
        <interface>
            <name>refclk</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>refclk</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>input</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>50000000</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>locked</name>
            <type>conduit</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>locked</name>
                    <role>export</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>output</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>associatedReset</key>
                    </entry>
                    <entry>
                        <key>prSafe</key>
                        <value>false</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>reset</name>
            <type>reset</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>rst</name>
                    <role>reset</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>input</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>NONE</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>outclk0</name>
            <type>clock</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>outclk_0</name>
                    <role>clk</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>output</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedDirectClock</key>
                    </entry>
                    <entry>
                        <key>clockRate</key>
                        <value>310000000</value>
                    </entry>
                    <entry>
                        <key>clockRateKnown</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>outclk1</name>
            <type>clock</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>outclk_1</name>
                    <role>clk</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap>
                    <entry>
                        <key>ui.blockdiagram.direction</key>
                        <value>output</value>
                    </entry>
                </assignmentValueMap>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedDirectClock</key>
                    </entry>
                    <entry>
                        <key>clockRate</key>
                        <value>155000000</value>
                    </entry>
                    <entry>
                        <key>clockRateKnown</key>
                        <value>true</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
    </interfaces>
</boundaryDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="moduleAssignmentDefinition">
   <type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
   <value><![CDATA[<assignmentDefinition>
    <assignmentValueMap>
        <entry>
            <key>embeddedsw.dts.compatible</key>
            <value>altr,pll</value>
        </entry>
        <entry>
            <key>embeddedsw.dts.group</key>
            <value>clock</value>
        </entry>
        <entry>
            <key>embeddedsw.dts.vendor</key>
            <value>altr</value>
        </entry>
    </assignmentValueMap>
</assignmentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="svInterfaceDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hdlParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
   <value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="transformParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
   <value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuInfo">
   <type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="bspCpu">
   <type>java.lang.Boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="liveModuleName">
   <type>java.lang.String</type>
   <value>iopll_0</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuHashInfo">
   <type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
   <value><![CDATA[<cpuHashInfoDefinition>
    <cpuHashInfoMap/>
</cpuHashInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="system_info_device_component">
   <type>java.lang.String</type>
   <value>A5EB013BB23BE4SCS</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE</sysinfo_type>
  </parameter>
  <parameter name="system_info_device_family">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="system_info_device_speed_grade">
   <type>[Ljava.lang.String;</type>
   <value>4</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_INFO</sysinfo_type>
   <sysinfo_arg>REAL_SPEED_GRADE</sysinfo_arg>
  </parameter>
  <parameter name="system_part_trait_iobank_rev">
   <type>java.lang.String</type>
   <value>IO96B_REVB1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>PART_TRAIT</sysinfo_type>
   <sysinfo_arg>DEVICE_IOBANK_REVISION</sysinfo_arg>
  </parameter>
  <parameter name="system_part_trait_speed_grade">
   <type>java.lang.String</type>
   <value>4</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>PART_TRAIT</sysinfo_type>
   <sysinfo_arg>DEVICE_SPEEDGRADE</sysinfo_arg>
  </parameter>
  <parameter name="AUTO_DEVICE_FAMILY">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="AUTO_DEVICE">
   <type>java.lang.String</type>
   <value>A5EB013BB23BE4SCS</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <interface name="refclk" kind="clock_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <assignment>
    <name>ui.blockdiagram.direction</name>
    <value>input</value>
   </assignment>
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRateKnown">
    <type>java.lang.Boolean</type>
    <value>true</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRate">
    <type>java.lang.Long</type>
    <value>50000000</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>refclk</name>
    <direction>Input</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
  <interface name="locked" kind="conduit_end" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <assignment>
    <name>ui.blockdiagram.direction</name>
    <value>output</value>
   </assignment>
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedReset">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="prSafe">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>conduit</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>locked</name>
    <direction>Output</direction>
    <width>1</width>
    <role>export</role>
   </port>
  </interface>
  <interface name="reset" kind="reset_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <assignment>
    <name>ui.blockdiagram.direction</name>
    <value>input</value>
   </assignment>
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="synchronousEdges">
    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
    <value>NONE</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>reset</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>rst</name>
    <direction>Input</direction>
    <width>1</width>
    <role>reset</role>
   </port>
  </interface>
  <interface name="outclk0" kind="clock_source" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <assignment>
    <name>ui.blockdiagram.direction</name>
    <value>output</value>
   </assignment>
   <parameter name="associatedDirectClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRate">
    <type>long</type>
    <value>310000000</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRateKnown">
    <type>boolean</type>
    <value>true</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>true</isStart>
   <port>
    <name>outclk_0</name>
    <direction>Output</direction>
    <width>1</width>
    <role>clk</role>
   </port>
   <clockDomainMember>
    <isBridge>false</isBridge>
    <moduleName>reset_in</moduleName>
    <slaveName>clk</slaveName>
    <name>reset_in.clk</name>
   </clockDomainMember>
   <clockDomainMember>
    <isBridge>false</isBridge>
    <moduleName>clock_310m</moduleName>
    <slaveName>in_clk</slaveName>
    <name>clock_310m.in_clk</name>
   </clockDomainMember>
   <clockDomainMember>
    <isBridge>false</isBridge>
    <moduleName>emif_lpddr4b</moduleName>
    <slaveName>s0_axi4_clock_in</slaveName>
    <name>emif_lpddr4b.s0_axi4_clock_in</name>
   </clockDomainMember>
  </interface>
  <interface name="outclk1" kind="clock_source" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <assignment>
    <name>ui.blockdiagram.direction</name>
    <value>output</value>
   </assignment>
   <parameter name="associatedDirectClock">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRate">
    <type>long</type>
    <value>155000000</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRateKnown">
    <type>boolean</type>
    <value>true</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>true</isStart>
   <port>
    <name>outclk_1</name>
    <direction>Output</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
 </module>
 <module
   name="reset_in"
   kind="altera_reset_bridge"
   version="19.2.0"
   entity="EMIF_Qsys_reset_in"
   library="EMIF_Qsys_reset_in"
   path="reset_in"
   hpath="reset_in"
   className="altera_generic_component">
  <!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
  <parameter name="componentDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ComponentDefinition</type>
   <value><![CDATA[<componentDefinition>
    <boundary>
        <interfaces>
            <interface>
                <name>clk</name>
                <type>clock</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>clk</name>
                        <role>clk</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>clockRate</key>
                            <value>0</value>
                        </entry>
                        <entry>
                            <key>externallyDriven</key>
                            <value>false</value>
                        </entry>
                        <entry>
                            <key>ptfSchematicName</key>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>in_reset</name>
                <type>reset</type>
                <isStart>false</isStart>
                <ports>
                    <port>
                        <name>in_reset_n</name>
                        <role>reset_n</role>
                        <direction>Input</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                            <value>clk</value>
                        </entry>
                        <entry>
                            <key>synchronousEdges</key>
                            <value>DEASSERT</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
            <interface>
                <name>out_reset</name>
                <type>reset</type>
                <isStart>true</isStart>
                <ports>
                    <port>
                        <name>out_reset_n</name>
                        <role>reset_n</role>
                        <direction>Output</direction>
                        <width>1</width>
                        <lowerBound>0</lowerBound>
                        <vhdlType>STD_LOGIC</vhdlType>
                        <terminationValue>0</terminationValue>
                    </port>
                </ports>
                <assignments>
                    <assignmentValueMap/>
                </assignments>
                <parameters>
                    <parameterValueMap>
                        <entry>
                            <key>associatedClock</key>
                            <value>clk</value>
                        </entry>
                        <entry>
                            <key>associatedDirectReset</key>
                            <value>in_reset</value>
                        </entry>
                        <entry>
                            <key>associatedResetSinks</key>
                            <value>in_reset</value>
                        </entry>
                        <entry>
                            <key>synchronousEdges</key>
                            <value>DEASSERT</value>
                        </entry>
                    </parameterValueMap>
                </parameters>
            </interface>
        </interfaces>
    </boundary>
    <originalModuleInfo>
        <className>altera_reset_bridge</className>
        <version>19.2.0</version>
        <displayName>Reset Bridge IP</displayName>
    </originalModuleInfo>
    <systemInfoParameterDescriptors>
        <descriptors>
            <descriptor>
                <parameterDefaultValue>-1</parameterDefaultValue>
                <parameterName>AUTO_CLK_CLOCK_RATE</parameterName>
                <parameterType>java.lang.Long</parameterType>
                <systemInfoArgs>clk</systemInfoArgs>
                <systemInfotype>CLOCK_RATE</systemInfotype>
            </descriptor>
        </descriptors>
    </systemInfoParameterDescriptors>
    <systemInfos>
        <connPtSystemInfos>
            <entry>
                <key>clk</key>
                <value>
                    <connectionPointName>clk</connectionPointName>
                    <suppliedSystemInfos/>
                    <consumedSystemInfos>
                        <entry>
                            <key>CLOCK_RATE</key>
                            <value>310000000</value>
                        </entry>
                    </consumedSystemInfos>
                </value>
            </entry>
        </connPtSystemInfos>
    </systemInfos>
</componentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generationInfoDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.GenerationInfoDefinition</type>
   <value><![CDATA[<generationInfoDefinition>
    <hdlLibraryName>EMIF_Qsys_reset_in</hdlLibraryName>
    <fileSets>
        <fileSet>
            <fileSetName>EMIF_Qsys_reset_in</fileSetName>
            <fileSetFixedName>EMIF_Qsys_reset_in</fileSetFixedName>
            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_reset_in</fileSetName>
            <fileSetFixedName>EMIF_Qsys_reset_in</fileSetFixedName>
            <fileSetKind>SIM_VERILOG</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_reset_in</fileSetName>
            <fileSetFixedName>EMIF_Qsys_reset_in</fileSetFixedName>
            <fileSetKind>SIM_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_reset_in</fileSetName>
            <fileSetFixedName>EMIF_Qsys_reset_in</fileSetFixedName>
            <fileSetKind>CDC</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
        <fileSet>
            <fileSetName>EMIF_Qsys_reset_in</fileSetName>
            <fileSetFixedName>EMIF_Qsys_reset_in</fileSetFixedName>
            <fileSetKind>CDC_VHDL</fileSetKind>
            <fileSetFiles/>
            <fileSetFileChangeDefs/>
        </fileSet>
    </fileSets>
</generationInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hlsFile">
   <type>java.lang.String</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="logicalView">
   <type>java.lang.String</type>
   <value>ip/EMIF_Qsys/EMIF_Qsys_reset_in.ip</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="defaultBoundary">
   <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
   <value><![CDATA[<boundaryDefinition>
    <interfaces>
        <interface>
            <name>clk</name>
            <type>clock</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>clk</name>
                    <role>clk</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>clockRate</key>
                        <value>0</value>
                    </entry>
                    <entry>
                        <key>externallyDriven</key>
                        <value>false</value>
                    </entry>
                    <entry>
                        <key>ptfSchematicName</key>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>in_reset</name>
            <type>reset</type>
            <isStart>false</isStart>
            <ports>
                <port>
                    <name>in_reset_n</name>
                    <role>reset_n</role>
                    <direction>Input</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                        <value>clk</value>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>DEASSERT</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
        <interface>
            <name>out_reset</name>
            <type>reset</type>
            <isStart>true</isStart>
            <ports>
                <port>
                    <name>out_reset_n</name>
                    <role>reset_n</role>
                    <direction>Output</direction>
                    <width>1</width>
                    <lowerBound>0</lowerBound>
                    <vhdlType>STD_LOGIC</vhdlType>
                    <terminationValue>0</terminationValue>
                </port>
            </ports>
            <assignments>
                <assignmentValueMap/>
            </assignments>
            <parameters>
                <parameterValueMap>
                    <entry>
                        <key>associatedClock</key>
                        <value>clk</value>
                    </entry>
                    <entry>
                        <key>associatedDirectReset</key>
                        <value>in_reset</value>
                    </entry>
                    <entry>
                        <key>associatedResetSinks</key>
                        <value>in_reset</value>
                    </entry>
                    <entry>
                        <key>synchronousEdges</key>
                        <value>DEASSERT</value>
                    </entry>
                </parameterValueMap>
            </parameters>
        </interface>
    </interfaces>
</boundaryDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="moduleAssignmentDefinition">
   <type>com.altera.sopcmodel.definition.AssignmentDefinition</type>
   <value><![CDATA[<assignmentDefinition>
    <assignmentValueMap/>
</assignmentDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="svInterfaceDefinition">
   <type>com.altera.qsys.blackboxmodule.definitions.ModuleSvInterfaceDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="hdlParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.HdlParameterDescriptorDefinitionList</type>
   <value><![CDATA[<hdlParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="transformParameters">
   <type>com.altera.qsys.blackboxmodule.definitions.TransformParameterDescriptorDefinitionList</type>
   <value><![CDATA[<transformParameterDescriptorDefinitionList/>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuInfo">
   <type>com.altera.sopcmodel.ensemble.cpuinfo.serializable.CpuInfoDefinition</type>
   <value></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="bspCpu">
   <type>java.lang.Boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="liveModuleName">
   <type>java.lang.String</type>
   <value>reset_in</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="cpuHashInfo">
   <type>com.altera.sopcmodel.definition.CpuHashInfoDefinition</type>
   <value><![CDATA[<cpuHashInfoDefinition>
    <cpuHashInfoMap/>
</cpuHashInfoDefinition>]]></value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="AUTO_CLK_CLOCK_RATE">
   <type>java.lang.Long</type>
   <value>310000000</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RATE</sysinfo_type>
   <sysinfo_arg>clk</sysinfo_arg>
  </parameter>
  <parameter name="AUTO_DEVICE_FAMILY">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="AUTO_DEVICE">
   <type>java.lang.String</type>
   <value>A5EB013BB23BE4SCS</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>Agilex 5</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <interface name="clk" kind="clock_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="externallyDriven">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="ptfSchematicName">
    <type>java.lang.String</type>
    <value></value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRateKnown">
    <type>java.lang.Boolean</type>
    <value>true</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="clockRate">
    <type>java.lang.Long</type>
    <value>310000000</value>
    <derived>true</derived>
    <enabled>true</enabled>
    <visible>false</visible>
    <valid>true</valid>
   </parameter>
   <type>clock</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>clk</name>
    <direction>Input</direction>
    <width>1</width>
    <role>clk</role>
   </port>
  </interface>
  <interface name="in_reset" kind="reset_sink" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value>clk</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="synchronousEdges">
    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
    <value>DEASSERT</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>reset</type>
   <span>0</span>
   <isStart>false</isStart>
   <port>
    <name>in_reset_n</name>
    <direction>Input</direction>
    <width>1</width>
    <role>reset_n</role>
   </port>
  </interface>
  <interface name="out_reset" kind="reset_source" version="25.3">
   <!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
   <parameter name="associatedClock">
    <type>java.lang.String</type>
    <value>clk</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedDirectReset">
    <type>java.lang.String</type>
    <value>in_reset</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="associatedResetSinks">
    <type>[Ljava.lang.String;</type>
    <value>in_reset</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="synchronousEdges">
    <type>com.altera.sopcmodel.reset.Reset$Edges</type>
    <value>DEASSERT</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="deviceFamily">
    <type>java.lang.String</type>
    <value>UNKNOWN</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <parameter name="generateLegacySim">
    <type>boolean</type>
    <value>false</value>
    <derived>false</derived>
    <enabled>true</enabled>
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
   <type>reset</type>
   <span>0</span>
   <isStart>true</isStart>
   <port>
    <name>out_reset_n</name>
    <direction>Output</direction>
    <width>1</width>
    <role>reset_n</role>
   </port>
  </interface>
 </module>
 <connection
   name="iopll.outclk0/reset_in.clk"
   kind="clock"
   version="25.3"
   start="iopll.outclk0"
   end="reset_in.clk">
  <parameter name="clockRateSysInfo">
   <type>java.lang.Long</type>
   <value>310000000</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RATE</sysinfo_type>
  </parameter>
  <parameter name="clockDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="resetDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>RESET_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="clockResetSysInfo">
   <type>java.lang.String</type>
   <value></value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>UNKNOWN</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <startModule>iopll</startModule>
  <startConnectionPoint>outclk0</startConnectionPoint>
  <endModule>reset_in</endModule>
  <endConnectionPoint>clk</endConnectionPoint>
 </connection>
 <connection
   name="iopll.outclk0/clock_310m.in_clk"
   kind="clock"
   version="25.3"
   start="iopll.outclk0"
   end="clock_310m.in_clk">
  <parameter name="clockRateSysInfo">
   <type>java.lang.Long</type>
   <value>310000000</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RATE</sysinfo_type>
  </parameter>
  <parameter name="clockDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="resetDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>RESET_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="clockResetSysInfo">
   <type>java.lang.String</type>
   <value></value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>UNKNOWN</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <startModule>iopll</startModule>
  <startConnectionPoint>outclk0</startConnectionPoint>
  <endModule>clock_310m</endModule>
  <endConnectionPoint>in_clk</endConnectionPoint>
 </connection>
 <connection
   name="iopll.outclk0/emif_lpddr4b.s0_axi4_clock_in"
   kind="clock"
   version="25.3"
   start="iopll.outclk0"
   end="emif_lpddr4b.s0_axi4_clock_in">
  <parameter name="clockRateSysInfo">
   <type>java.lang.Long</type>
   <value>310000000</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RATE</sysinfo_type>
  </parameter>
  <parameter name="clockDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="resetDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>RESET_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="clockResetSysInfo">
   <type>java.lang.String</type>
   <value></value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>UNKNOWN</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <startModule>iopll</startModule>
  <startConnectionPoint>outclk0</startConnectionPoint>
  <endModule>emif_lpddr4b</endModule>
  <endConnectionPoint>s0_axi4_clock_in</endConnectionPoint>
 </connection>
 <connection
   name="reset_in.out_reset/emif_lpddr4b.core_init_n"
   kind="reset"
   version="25.3"
   start="reset_in.out_reset"
   end="emif_lpddr4b.core_init_n">
  <parameter name="resetDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>RESET_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="clockDomainSysInfo">
   <type>java.lang.Integer</type>
   <value>-1</value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
  </parameter>
  <parameter name="clockResetSysInfo">
   <type>java.lang.String</type>
   <value></value>
   <derived>true</derived>
   <enabled>true</enabled>
   <visible>false</visible>
   <valid>true</valid>
   <sysinfo_type>CLOCK_RESET_INFO</sysinfo_type>
  </parameter>
  <parameter name="deviceFamily">
   <type>java.lang.String</type>
   <value>UNKNOWN</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <parameter name="generateLegacySim">
   <type>boolean</type>
   <value>false</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
   <valid>true</valid>
  </parameter>
  <startModule>reset_in</startModule>
  <startConnectionPoint>out_reset</startConnectionPoint>
  <endModule>emif_lpddr4b</endModule>
  <endConnectionPoint>core_init_n</endConnectionPoint>
 </connection>
 <plugin>
  <instanceCount>4</instanceCount>
  <name>altera_generic_component</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype></subtype>
  <displayName>Generic Component</displayName>
  <version>1.0</version>
 </plugin>
 <plugin>
  <instanceCount>6</instanceCount>
  <name>clock_sink</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>Clock Input</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>3</instanceCount>
  <name>clock_source</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>Clock Output</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>4</instanceCount>
  <name>reset_sink</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>Reset Input</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>2</instanceCount>
  <name>reset_source</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>Reset Output</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>1</instanceCount>
  <name>altera_axi4_slave</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>AXI4 Subordinate</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>1</instanceCount>
  <name>altera_axi4lite_slave</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>AXI4Lite Subordinate</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>5</instanceCount>
  <name>conduit_end</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
  <displayName>Conduit</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>3</instanceCount>
  <name>clock</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IConnection</subtype>
  <displayName>Clock Connection</displayName>
  <version>25.3</version>
 </plugin>
 <plugin>
  <instanceCount>1</instanceCount>
  <name>reset</name>
  <type>com.altera.entityinterfaces.IElementClass</type>
  <subtype>com.altera.entityinterfaces.IConnection</subtype>
  <displayName>Reset Connection</displayName>
  <version>25.3</version>
 </plugin>
 <reportVersion>25.3.1 100</reportVersion>
 <uniqueIdentifier></uniqueIdentifier>
</EnsembleReport>
