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   library="emif_io96b_cal_232">
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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 <file
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   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_noc.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_wide.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_slim.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pa.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pll.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_reftree.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_hmc.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_lane.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_wide.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_slim.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_io96b_top.sv"
   type="SYSTEM_VERILOG"
   library="emif_io96b_lpddr4_420">
  <include path="emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh" />
 </file>
 <file
   path="sim/EMIF_Qsys_emif_ddr4a_0.v"
   type="VERILOG"
   library="EMIF_Qsys_emif_ddr4a_0"
   hasInlineConfiguration="true" />
 <topLevel name="EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0" />
 <deviceFamily name="agilex5" />
 <device name="A5EB013BB23BE4SCS" />
</simPackage>
