	component EMIF_Qsys is
		port (
			clock_310m_out_clk_clk                   : out   std_logic;                                         -- clk
			emif_lpddr4b_s0_axi4_ctrl_ready_reset_n  : out   std_logic;                                         -- reset_n
			emif_lpddr4b_s0_axi4_awaddr              : in    std_logic_vector(29 downto 0)  := (others => 'X'); -- awaddr
			emif_lpddr4b_s0_axi4_awburst             : in    std_logic_vector(1 downto 0)   := (others => 'X'); -- awburst
			emif_lpddr4b_s0_axi4_awid                : in    std_logic_vector(6 downto 0)   := (others => 'X'); -- awid
			emif_lpddr4b_s0_axi4_awlen               : in    std_logic_vector(7 downto 0)   := (others => 'X'); -- awlen
			emif_lpddr4b_s0_axi4_awlock              : in    std_logic                      := 'X';             -- awlock
			emif_lpddr4b_s0_axi4_awqos               : in    std_logic_vector(3 downto 0)   := (others => 'X'); -- awqos
			emif_lpddr4b_s0_axi4_awsize              : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- awsize
			emif_lpddr4b_s0_axi4_awvalid             : in    std_logic                      := 'X';             -- awvalid
			emif_lpddr4b_s0_axi4_awuser              : in    std_logic_vector(13 downto 0)  := (others => 'X'); -- awuser
			emif_lpddr4b_s0_axi4_awprot              : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- awprot
			emif_lpddr4b_s0_axi4_awready             : out   std_logic;                                         -- awready
			emif_lpddr4b_s0_axi4_araddr              : in    std_logic_vector(29 downto 0)  := (others => 'X'); -- araddr
			emif_lpddr4b_s0_axi4_arburst             : in    std_logic_vector(1 downto 0)   := (others => 'X'); -- arburst
			emif_lpddr4b_s0_axi4_arid                : in    std_logic_vector(6 downto 0)   := (others => 'X'); -- arid
			emif_lpddr4b_s0_axi4_arlen               : in    std_logic_vector(7 downto 0)   := (others => 'X'); -- arlen
			emif_lpddr4b_s0_axi4_arlock              : in    std_logic                      := 'X';             -- arlock
			emif_lpddr4b_s0_axi4_arqos               : in    std_logic_vector(3 downto 0)   := (others => 'X'); -- arqos
			emif_lpddr4b_s0_axi4_arsize              : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- arsize
			emif_lpddr4b_s0_axi4_arvalid             : in    std_logic                      := 'X';             -- arvalid
			emif_lpddr4b_s0_axi4_aruser              : in    std_logic_vector(13 downto 0)  := (others => 'X'); -- aruser
			emif_lpddr4b_s0_axi4_arprot              : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- arprot
			emif_lpddr4b_s0_axi4_arready             : out   std_logic;                                         -- arready
			emif_lpddr4b_s0_axi4_wdata               : in    std_logic_vector(255 downto 0) := (others => 'X'); -- wdata
			emif_lpddr4b_s0_axi4_wstrb               : in    std_logic_vector(31 downto 0)  := (others => 'X'); -- wstrb
			emif_lpddr4b_s0_axi4_wlast               : in    std_logic                      := 'X';             -- wlast
			emif_lpddr4b_s0_axi4_wvalid              : in    std_logic                      := 'X';             -- wvalid
			emif_lpddr4b_s0_axi4_wready              : out   std_logic;                                         -- wready
			emif_lpddr4b_s0_axi4_bready              : in    std_logic                      := 'X';             -- bready
			emif_lpddr4b_s0_axi4_bid                 : out   std_logic_vector(6 downto 0);                      -- bid
			emif_lpddr4b_s0_axi4_bresp               : out   std_logic_vector(1 downto 0);                      -- bresp
			emif_lpddr4b_s0_axi4_bvalid              : out   std_logic;                                         -- bvalid
			emif_lpddr4b_s0_axi4_rready              : in    std_logic                      := 'X';             -- rready
			emif_lpddr4b_s0_axi4_rdata               : out   std_logic_vector(255 downto 0);                    -- rdata
			emif_lpddr4b_s0_axi4_rid                 : out   std_logic_vector(6 downto 0);                      -- rid
			emif_lpddr4b_s0_axi4_rlast               : out   std_logic;                                         -- rlast
			emif_lpddr4b_s0_axi4_rresp               : out   std_logic_vector(1 downto 0);                      -- rresp
			emif_lpddr4b_s0_axi4_rvalid              : out   std_logic;                                         -- rvalid
			emif_lpddr4b_s0_axi4lite_clock_clk       : in    std_logic                      := 'X';             -- clk
			emif_lpddr4b_s0_axi4lite_reset_n_reset_n : in    std_logic                      := 'X';             -- reset_n
			emif_lpddr4b_s0_axi4lite_awaddr          : in    std_logic_vector(26 downto 0)  := (others => 'X'); -- awaddr
			emif_lpddr4b_s0_axi4lite_awprot          : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- awprot
			emif_lpddr4b_s0_axi4lite_awvalid         : in    std_logic                      := 'X';             -- awvalid
			emif_lpddr4b_s0_axi4lite_awready         : out   std_logic;                                         -- awready
			emif_lpddr4b_s0_axi4lite_araddr          : in    std_logic_vector(26 downto 0)  := (others => 'X'); -- araddr
			emif_lpddr4b_s0_axi4lite_arprot          : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- arprot
			emif_lpddr4b_s0_axi4lite_arvalid         : in    std_logic                      := 'X';             -- arvalid
			emif_lpddr4b_s0_axi4lite_arready         : out   std_logic;                                         -- arready
			emif_lpddr4b_s0_axi4lite_wdata           : in    std_logic_vector(31 downto 0)  := (others => 'X'); -- wdata
			emif_lpddr4b_s0_axi4lite_wstrb           : in    std_logic_vector(3 downto 0)   := (others => 'X'); -- wstrb
			emif_lpddr4b_s0_axi4lite_wvalid          : in    std_logic                      := 'X';             -- wvalid
			emif_lpddr4b_s0_axi4lite_wready          : out   std_logic;                                         -- wready
			emif_lpddr4b_s0_axi4lite_bready          : in    std_logic                      := 'X';             -- bready
			emif_lpddr4b_s0_axi4lite_bresp           : out   std_logic_vector(1 downto 0);                      -- bresp
			emif_lpddr4b_s0_axi4lite_bvalid          : out   std_logic;                                         -- bvalid
			emif_lpddr4b_s0_axi4lite_rready          : in    std_logic                      := 'X';             -- rready
			emif_lpddr4b_s0_axi4lite_rdata           : out   std_logic_vector(31 downto 0);                     -- rdata
			emif_lpddr4b_s0_axi4lite_rresp           : out   std_logic_vector(1 downto 0);                      -- rresp
			emif_lpddr4b_s0_axi4lite_rvalid          : out   std_logic;                                         -- rvalid
			emif_lpddr4b_mem_mem_cs                  : out   std_logic_vector(0 downto 0);                      -- mem_cs
			emif_lpddr4b_mem_mem_ca                  : out   std_logic_vector(5 downto 0);                      -- mem_ca
			emif_lpddr4b_mem_mem_cke                 : out   std_logic_vector(0 downto 0);                      -- mem_cke
			emif_lpddr4b_mem_mem_dq                  : inout std_logic_vector(31 downto 0)  := (others => 'X'); -- mem_dq
			emif_lpddr4b_mem_mem_dqs_t               : inout std_logic_vector(3 downto 0)   := (others => 'X'); -- mem_dqs_t
			emif_lpddr4b_mem_mem_dqs_c               : inout std_logic_vector(3 downto 0)   := (others => 'X'); -- mem_dqs_c
			emif_lpddr4b_mem_mem_dmi                 : inout std_logic_vector(3 downto 0)   := (others => 'X'); -- mem_dmi
			emif_lpddr4b_mem_ck_mem_ck_t             : out   std_logic_vector(0 downto 0);                      -- mem_ck_t
			emif_lpddr4b_mem_ck_mem_ck_c             : out   std_logic_vector(0 downto 0);                      -- mem_ck_c
			emif_lpddr4b_mem_reset_n_mem_reset_n     : out   std_logic;                                         -- mem_reset_n
			emif_lpddr4b_oct_oct_rzqin               : in    std_logic                      := 'X';             -- oct_rzqin
			emif_lpddr4b_ref_clk_clk                 : in    std_logic                      := 'X';             -- clk
			iopll_refclk_clk                         : in    std_logic                      := 'X';             -- clk
			iopll_locked_export                      : out   std_logic;                                         -- export
			iopll_reset_reset                        : in    std_logic                      := 'X';             -- reset
			iopll_outclk_axi4_lite_clk               : out   std_logic;                                         -- clk
			reset_reset_n                            : in    std_logic                      := 'X'              -- reset_n
		);
	end component EMIF_Qsys;

