set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_NAME "QsysPrimePro"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_VERSION "25.3.1"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_ENV "QsysPrimePro"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOOL_VENDOR_NAME "Intel Corporation"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TOP_LEVEL_COMPONENT_NAME "altera_clock_bridge"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name PRE_COMPILED_MODULE "ON"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_FILE [file join $::quartus(qip_path) "../EMIF_Qsys_clock_bridge_0.ip"]
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_TYPE "altera_clock_bridge"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_VERSION "19.2.0"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name OCS_IP_HASH "njakcna"
set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "EMIF_Qsys_clock_bridge_0.sopcinfo"]
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name SLD_INFO "QSYS_NAME EMIF_Qsys_clock_bridge_0 HAS_SOPCINFO 1 GENERATION_ID 0"
set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name MISC_FILE [file join $::quartus(qip_path) "EMIF_Qsys_clock_bridge_0.cmp"]
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_TARGETED_DEVICE_FAMILY "Agilex 5"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_GENERATED_DEVICE_FAMILY "{Agilex 5}"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_QSYS_MODE "STANDALONE"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name MISC_FILE [file join $::quartus(qip_path) "../EMIF_Qsys_clock_bridge_0.ip"]

set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_NAME "RU1JRl9Rc3lzX2Nsb2NrX2JyaWRnZV8w"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
set_global_assignment -entity "EMIF_Qsys_clock_bridge_0" -library "EMIF_Qsys_clock_bridge_0" -name IP_COMPONENT_VERSION "MS4w"


set_global_assignment -library "EMIF_Qsys_clock_bridge_0" -name VERILOG_FILE [file join $::quartus(qip_path) "synth/EMIF_Qsys_clock_bridge_0.v"]

