Info: Generated by version: 25.3.1 build 100
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/EMIF_Qsys.qsys --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE/ip/emif_lpddr4b/EMIF_Qsys --family="Agilex 5" --part=A5EB013BB23BE4SCS
Progress: Loading emif_lpddr4b/EMIF_Qsys.qsys
Progress: Reading input file
Progress: Parameterizing module clock_310m
Progress: Parameterizing module emif_lpddr4b
Progress: Parameterizing module iopll
Progress: Parameterizing module reset_in
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: EMIF_Qsys: "Transforming system: EMIF_Qsys"
Info: EMIF_Qsys: "Naming system components in system: EMIF_Qsys"
Info: EMIF_Qsys: "Processing generation queue"
Info: EMIF_Qsys: "Generating: EMIF_Qsys"
Info: EMIF_Qsys: "Generating: EMIF_Qsys_clock_bridge_0"
Info: EMIF_Qsys: "Generating: EMIF_Qsys_emif_ddr4a_0"
Info: EMIF_Qsys: "Generating: EMIF_Qsys_iopll_0"
Info: EMIF_Qsys: "Generating: EMIF_Qsys_reset_in"
Info: EMIF_Qsys: Done "EMIF_Qsys" with 5 modules, 1 files
Info: Finished: Create HDL design files for synthesis
