# system info EMIF_Qsys_emif_ddr4a_0 on 2026.04.08.11:54:31
system_info:
name,value
DEVICE,A5EB013BB23BE4SCS
DEVICE_FAMILY,Agilex 5
GENERATION_ID,0
#
#
# Files generated for EMIF_Qsys_emif_ddr4a_0 on 2026.04.08.11:54:31
files:
filepath,kind,attributes,module,is_top
sim/EMIF_Qsys_emif_ddr4a_0.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0,true
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_arch_top.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/altera_std_synchronizer_nocut.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/emif_io96b_interface.svh,SYSTEM_VERILOG_INCLUDE,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/emif_io96b_lib.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/emif_io96b_clk_div.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_jedec_params.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pin_locations.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_byte_ctrl.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_cpa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_hmc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_hmc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_c2p_lane.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_p2c_lane.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_fa_noc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_wide.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_hmc_slim.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_pll.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_attr_bufs_mem.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_sim.hex,HEX,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_mc_wide_seq_pt_sim.txt,OTHER,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_bufs_mem.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_byte_ctrl.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_cpa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_noc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_wide.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_hmc_slim.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_pll.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_reftree.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_hmc.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_atom_inst_fa_lane.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_wide.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_fbr_axi_adapter_slim.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/io96b_0/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei_io96b_top.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei,false
emif_io96b_lpddr4_420/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby,false
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_c2p_ssm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_fa_p2c_ssm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_iossm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/io0_EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_atom_attr_seq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/iossm_cal_boot.hex,HEX,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/iossm_cal.hex,HEX,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_arbitrator.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_top.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_iossm.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_seq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_fa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq_cal_arch_fp_atom_inst_comp.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/cal_io96b_interface.svh,SYSTEM_VERILOG_INCLUDE,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/altera_emif_cal_gearbox.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/altera_emif_cal_gearbox_bidir.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_translator_1931_d46vvwa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_reset_controller.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_bytes_to_packets.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_avalon_packets_to_master.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_master_ni_1962_2kryw2a.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_merlin_reorder_memory.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_7ekoqry.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_1921_bk6lvda.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_channel_adapter_1921_fkajlia.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_jy53pgi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_ctb2miq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_7b7u3ni.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_252f2xa.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_pri_mux_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_comp_sel_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_channel_adapter_1921_5wnzrci.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_packets_to_bytes.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_sipo_plus_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_response_mem_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_comp_sel_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_response_mem_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_sipo_plus_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_comp_sel_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_sipo_plus_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_sipo_plus_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_vnonqiy.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_alj3kza.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_ysgnmwa.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/compare_eq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_response_mem_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_response_mem_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_pri_mux_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/rd_comp_sel_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_o34766q.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_pri_mux_kt2puei.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/wr_pri_mux_cwyib4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_h6wexfa.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_cgpn6xq.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_avalon_sc_fifo_1931_fzgstwy.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_2qdsena.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_master_agent_1921_2inlndi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_rcor4va.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_ekcygpi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_c2mlp5i.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_merlin_address_alignment.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_sqfzewq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1931_glj62si.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_uncmpr.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_new.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_burst_adapter_1931_hbsisni.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_wrap_burst_converter.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_merlin_burst_adapter_13_1.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_incr_burst_converter.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_default_burst_converter.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_timing_adapter_1940_5ju4ddy.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_dcfifo_s.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_util.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/intel_axi4lite_injector_ph2.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_intel_axi4lite_injector_100_2yowc3a.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_hs_clk_xer_1940_hvja46q.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_hs_clk_xer_1940_4s7hdhy.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_mm_interconnect_1920_jmzr6ly.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_mm_interconnect_1920_5sovoyi.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_master_translator_192_lykd4la.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_std_synchronizer_nocut.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_reset_synchronizer.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_pipeline_base.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/altera_avalon_st_clock_crosser.v,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_vbaxzva.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_nxsnrbi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_irryw4q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_wqohhgi.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_4ytgf2y.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/interconnect/ed_synth_dut_altera_merlin_router_1921_2jqun3q.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq,false
emif_io96b_cal_232/sim/EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa,false
alt_mem_if_jtag_master_191/sim/EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi.v,VERILOG,CONTAINS_INLINE_CONFIGURATION,EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_jtag_dc_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_jtag_sld_node.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_jtag_streaming.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_clock_crosser.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_reset_synchronizer.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_std_synchronizer_nocut.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_base.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_remover.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_idle_inserter.v,VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_pipeline_stage.sv,SYSTEM_VERILOG,,altera_avalon_st_jtag_interface,false
altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.sdc,SDC_ENTITY,NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION,altera_avalon_st_jtag_interface,false
timing_adapter_1950/sim/EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq,false
altera_avalon_sc_fifo_1932/sim/EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq.v,VERILOG,,EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq,false
altera_avalon_st_bytes_to_packets_1922/sim/altera_avalon_st_bytes_to_packets.v,VERILOG,,altera_avalon_st_bytes_to_packets,false
altera_avalon_st_packets_to_bytes_1922/sim/altera_avalon_st_packets_to_bytes.v,VERILOG,,altera_avalon_st_packets_to_bytes,false
altera_avalon_packets_to_master_1922/sim/altera_avalon_packets_to_master.v,VERILOG,,altera_avalon_packets_to_master,false
channel_adapter_1922/sim/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy,false
channel_adapter_1922/sim/EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a.sv,SYSTEM_VERILOG,,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a,false
altera_reset_controller_1924/sim/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
altera_reset_controller_1924/sim/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
altera_reset_controller_1924/sim/altera_reset_controller.sdc,SDC_ENTITY,NO_SDC_PROMOTION,altera_reset_controller,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_420_ddgvvei
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0,EMIF_Qsys_emif_ddr4a_0_emif_io96b_lpddr4_emif_io96b_cal_420_ym42tby
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_232_l4guqcq
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb,EMIF_Qsys_emif_ddr4a_0_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb,EMIF_Qsys_emif_ddr4a_0_alt_mem_if_jtag_master_191_2xbfrbi
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.jtag_phy_embedded_in_jtag_master,altera_avalon_st_jtag_interface
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.timing_adt,EMIF_Qsys_emif_ddr4a_0_timing_adapter_1950_bbjt6kq
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.fifo,EMIF_Qsys_emif_ddr4a_0_altera_avalon_sc_fifo_1932_onpcouq
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.b2p,altera_avalon_st_bytes_to_packets
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.p2b,altera_avalon_st_packets_to_bytes
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.transacto,altera_avalon_packets_to_master
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.b2p_adapter,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_rd56ufy
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.p2b_adapter,EMIF_Qsys_emif_ddr4a_0_channel_adapter_1922_5vp3d5a
EMIF_Qsys_emif_ddr4a_0.EMIF_Qsys_emif_ddr4a_0.cal_0.cal_0.jamb.jamb.rst_controller,altera_reset_controller
