// EMIF_Qsys.v

// Generated using ACDS version 25.3.1 100

`timescale 1 ps / 1 ps
module EMIF_Qsys (
		output wire         clock_310m_out_clk_clk,                   //               clock_310m_out_clk.clk
		output wire         emif_lpddr4b_s0_axi4_ctrl_ready_reset_n,  //  emif_lpddr4b_s0_axi4_ctrl_ready.reset_n
		input  wire [29:0]  emif_lpddr4b_s0_axi4_awaddr,              //             emif_lpddr4b_s0_axi4.awaddr
		input  wire [1:0]   emif_lpddr4b_s0_axi4_awburst,             //                                 .awburst
		input  wire [6:0]   emif_lpddr4b_s0_axi4_awid,                //                                 .awid
		input  wire [7:0]   emif_lpddr4b_s0_axi4_awlen,               //                                 .awlen
		input  wire         emif_lpddr4b_s0_axi4_awlock,              //                                 .awlock
		input  wire [3:0]   emif_lpddr4b_s0_axi4_awqos,               //                                 .awqos
		input  wire [2:0]   emif_lpddr4b_s0_axi4_awsize,              //                                 .awsize
		input  wire         emif_lpddr4b_s0_axi4_awvalid,             //                                 .awvalid
		input  wire [13:0]  emif_lpddr4b_s0_axi4_awuser,              //                                 .awuser
		input  wire [2:0]   emif_lpddr4b_s0_axi4_awprot,              //                                 .awprot
		output wire         emif_lpddr4b_s0_axi4_awready,             //                                 .awready
		input  wire [29:0]  emif_lpddr4b_s0_axi4_araddr,              //                                 .araddr
		input  wire [1:0]   emif_lpddr4b_s0_axi4_arburst,             //                                 .arburst
		input  wire [6:0]   emif_lpddr4b_s0_axi4_arid,                //                                 .arid
		input  wire [7:0]   emif_lpddr4b_s0_axi4_arlen,               //                                 .arlen
		input  wire         emif_lpddr4b_s0_axi4_arlock,              //                                 .arlock
		input  wire [3:0]   emif_lpddr4b_s0_axi4_arqos,               //                                 .arqos
		input  wire [2:0]   emif_lpddr4b_s0_axi4_arsize,              //                                 .arsize
		input  wire         emif_lpddr4b_s0_axi4_arvalid,             //                                 .arvalid
		input  wire [13:0]  emif_lpddr4b_s0_axi4_aruser,              //                                 .aruser
		input  wire [2:0]   emif_lpddr4b_s0_axi4_arprot,              //                                 .arprot
		output wire         emif_lpddr4b_s0_axi4_arready,             //                                 .arready
		input  wire [255:0] emif_lpddr4b_s0_axi4_wdata,               //                                 .wdata
		input  wire [31:0]  emif_lpddr4b_s0_axi4_wstrb,               //                                 .wstrb
		input  wire         emif_lpddr4b_s0_axi4_wlast,               //                                 .wlast
		input  wire         emif_lpddr4b_s0_axi4_wvalid,              //                                 .wvalid
		output wire         emif_lpddr4b_s0_axi4_wready,              //                                 .wready
		input  wire         emif_lpddr4b_s0_axi4_bready,              //                                 .bready
		output wire [6:0]   emif_lpddr4b_s0_axi4_bid,                 //                                 .bid
		output wire [1:0]   emif_lpddr4b_s0_axi4_bresp,               //                                 .bresp
		output wire         emif_lpddr4b_s0_axi4_bvalid,              //                                 .bvalid
		input  wire         emif_lpddr4b_s0_axi4_rready,              //                                 .rready
		output wire [255:0] emif_lpddr4b_s0_axi4_rdata,               //                                 .rdata
		output wire [6:0]   emif_lpddr4b_s0_axi4_rid,                 //                                 .rid
		output wire         emif_lpddr4b_s0_axi4_rlast,               //                                 .rlast
		output wire [1:0]   emif_lpddr4b_s0_axi4_rresp,               //                                 .rresp
		output wire         emif_lpddr4b_s0_axi4_rvalid,              //                                 .rvalid
		input  wire         emif_lpddr4b_s0_axi4lite_clock_clk,       //   emif_lpddr4b_s0_axi4lite_clock.clk
		input  wire         emif_lpddr4b_s0_axi4lite_reset_n_reset_n, // emif_lpddr4b_s0_axi4lite_reset_n.reset_n
		input  wire [26:0]  emif_lpddr4b_s0_axi4lite_awaddr,          //         emif_lpddr4b_s0_axi4lite.awaddr
		input  wire [2:0]   emif_lpddr4b_s0_axi4lite_awprot,          //                                 .awprot
		input  wire         emif_lpddr4b_s0_axi4lite_awvalid,         //                                 .awvalid
		output wire         emif_lpddr4b_s0_axi4lite_awready,         //                                 .awready
		input  wire [26:0]  emif_lpddr4b_s0_axi4lite_araddr,          //                                 .araddr
		input  wire [2:0]   emif_lpddr4b_s0_axi4lite_arprot,          //                                 .arprot
		input  wire         emif_lpddr4b_s0_axi4lite_arvalid,         //                                 .arvalid
		output wire         emif_lpddr4b_s0_axi4lite_arready,         //                                 .arready
		input  wire [31:0]  emif_lpddr4b_s0_axi4lite_wdata,           //                                 .wdata
		input  wire [3:0]   emif_lpddr4b_s0_axi4lite_wstrb,           //                                 .wstrb
		input  wire         emif_lpddr4b_s0_axi4lite_wvalid,          //                                 .wvalid
		output wire         emif_lpddr4b_s0_axi4lite_wready,          //                                 .wready
		input  wire         emif_lpddr4b_s0_axi4lite_bready,          //                                 .bready
		output wire [1:0]   emif_lpddr4b_s0_axi4lite_bresp,           //                                 .bresp
		output wire         emif_lpddr4b_s0_axi4lite_bvalid,          //                                 .bvalid
		input  wire         emif_lpddr4b_s0_axi4lite_rready,          //                                 .rready
		output wire [31:0]  emif_lpddr4b_s0_axi4lite_rdata,           //                                 .rdata
		output wire [1:0]   emif_lpddr4b_s0_axi4lite_rresp,           //                                 .rresp
		output wire         emif_lpddr4b_s0_axi4lite_rvalid,          //                                 .rvalid
		output wire [0:0]   emif_lpddr4b_mem_mem_cs,                  //                 emif_lpddr4b_mem.mem_cs
		output wire [5:0]   emif_lpddr4b_mem_mem_ca,                  //                                 .mem_ca
		output wire [0:0]   emif_lpddr4b_mem_mem_cke,                 //                                 .mem_cke
		inout  wire [31:0]  emif_lpddr4b_mem_mem_dq,                  //                                 .mem_dq
		inout  wire [3:0]   emif_lpddr4b_mem_mem_dqs_t,               //                                 .mem_dqs_t
		inout  wire [3:0]   emif_lpddr4b_mem_mem_dqs_c,               //                                 .mem_dqs_c
		inout  wire [3:0]   emif_lpddr4b_mem_mem_dmi,                 //                                 .mem_dmi
		output wire [0:0]   emif_lpddr4b_mem_ck_mem_ck_t,             //              emif_lpddr4b_mem_ck.mem_ck_t
		output wire [0:0]   emif_lpddr4b_mem_ck_mem_ck_c,             //                                 .mem_ck_c
		output wire         emif_lpddr4b_mem_reset_n_mem_reset_n,     //         emif_lpddr4b_mem_reset_n.mem_reset_n
		input  wire         emif_lpddr4b_oct_oct_rzqin,               //                 emif_lpddr4b_oct.oct_rzqin
		input  wire         emif_lpddr4b_ref_clk_clk,                 //             emif_lpddr4b_ref_clk.clk
		input  wire         iopll_refclk_clk,                         //                     iopll_refclk.clk
		output wire         iopll_locked_export,                      //                     iopll_locked.export
		input  wire         iopll_reset_reset,                        //                      iopll_reset.reset
		output wire         iopll_outclk_axi4_lite_clk,               //           iopll_outclk_axi4_lite.clk
		input  wire         reset_reset_n                             //                            reset.reset_n
	);

	wire    iopll_outclk0_clk;        // iopll:outclk_0 -> [clock_310m:in_clk, emif_lpddr4b:s0_axi4_clock_in, reset_in:clk]
	wire    reset_in_out_reset_reset; // reset_in:out_reset_n -> emif_lpddr4b:core_init_n

	EMIF_Qsys_clock_bridge_0 clock_310m (
		.in_clk  (iopll_outclk0_clk),      //   input,  width = 1,  in_clk.clk
		.out_clk (clock_310m_out_clk_clk)  //  output,  width = 1, out_clk.clk
	);

	EMIF_Qsys_emif_ddr4a_0 emif_lpddr4b (
		.s0_axi4_clock_in    (iopll_outclk0_clk),                        //   input,    width = 1,    s0_axi4_clock_in.clk
		.core_init_n         (reset_in_out_reset_reset),                 //   input,    width = 1,         core_init_n.reset_n
		.s0_axi4_reset_n     (emif_lpddr4b_s0_axi4_ctrl_ready_reset_n),  //  output,    width = 1,  s0_axi4_ctrl_ready.reset_n
		.s0_axi4_awaddr      (emif_lpddr4b_s0_axi4_awaddr),              //   input,   width = 30,             s0_axi4.awaddr
		.s0_axi4_awburst     (emif_lpddr4b_s0_axi4_awburst),             //   input,    width = 2,                    .awburst
		.s0_axi4_awid        (emif_lpddr4b_s0_axi4_awid),                //   input,    width = 7,                    .awid
		.s0_axi4_awlen       (emif_lpddr4b_s0_axi4_awlen),               //   input,    width = 8,                    .awlen
		.s0_axi4_awlock      (emif_lpddr4b_s0_axi4_awlock),              //   input,    width = 1,                    .awlock
		.s0_axi4_awqos       (emif_lpddr4b_s0_axi4_awqos),               //   input,    width = 4,                    .awqos
		.s0_axi4_awsize      (emif_lpddr4b_s0_axi4_awsize),              //   input,    width = 3,                    .awsize
		.s0_axi4_awvalid     (emif_lpddr4b_s0_axi4_awvalid),             //   input,    width = 1,                    .awvalid
		.s0_axi4_awuser      (emif_lpddr4b_s0_axi4_awuser),              //   input,   width = 14,                    .awuser
		.s0_axi4_awprot      (emif_lpddr4b_s0_axi4_awprot),              //   input,    width = 3,                    .awprot
		.s0_axi4_awready     (emif_lpddr4b_s0_axi4_awready),             //  output,    width = 1,                    .awready
		.s0_axi4_araddr      (emif_lpddr4b_s0_axi4_araddr),              //   input,   width = 30,                    .araddr
		.s0_axi4_arburst     (emif_lpddr4b_s0_axi4_arburst),             //   input,    width = 2,                    .arburst
		.s0_axi4_arid        (emif_lpddr4b_s0_axi4_arid),                //   input,    width = 7,                    .arid
		.s0_axi4_arlen       (emif_lpddr4b_s0_axi4_arlen),               //   input,    width = 8,                    .arlen
		.s0_axi4_arlock      (emif_lpddr4b_s0_axi4_arlock),              //   input,    width = 1,                    .arlock
		.s0_axi4_arqos       (emif_lpddr4b_s0_axi4_arqos),               //   input,    width = 4,                    .arqos
		.s0_axi4_arsize      (emif_lpddr4b_s0_axi4_arsize),              //   input,    width = 3,                    .arsize
		.s0_axi4_arvalid     (emif_lpddr4b_s0_axi4_arvalid),             //   input,    width = 1,                    .arvalid
		.s0_axi4_aruser      (emif_lpddr4b_s0_axi4_aruser),              //   input,   width = 14,                    .aruser
		.s0_axi4_arprot      (emif_lpddr4b_s0_axi4_arprot),              //   input,    width = 3,                    .arprot
		.s0_axi4_arready     (emif_lpddr4b_s0_axi4_arready),             //  output,    width = 1,                    .arready
		.s0_axi4_wdata       (emif_lpddr4b_s0_axi4_wdata),               //   input,  width = 256,                    .wdata
		.s0_axi4_wstrb       (emif_lpddr4b_s0_axi4_wstrb),               //   input,   width = 32,                    .wstrb
		.s0_axi4_wlast       (emif_lpddr4b_s0_axi4_wlast),               //   input,    width = 1,                    .wlast
		.s0_axi4_wvalid      (emif_lpddr4b_s0_axi4_wvalid),              //   input,    width = 1,                    .wvalid
		.s0_axi4_wready      (emif_lpddr4b_s0_axi4_wready),              //  output,    width = 1,                    .wready
		.s0_axi4_bready      (emif_lpddr4b_s0_axi4_bready),              //   input,    width = 1,                    .bready
		.s0_axi4_bid         (emif_lpddr4b_s0_axi4_bid),                 //  output,    width = 7,                    .bid
		.s0_axi4_bresp       (emif_lpddr4b_s0_axi4_bresp),               //  output,    width = 2,                    .bresp
		.s0_axi4_bvalid      (emif_lpddr4b_s0_axi4_bvalid),              //  output,    width = 1,                    .bvalid
		.s0_axi4_rready      (emif_lpddr4b_s0_axi4_rready),              //   input,    width = 1,                    .rready
		.s0_axi4_rdata       (emif_lpddr4b_s0_axi4_rdata),               //  output,  width = 256,                    .rdata
		.s0_axi4_rid         (emif_lpddr4b_s0_axi4_rid),                 //  output,    width = 7,                    .rid
		.s0_axi4_rlast       (emif_lpddr4b_s0_axi4_rlast),               //  output,    width = 1,                    .rlast
		.s0_axi4_rresp       (emif_lpddr4b_s0_axi4_rresp),               //  output,    width = 2,                    .rresp
		.s0_axi4_rvalid      (emif_lpddr4b_s0_axi4_rvalid),              //  output,    width = 1,                    .rvalid
		.s0_axi4lite_clock   (emif_lpddr4b_s0_axi4lite_clock_clk),       //   input,    width = 1,   s0_axi4lite_clock.clk
		.s0_axi4lite_reset_n (emif_lpddr4b_s0_axi4lite_reset_n_reset_n), //   input,    width = 1, s0_axi4lite_reset_n.reset_n
		.s0_axi4lite_awaddr  (emif_lpddr4b_s0_axi4lite_awaddr),          //   input,   width = 27,         s0_axi4lite.awaddr
		.s0_axi4lite_awprot  (emif_lpddr4b_s0_axi4lite_awprot),          //   input,    width = 3,                    .awprot
		.s0_axi4lite_awvalid (emif_lpddr4b_s0_axi4lite_awvalid),         //   input,    width = 1,                    .awvalid
		.s0_axi4lite_awready (emif_lpddr4b_s0_axi4lite_awready),         //  output,    width = 1,                    .awready
		.s0_axi4lite_araddr  (emif_lpddr4b_s0_axi4lite_araddr),          //   input,   width = 27,                    .araddr
		.s0_axi4lite_arprot  (emif_lpddr4b_s0_axi4lite_arprot),          //   input,    width = 3,                    .arprot
		.s0_axi4lite_arvalid (emif_lpddr4b_s0_axi4lite_arvalid),         //   input,    width = 1,                    .arvalid
		.s0_axi4lite_arready (emif_lpddr4b_s0_axi4lite_arready),         //  output,    width = 1,                    .arready
		.s0_axi4lite_wdata   (emif_lpddr4b_s0_axi4lite_wdata),           //   input,   width = 32,                    .wdata
		.s0_axi4lite_wstrb   (emif_lpddr4b_s0_axi4lite_wstrb),           //   input,    width = 4,                    .wstrb
		.s0_axi4lite_wvalid  (emif_lpddr4b_s0_axi4lite_wvalid),          //   input,    width = 1,                    .wvalid
		.s0_axi4lite_wready  (emif_lpddr4b_s0_axi4lite_wready),          //  output,    width = 1,                    .wready
		.s0_axi4lite_bready  (emif_lpddr4b_s0_axi4lite_bready),          //   input,    width = 1,                    .bready
		.s0_axi4lite_bresp   (emif_lpddr4b_s0_axi4lite_bresp),           //  output,    width = 2,                    .bresp
		.s0_axi4lite_bvalid  (emif_lpddr4b_s0_axi4lite_bvalid),          //  output,    width = 1,                    .bvalid
		.s0_axi4lite_rready  (emif_lpddr4b_s0_axi4lite_rready),          //   input,    width = 1,                    .rready
		.s0_axi4lite_rdata   (emif_lpddr4b_s0_axi4lite_rdata),           //  output,   width = 32,                    .rdata
		.s0_axi4lite_rresp   (emif_lpddr4b_s0_axi4lite_rresp),           //  output,    width = 2,                    .rresp
		.s0_axi4lite_rvalid  (emif_lpddr4b_s0_axi4lite_rvalid),          //  output,    width = 1,                    .rvalid
		.mem_0_cs            (emif_lpddr4b_mem_mem_cs),                  //  output,    width = 1,               mem_0.mem_cs
		.mem_0_ca            (emif_lpddr4b_mem_mem_ca),                  //  output,    width = 6,                    .mem_ca
		.mem_0_cke           (emif_lpddr4b_mem_mem_cke),                 //  output,    width = 1,                    .mem_cke
		.mem_0_dq            (emif_lpddr4b_mem_mem_dq),                  //   inout,   width = 32,                    .mem_dq
		.mem_0_dqs_t         (emif_lpddr4b_mem_mem_dqs_t),               //   inout,    width = 4,                    .mem_dqs_t
		.mem_0_dqs_c         (emif_lpddr4b_mem_mem_dqs_c),               //   inout,    width = 4,                    .mem_dqs_c
		.mem_0_dmi           (emif_lpddr4b_mem_mem_dmi),                 //   inout,    width = 4,                    .mem_dmi
		.mem_0_ck_t          (emif_lpddr4b_mem_ck_mem_ck_t),             //  output,    width = 1,            mem_ck_0.mem_ck_t
		.mem_0_ck_c          (emif_lpddr4b_mem_ck_mem_ck_c),             //  output,    width = 1,                    .mem_ck_c
		.mem_0_reset_n       (emif_lpddr4b_mem_reset_n_mem_reset_n),     //  output,    width = 1,         mem_reset_n.mem_reset_n
		.oct_rzqin_0         (emif_lpddr4b_oct_oct_rzqin),               //   input,    width = 1,               oct_0.oct_rzqin
		.ref_clk             (emif_lpddr4b_ref_clk_clk)                  //   input,    width = 1,             ref_clk.clk
	);

	EMIF_Qsys_iopll_0 iopll (
		.refclk   (iopll_refclk_clk),           //   input,  width = 1,  refclk.clk
		.locked   (iopll_locked_export),        //  output,  width = 1,  locked.export
		.rst      (iopll_reset_reset),          //   input,  width = 1,   reset.reset
		.outclk_0 (iopll_outclk0_clk),          //  output,  width = 1, outclk0.clk
		.outclk_1 (iopll_outclk_axi4_lite_clk)  //  output,  width = 1, outclk1.clk
	);

	EMIF_Qsys_reset_in reset_in (
		.clk         (iopll_outclk0_clk),        //   input,  width = 1,       clk.clk
		.in_reset_n  (reset_reset_n),            //   input,  width = 1,  in_reset.reset_n
		.out_reset_n (reset_in_out_reset_reset)  //  output,  width = 1, out_reset.reset_n
	);

endmodule
