Info: Generated by version: 26.1 build 110
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/ip/pll.ip --synthesis=VERILOG --output-directory=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/ip/pll --family="Agilex 5" --part=A5EB013BB23BE4SCS
Info: pll.iopll_0: Able to implement PLL with user settings
Info: pll: "Transforming system: pll"
Info: pll: "Naming system components in system: pll"
Info: pll: "Processing generation queue"
Info: pll: "Generating: pll"
Info: pll: "Generating: pll_altera_iopll_2110_amd7dlq"
Info: pll: Done "pll" with 2 modules, 6 files
Info: Finished: Create HDL design files for synthesis
