// retroDE_ps2 — tb_ee_core_divu_mflo
//
// Chapter 43 opcode growth. First MIPS HI/LO-pair op: DIVU (unsigned
// divide) plus the two read-back moves MFHI and MFLO. Triggered by
// the ch42 real-BIOS trap on `divu $3, $4, $5` at pc=0xBFC4CC24
// (instr=0x0064001B). Signed DIV, MULT, MULTU, and MTHI/MTLO are
// left for the next chapter.
//
// Proves:
//   1. DIVU writes LO = quotient, HI = remainder.
//   2. MFLO / MFHI move the results out to rd.
//   3. rd=$0 is still honored (MFLO $0 does not corrupt other regs
//      and does not trap).
//   4. Divide-by-zero leaves HI/LO untouched (deterministic policy
//      chosen for this stub — Codex-sanctioned).
//   5. No STRICT_UNSUPPORTED trap for any of the three opcodes.
//
// Bootstrap layout (slot indices relative to BOOTSTRAP_SLOT):
//   +0   ori  $8,  $0, 0x0064    ; $8 = 100
//   +1   ori  $9,  $0, 0x0007    ; $9 = 7
//   +2   divu $8, $9             ; LO = 14, HI = 2
//   +3   mflo $10                ; $10 = 14
//   +4   mfhi $11                ; $11 = 2
//   +5   ori  $12, $0, 0x000E    ; expect_lo = 14
//   +6   bne  $10, $12, FAIL     ; quotient check
//   +7   nop                     ; delay slot
//   +8   ori  $13, $0, 0x0002    ; expect_hi = 2
//   +9   bne  $11, $13, FAIL     ; remainder check
//   +10  nop
//   +11  divu $8, $0             ; rt=0 → leave HI/LO unchanged
//   +12  mflo $14                ; must still be 14
//   +13  mfhi $15                ; must still be 2
//   +14  bne  $14, $12, FAIL     ; div-by-zero LO policy
//   +15  nop
//   +16  bne  $15, $13, FAIL     ; div-by-zero HI policy
//   +17  nop
//   +18  mflo $0                 ; rd=0 guard — must not trap; $0 stays 0
//   +19  bne  $0, $zero, FAIL    ; redundant self-check; $0 always 0
//   +20  nop
//   +21  syscall PASS
//   +22  syscall FAIL

`timescale 1ns/1ps

module tb_ee_core_divu_mflo;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    localparam int B_ORI_8   = BOOTSTRAP_SLOT + 0;
    localparam int B_ORI_9   = BOOTSTRAP_SLOT + 1;
    localparam int B_DIVU    = BOOTSTRAP_SLOT + 2;
    localparam int B_MFLO_10 = BOOTSTRAP_SLOT + 3;
    localparam int B_MFHI_11 = BOOTSTRAP_SLOT + 4;
    localparam int B_ORI_12  = BOOTSTRAP_SLOT + 5;
    localparam int B_BNE_LO  = BOOTSTRAP_SLOT + 6;
    localparam int B_DS_0    = BOOTSTRAP_SLOT + 7;
    localparam int B_ORI_13  = BOOTSTRAP_SLOT + 8;
    localparam int B_BNE_HI  = BOOTSTRAP_SLOT + 9;
    localparam int B_DS_1    = BOOTSTRAP_SLOT + 10;
    localparam int B_DIVU0   = BOOTSTRAP_SLOT + 11;
    localparam int B_MFLO_14 = BOOTSTRAP_SLOT + 12;
    localparam int B_MFHI_15 = BOOTSTRAP_SLOT + 13;
    localparam int B_BNE_LO0 = BOOTSTRAP_SLOT + 14;
    localparam int B_DS_2    = BOOTSTRAP_SLOT + 15;
    localparam int B_BNE_HI0 = BOOTSTRAP_SLOT + 16;
    localparam int B_DS_3    = BOOTSTRAP_SLOT + 17;
    localparam int B_MFLO_0  = BOOTSTRAP_SLOT + 18;
    localparam int B_BNE_Z   = BOOTSTRAP_SLOT + 19;
    localparam int B_DS_4    = BOOTSTRAP_SLOT + 20;
    localparam int B_PASS    = BOOTSTRAP_SLOT + 21;
    localparam int B_FAIL    = BOOTSTRAP_SLOT + 22;

    localparam logic [5:0] OP_SPECIAL = 6'h00;
    localparam logic [5:0] OP_J       = 6'h02;
    localparam logic [5:0] OP_BNE     = 6'h05;
    localparam logic [5:0] OP_ORI     = 6'h0D;
    localparam logic [5:0] FUNC_MFHI  = 6'h10;
    localparam logic [5:0] FUNC_MFLO  = 6'h12;
    localparam logic [5:0] FUNC_DIVU  = 6'h1B;

    logic clk;
    logic rst_n;

    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go;
    logic        core_halt;
    logic [31:0] core_pc;
    logic        core_trap;
    logic [31:0] core_trap_pc;
    logic [31:0] core_trap_instr;

    logic        ee_rd_en;
    logic [31:0] ee_rd_addr;
    logic [31:0] ee_rd_data;
    logic        ee_rd_valid;

    logic        ee_wr_en;
    logic [31:0] ee_wr_addr;
    logic [31:0] ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic        ee_cpu_irq;
    assign ee_cpu_irq = 1'b0;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(
        .STRICT_UNSUPPORTED(1'b1)
    ) u_core (
        .clk(clk), .rst_n(rst_n),
        .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(ee_cpu_irq),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    logic         bios_rd_en;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         bios_rd_valid;

    logic         ee_ram_rd_en;
    logic [24:0]  ee_ram_rd_addr;
    logic [127:0] ee_ram_rd_data;
    logic         ee_ram_rd_valid;
    logic         ee_ram_wr_en;
    logic [24:0]  ee_ram_wr_addr;
    logic [127:0] ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_divu_mflo_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events;
    int core_halt_events;
    int core_trap_events;
    int errors;

    initial begin
        core_retired_events = 0;
        core_halt_events    = 0;
        core_trap_events    = 0;
        errors              = 0;
    end

    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0)
                core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0)
                core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction

    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction

    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    // SPECIAL-encoded ops: {SPECIAL, rs[4:0], rt[4:0], rd[4:0], sa[4:0], func}
    function automatic logic [31:0] enc_r(input int rs, input int rt,
                                          input int rd, input int sa,
                                          input logic [5:0] func);
        return {OP_SPECIAL, rs[4:0], rt[4:0], rd[4:0], sa[4:0], func};
    endfunction

    task automatic bios_j(input int slot, input logic [31:0] tgt);
        bios_word(slot, enc_j(tgt));
    endtask
    task automatic bios_nop(input int slot);
        bios_word(slot, 32'd0);
    endtask
    task automatic bios_ori(input int slot, input int rt, input int rs,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_ORI, rs, rt, imm));
    endtask
    task automatic bios_bne(input int slot, input int rs, input int rt,
                            input int target_slot);
        bios_word(slot, enc_i(OP_BNE, rs, rt,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_syscall(input int slot);
        bios_word(slot, 32'h0000_000C);
    endtask
    task automatic bios_divu(input int slot, input int rs, input int rt);
        bios_word(slot, enc_r(rs, rt, 0, 0, FUNC_DIVU));
    endtask
    task automatic bios_mfhi(input int slot, input int rd);
        bios_word(slot, enc_r(0, 0, rd, 0, FUNC_MFHI));
    endtask
    task automatic bios_mflo(input int slot, input int rd);
        bios_word(slot, enc_r(0, 0, rd, 0, FUNC_MFLO));
    endtask

    initial begin
        rst_n   = 1'b0;
        core_go = 1'b0;

        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_j  (RESET_SLOT,     BOOTSTRAP_VA);
        bios_nop(RESET_SLOT + 1);

        // Operands and first DIVU.
        bios_ori (B_ORI_8, 8, 0, 16'h0064);    // $8 = 100
        bios_ori (B_ORI_9, 9, 0, 16'h0007);    // $9 = 7
        bios_divu(B_DIVU,   8, 9);             // LO=14, HI=2
        bios_mflo(B_MFLO_10, 10);              // $10 = 14
        bios_mfhi(B_MFHI_11, 11);              // $11 = 2

        bios_ori (B_ORI_12, 12, 0, 16'h000E);  // $12 = 14
        bios_bne (B_BNE_LO, 10, 12, B_FAIL);
        bios_nop (B_DS_0);
        bios_ori (B_ORI_13, 13, 0, 16'h0002);  // $13 = 2
        bios_bne (B_BNE_HI, 11, 13, B_FAIL);
        bios_nop (B_DS_1);

        // Divide-by-zero: HI/LO must stay unchanged.
        bios_divu(B_DIVU0, 8, 0);              // rt=$0=0
        bios_mflo(B_MFLO_14, 14);              // must still read 14
        bios_mfhi(B_MFHI_15, 15);              // must still read 2
        bios_bne (B_BNE_LO0, 14, 12, B_FAIL);  // $14 ?= $12
        bios_nop (B_DS_2);
        bios_bne (B_BNE_HI0, 15, 13, B_FAIL);  // $15 ?= $13
        bios_nop (B_DS_3);

        // $0 guard: MFLO $0 must not trap and must not corrupt $0.
        bios_mflo(B_MFLO_0, 0);                // rd=$0
        bios_bne (B_BNE_Z,  0, 0, B_FAIL);     // $0 != $0 never taken
        bios_nop (B_DS_4);

        bios_syscall(B_PASS);
        bios_syscall(B_FAIL);

        @(negedge clk);
        core_go = 1'b1;
        @(negedge clk);
        core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        if (core_halt_events != 1) begin
            $error("[tb_ee_core_divu_mflo] expected 1 halt, got %0d",
                   core_halt_events);
            errors = errors + 1;
        end
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_divu_mflo] unexpected strict trap: %0d",
                   core_trap_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_divu_mflo] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc,
                   BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        $display("[tb_ee_core_divu_mflo] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);

        if (errors == 0 &&
            core_halt_events == 1 &&
            core_trap_events == 0 &&
            core_pc == BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2))
            $display("[tb_ee_core_divu_mflo] PASS");
        else
            $display("[tb_ee_core_divu_mflo] FAIL");

        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_divu_mflo] timeout");
        $finish;
    end

endmodule : tb_ee_core_divu_mflo
