// retroDE_ps2 — tb_ee_core_jalr
//
// Thirteenth evidence-driven opcode growth: JALR (SPECIAL func 0x09,
// jump-and-link-register). Real-BIOS trapped on `jalr $31, $3` at
// 0xBFC5_29E8 after SH unlocked the previous stretch. JALR is the
// register-indirect mate to JAL:
//   - target: rs_val (same path as JR)
//   - link:   pc+8 written to rd_idx (not hardcoded $31 like JAL)
//   - rd==0 is a valid encoding that suppresses the link write
//     (same semantic as the existing regfile writeback guard)
//
// Two probes, both tight:
//
//   Probe A — canonical jalr $31, $rs (the shape the BIOS uses):
//     Build $10 = address of sub_a, then `jalr $31, $10`. Delay slot
//     is a NOP. sub_a writes a witness into $12 and returns via
//     `jr $31`. Back in main, a BNE checks $12 matches the expected
//     sentinel. If the link write missed $31 or wrote the wrong PC,
//     the JR lands in the wrong instruction and the sentinel check
//     either fails or the core wanders off.
//
//   Probe B — jalr with rd != $31, to prove rd is explicit:
//     Same shape, but uses $20 as the link register: `jalr $20, $11`.
//     sub_b returns via `jr $20`. This catches a bug where someone
//     copy-pasted JAL's hardcoded $31 into the JALR path — if link
//     always went to $31, the JR $20 return would use whatever
//     $20 held before (zero from reset), jumping to 0 and wandering.
//
// FAIL/PASS SYSCALL pattern; "final PC parks at PASS" is the load-
// bearing assertion. STRICT_UNSUPPORTED=1 so a missing JALR decode
// shows as a loud trap instead of silent NOP.

`timescale 1ns/1ps

module tb_ee_core_jalr;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR  = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA  = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    // Main (bootstrap) slot layout
    localparam int B_LUI_10    = BOOTSTRAP_SLOT + 0;
    localparam int B_ORI_10    = BOOTSTRAP_SLOT + 1;    // $10 = VA of sub_a
    localparam int B_JALR_A    = BOOTSTRAP_SLOT + 2;    // jalr $31, $10
    localparam int B_DS_A      = BOOTSTRAP_SLOT + 3;    // delay nop
    // ---- returns here ----
    localparam int B_ORI_EXP_A = BOOTSTRAP_SLOT + 4;    // $13 = 0x00A1
    localparam int B_BNE_A     = BOOTSTRAP_SLOT + 5;    // $12 != $13 → FAIL
    localparam int B_DS_BNE_A  = BOOTSTRAP_SLOT + 6;

    localparam int B_LUI_11    = BOOTSTRAP_SLOT + 7;
    localparam int B_ORI_11    = BOOTSTRAP_SLOT + 8;    // $11 = VA of sub_b
    localparam int B_JALR_B    = BOOTSTRAP_SLOT + 9;    // jalr $20, $11
    localparam int B_DS_B      = BOOTSTRAP_SLOT + 10;
    // ---- returns here ----
    localparam int B_ORI_EXP_B = BOOTSTRAP_SLOT + 11;   // $14 = 0x00B2
    localparam int B_BNE_B     = BOOTSTRAP_SLOT + 12;   // $15 != $14 → FAIL
    localparam int B_DS_BNE_B  = BOOTSTRAP_SLOT + 13;

    localparam int B_PASS      = BOOTSTRAP_SLOT + 14;   // SYSCALL PASS
    localparam int B_FAIL      = BOOTSTRAP_SLOT + 15;   // SYSCALL FAIL

    // Subroutine A: writes $12 = 0xA1, returns via $31
    localparam int B_SUBA_ORI  = BOOTSTRAP_SLOT + 16;
    localparam int B_SUBA_JR   = BOOTSTRAP_SLOT + 17;   // jr $31
    localparam int B_SUBA_DS   = BOOTSTRAP_SLOT + 18;

    // Subroutine B: writes $15 = 0xB2, returns via $20 (non-$31 link!)
    localparam int B_SUBB_ORI  = BOOTSTRAP_SLOT + 19;
    localparam int B_SUBB_JR   = BOOTSTRAP_SLOT + 20;   // jr $20
    localparam int B_SUBB_DS   = BOOTSTRAP_SLOT + 21;

    localparam logic [5:0] OP_SPECIAL = 6'h00;
    localparam logic [5:0] OP_J       = 6'h02;
    localparam logic [5:0] OP_BNE     = 6'h05;
    localparam logic [5:0] OP_ORI     = 6'h0D;
    localparam logic [5:0] OP_LUI     = 6'h0F;
    localparam logic [5:0] FUNC_JR    = 6'h08;
    localparam logic [5:0] FUNC_JALR  = 6'h09;

    // Encoded subroutine addresses
    localparam logic [31:0] SUB_A_VA =
        BOOTSTRAP_VA + ((B_SUBA_ORI - BOOTSTRAP_SLOT) << 2);
    localparam logic [31:0] SUB_B_VA =
        BOOTSTRAP_VA + ((B_SUBB_ORI - BOOTSTRAP_SLOT) << 2);

    logic clk;
    logic rst_n;

    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go;
    logic        core_halt;
    logic [31:0] core_pc;
    logic        core_trap;
    logic [31:0] core_trap_pc;
    logic [31:0] core_trap_instr;

    logic        ee_rd_en;
    logic [31:0] ee_rd_addr;
    logic [31:0] ee_rd_data;
    logic        ee_rd_valid;

    logic        ee_wr_en;
    logic [31:0] ee_wr_addr;
    logic [31:0] ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic        ee_cpu_irq;
    assign ee_cpu_irq = 1'b0;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(
        .STRICT_UNSUPPORTED(1'b1)
    ) u_core (
        .clk(clk), .rst_n(rst_n),
        .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(ee_cpu_irq),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    logic         bios_rd_en;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         bios_rd_valid;

    logic         ee_ram_rd_en;
    logic [24:0]  ee_ram_rd_addr;
    logic [127:0] ee_ram_rd_data;
    logic         ee_ram_rd_valid;
    logic         ee_ram_wr_en;
    logic [24:0]  ee_ram_wr_addr;
    logic [127:0] ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_jalr_core.trace"),
                      .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events;
    int core_halt_events;
    int core_trap_events;
    int errors;

    initial begin
        core_retired_events = 0;
        core_halt_events    = 0;
        core_trap_events    = 0;
        errors              = 0;
    end

    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0)
                core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0)
                core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction

    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction

    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    // JALR: SPECIAL | rs[4:0] | 0 | rd[4:0] | 0 | func=0x09
    function automatic logic [31:0] enc_jalr(input int rd, input int rs);
        return {OP_SPECIAL, rs[4:0], 5'd0, rd[4:0], 5'd0, FUNC_JALR};
    endfunction

    // JR: SPECIAL | rs[4:0] | 0 | 0 | 0 | func=0x08
    function automatic logic [31:0] enc_jr(input int rs);
        return {OP_SPECIAL, rs[4:0], 15'd0, FUNC_JR};
    endfunction

    task automatic bios_j(input int slot, input logic [31:0] tgt);
        bios_word(slot, enc_j(tgt));
    endtask
    task automatic bios_nop(input int slot);
        bios_word(slot, 32'd0);
    endtask
    task automatic bios_lui(input int slot, input int rt,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_LUI, 0, rt, imm));
    endtask
    task automatic bios_ori(input int slot, input int rt, input int rs,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_ORI, rs, rt, imm));
    endtask
    task automatic bios_bne(input int slot, input int rs, input int rt,
                            input int target_slot);
        bios_word(slot, enc_i(OP_BNE, rs, rt,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_jalr(input int slot, input int rd, input int rs);
        bios_word(slot, enc_jalr(rd, rs));
    endtask
    task automatic bios_jr(input int slot, input int rs);
        bios_word(slot, enc_jr(rs));
    endtask
    task automatic bios_syscall(input int slot);
        bios_word(slot, 32'h0000_000C);
    endtask

    initial begin
        rst_n   = 1'b0;
        core_go = 1'b0;

        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_j  (RESET_SLOT,     BOOTSTRAP_VA);
        bios_nop(RESET_SLOT + 1);

        // --- Main ---
        bios_lui(B_LUI_10, 10,    SUB_A_VA[31:16]);
        bios_ori(B_ORI_10, 10,10, SUB_A_VA[15:0]);          // $10 = SUB_A_VA
        bios_jalr(B_JALR_A, 31, 10);                         // jalr $31, $10
        bios_nop (B_DS_A);                                   // delay slot
        // Returns here. sub_a set $12 = 0xA1.
        bios_ori(B_ORI_EXP_A, 13, 0, 16'h00A1);             // $13 = expected
        bios_bne(B_BNE_A,     12, 13, B_FAIL);              // $12 must == $13
        bios_nop(B_DS_BNE_A);

        bios_lui(B_LUI_11, 11,    SUB_B_VA[31:16]);
        bios_ori(B_ORI_11, 11,11, SUB_B_VA[15:0]);          // $11 = SUB_B_VA
        bios_jalr(B_JALR_B, 20, 11);                         // jalr $20, $11
        bios_nop (B_DS_B);
        // Returns here. sub_b set $15 = 0xB2.
        bios_ori(B_ORI_EXP_B, 14, 0, 16'h00B2);             // $14 = expected
        bios_bne(B_BNE_B,     15, 14, B_FAIL);              // $15 must == $14
        bios_nop(B_DS_BNE_B);

        bios_syscall(B_PASS);
        bios_syscall(B_FAIL);

        // --- Subroutine A: returns via $31 ---
        bios_ori (B_SUBA_ORI, 12, 0, 16'h00A1);             // $12 = 0xA1
        bios_jr  (B_SUBA_JR, 31);
        bios_nop (B_SUBA_DS);

        // --- Subroutine B: returns via $20 (link written by JALR) ---
        bios_ori (B_SUBB_ORI, 15, 0, 16'h00B2);             // $15 = 0xB2
        bios_jr  (B_SUBB_JR, 20);
        bios_nop (B_SUBB_DS);

        @(negedge clk);
        core_go = 1'b1;
        @(negedge clk);
        core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        if (core_halt_events != 1) begin
            $error("[tb_ee_core_jalr] expected 1 halt, got %0d",
                   core_halt_events);
            errors = errors + 1;
        end
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_jalr] unexpected strict trap: %0d",
                   core_trap_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_jalr] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc,
                   BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        $display("[tb_ee_core_jalr] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);

        if (errors == 0 &&
            core_halt_events == 1 &&
            core_trap_events == 0 &&
            core_pc == BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2))
            $display("[tb_ee_core_jalr] PASS");
        else
            $display("[tb_ee_core_jalr] FAIL");

        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_jalr] timeout");
        $finish;
    end

endmodule : tb_ee_core_jalr
