// retroDE_ps2 — tb_ee_core_align
//
// Chapter 47 coverage: address-error enforcement on word/halfword
// load-store alignment. Real MIPS raises AdEL/AdES on SW/LW with
// ea[1:0]!=0 or SH/LH/LHU with ea[0]!=0. The ee_core_stub stub
// previously silently aliased to the nearest aligned slot; ch46's
// real-BIOS smoke showed the old behavior was masking upstream
// state errors. Ch47 gates the fault trap on TRAP_ALIGN_ERROR
// (defaults to 1). This TB pins the new behavior:
//
//   1. Aligned SW to kseg0 0x80000010 succeeds (no trap).
//   2. Aligned LW back reads the same word.
//   3. Misaligned SW with ea[1:0]=1 raises a trap.
//   4. The trap's pc / instr name the offending SW.
//
// Layout (slots relative to BOOTSTRAP_SLOT):
//   +0   lui  $1, 0x8000                ; $1 = 0x80000000 (kseg0 base)
//   +1   ori  $2, $0, 0xCAFE            ; lower half of witness
//   +2   lui  $3, 0xDEAD                ; upper half of witness
//   +3   ori  $3, $3, 0xBEEF            ; $3 = 0xDEADBEEF
//   +4   sw   $3, 0x10($1)              ; aligned SW (EA=0x80000010)
//   +5   lw   $4, 0x10($1)              ; aligned LW back
//   +6   bne  $3, $4, FAIL_ALIGNED      ; data must round-trip
//   +7   nop                            ; delay slot
//   +8   sw   $3, 0x11($1)              ; misaligned SW — TRAP expected
//   +9   nop                            ; delay slot (never retires)
//   +10  syscall PASS_IF_TRAP_MISSED    ; unreached on success
//   +11  syscall FAIL_ALIGNED           ; ch6 branch target

`timescale 1ns/1ps

module tb_ee_core_align;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    localparam int B_LUI_1     = BOOTSTRAP_SLOT + 0;
    localparam int B_ORI_2     = BOOTSTRAP_SLOT + 1;
    localparam int B_LUI_3     = BOOTSTRAP_SLOT + 2;
    localparam int B_ORI_3     = BOOTSTRAP_SLOT + 3;
    localparam int B_SW_OK     = BOOTSTRAP_SLOT + 4;
    localparam int B_LW_OK     = BOOTSTRAP_SLOT + 5;
    localparam int B_BNE       = BOOTSTRAP_SLOT + 6;
    localparam int B_DS_BNE    = BOOTSTRAP_SLOT + 7;
    localparam int B_SW_BAD    = BOOTSTRAP_SLOT + 8;
    localparam int B_DS_BAD    = BOOTSTRAP_SLOT + 9;
    localparam int B_NEVER     = BOOTSTRAP_SLOT + 10;
    localparam int B_FAIL      = BOOTSTRAP_SLOT + 11;

    localparam logic [5:0] OP_J     = 6'h02;
    localparam logic [5:0] OP_BNE   = 6'h05;
    localparam logic [5:0] OP_ORI   = 6'h0D;
    localparam logic [5:0] OP_LUI   = 6'h0F;
    localparam logic [5:0] OP_LW    = 6'h23;
    localparam logic [5:0] OP_SW    = 6'h2B;

    logic clk;
    logic rst_n;

    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go;
    logic        core_halt;
    logic [31:0] core_pc;
    logic        core_trap;
    logic [31:0] core_trap_pc;
    logic [31:0] core_trap_instr;

    logic        ee_rd_en;
    logic [31:0] ee_rd_addr;
    logic [31:0] ee_rd_data;
    logic        ee_rd_valid;

    logic        ee_wr_en;
    logic [31:0] ee_wr_addr;
    logic [31:0] ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic        ee_cpu_irq;
    assign ee_cpu_irq = 1'b0;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(
        .STRICT_UNSUPPORTED(1'b1),
        .TRAP_ALIGN_ERROR  (1'b1)
    ) u_core (
        .clk(clk), .rst_n(rst_n),
        .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(ee_cpu_irq),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    logic         bios_rd_en;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         bios_rd_valid;

    logic         ee_ram_rd_en;
    logic [24:0]  ee_ram_rd_addr;
    logic [127:0] ee_ram_rd_data;
    logic         ee_ram_rd_valid;
    logic         ee_ram_wr_en;
    logic [24:0]  ee_ram_wr_addr;
    logic [127:0] ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_align_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events;
    int core_halt_events;
    int core_trap_events;
    int errors;

    initial begin
        core_retired_events = 0;
        core_halt_events    = 0;
        core_trap_events    = 0;
        errors              = 0;
    end

    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0)
                core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0)
                core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction

    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction

    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    task automatic bios_j(input int slot, input logic [31:0] tgt);
        bios_word(slot, enc_j(tgt));
    endtask
    task automatic bios_nop(input int slot);
        bios_word(slot, 32'd0);
    endtask
    task automatic bios_lui(input int slot, input int rt,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_LUI, 0, rt, imm));
    endtask
    task automatic bios_ori(input int slot, input int rt, input int rs,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_ORI, rs, rt, imm));
    endtask
    task automatic bios_lw(input int slot, input int rt, input int rs,
                           input logic [15:0] offs);
        bios_word(slot, enc_i(OP_LW, rs, rt, offs));
    endtask
    task automatic bios_sw(input int slot, input int rt, input int rs,
                           input logic [15:0] offs);
        bios_word(slot, enc_i(OP_SW, rs, rt, offs));
    endtask
    task automatic bios_bne(input int slot, input int rs, input int rt,
                            input int target_slot);
        bios_word(slot, enc_i(OP_BNE, rs, rt,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_syscall(input int slot);
        bios_word(slot, 32'h0000_000C);
    endtask

    initial begin
        rst_n   = 1'b0;
        core_go = 1'b0;

        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_j  (RESET_SLOT,     BOOTSTRAP_VA);
        bios_nop(RESET_SLOT + 1);

        bios_lui(B_LUI_1, 1, 16'h8000);
        bios_ori(B_ORI_2, 2, 0, 16'hCAFE);
        bios_lui(B_LUI_3, 3, 16'hDEAD);
        bios_ori(B_ORI_3, 3, 3, 16'hBEEF);
        bios_sw (B_SW_OK, 3, 1, 16'h0010);    // aligned EA=0x80000010
        bios_lw (B_LW_OK, 4, 1, 16'h0010);    // aligned LW back
        bios_bne(B_BNE,   3, 4, B_FAIL);
        bios_nop(B_DS_BNE);
        bios_sw (B_SW_BAD, 3, 1, 16'h0011);   // misaligned EA=0x80000011 — TRAP expected
        bios_nop(B_DS_BAD);
        bios_syscall(B_NEVER);
        bios_syscall(B_FAIL);

        @(negedge clk);
        core_go = 1'b1;
        @(negedge clk);
        core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        if (!core_trap) begin
            $error("[tb_ee_core_align] expected trap on misaligned SW, got halt without trap");
            errors = errors + 1;
        end
        if (core_trap_events != 1) begin
            $error("[tb_ee_core_align] expected exactly 1 trap retire, got %0d",
                   core_trap_events);
            errors = errors + 1;
        end
        if (core_trap_pc !== BOOTSTRAP_VA + ((B_SW_BAD - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_align] trap_pc mismatch: got 0x%08h expected 0x%08h",
                   core_trap_pc,
                   BOOTSTRAP_VA + ((B_SW_BAD - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end
        if (core_trap_instr[31:26] !== OP_SW) begin
            $error("[tb_ee_core_align] trap_instr is not SW: 0x%08h",
                   core_trap_instr);
            errors = errors + 1;
        end
        // Core must not have progressed past the misaligned SW (the
        // never / fail syscalls should not have executed).
        if (core_halt_events != 0) begin
            $error("[tb_ee_core_align] unexpected SYSCALL halt(s): %0d",
                   core_halt_events);
            errors = errors + 1;
        end

        $display("[tb_ee_core_align] retired=%0d halt=%0d trap=%0d trap_pc=0x%08h trap_instr=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_trap_pc, core_trap_instr,
                 errors);

        if (errors == 0 &&
            core_trap == 1'b1 &&
            core_trap_events == 1 &&
            core_halt_events == 0 &&
            core_trap_pc == BOOTSTRAP_VA + ((B_SW_BAD - BOOTSTRAP_SLOT) << 2) &&
            core_trap_instr[31:26] == OP_SW)
            $display("[tb_ee_core_align] PASS");
        else
            $display("[tb_ee_core_align] FAIL");

        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_align] timeout");
        $finish;
    end

endmodule : tb_ee_core_align
