// retroDE_ps2 — tb_ee_core_slt
//
// Ninth evidence-driven opcode growth. Real-BIOS trapped on SLTU
// (SPECIAL func 0x2B) at 0xBFC0_2644, the instruction right after
// ADDU. Batched with SLT (func 0x2A) — identical plumbing, just
// signed-vs-unsigned compare, same pattern as SLTI/SLTIU but
// register-register instead of register-immediate.
//
// Probes (with $2 = 5, $3 = -1 via ADDIU -1, $4 = 10):
//   slt  $5, $2, $4    → 1   (5 < 10 signed)
//   slt  $6, $3, $4    → 1   (-1 < 10 signed; -1 is less)
//   slt  $7, $4, $4    → 0   (10 < 10 signed; equal, not less)
//   sltu $8, $3, $4    → 0   (0xFFFFFFFF < 10 unsigned; NOT less)
//   sltu $9, $2, $4    → 1   (5 < 10 unsigned)
//
// The critical probe is sltu $3/$4 — it catches any code path that
// zero-extends instead of using the full 32-bit register as
// unsigned. Same quirk as SLTIU.

`timescale 1ns/1ps

module tb_ee_core_slt;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR  = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA  = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    localparam int B_ORI_2    = BOOTSTRAP_SLOT + 0;    // $2 = 5
    localparam int B_ADDIU_3  = BOOTSTRAP_SLOT + 1;    // $3 = -1
    localparam int B_ORI_4    = BOOTSTRAP_SLOT + 2;    // $4 = 10
    localparam int B_SLT_1    = BOOTSTRAP_SLOT + 3;    // $5 = slt  $2,$4
    localparam int B_SLT_2    = BOOTSTRAP_SLOT + 4;    // $6 = slt  $3,$4
    localparam int B_SLT_3    = BOOTSTRAP_SLOT + 5;    // $7 = slt  $4,$4
    localparam int B_SLTU_1   = BOOTSTRAP_SLOT + 6;    // $8 = sltu $3,$4
    localparam int B_SLTU_2   = BOOTSTRAP_SLOT + 7;    // $9 = sltu $2,$4
    localparam int B_ORI_10   = BOOTSTRAP_SLOT + 8;    // $10 = 1
    localparam int B_BNE_1    = BOOTSTRAP_SLOT + 9;    // $5 != 1 → FAIL
    localparam int B_DS_1     = BOOTSTRAP_SLOT + 10;
    localparam int B_BNE_2    = BOOTSTRAP_SLOT + 11;   // $6 != 1 → FAIL
    localparam int B_DS_2     = BOOTSTRAP_SLOT + 12;
    localparam int B_BNE_3    = BOOTSTRAP_SLOT + 13;   // $7 != 0 → FAIL
    localparam int B_DS_3     = BOOTSTRAP_SLOT + 14;
    localparam int B_BNE_4    = BOOTSTRAP_SLOT + 15;   // $8 != 0 → FAIL
    localparam int B_DS_4     = BOOTSTRAP_SLOT + 16;
    localparam int B_BNE_5    = BOOTSTRAP_SLOT + 17;   // $9 != 1 → FAIL
    localparam int B_DS_5     = BOOTSTRAP_SLOT + 18;
    localparam int B_PASS     = BOOTSTRAP_SLOT + 19;
    localparam int B_FAIL     = BOOTSTRAP_SLOT + 20;

    localparam logic [5:0] OP_SPECIAL = 6'h00;
    localparam logic [5:0] OP_J       = 6'h02;
    localparam logic [5:0] OP_BNE     = 6'h05;
    localparam logic [5:0] OP_ADDIU   = 6'h09;
    localparam logic [5:0] OP_ORI     = 6'h0D;
    localparam logic [5:0] FUNC_SLT   = 6'h2A;
    localparam logic [5:0] FUNC_SLTU  = 6'h2B;

    logic clk;
    logic rst_n;

    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go;
    logic        core_halt;
    logic [31:0] core_pc;
    logic        core_trap;
    logic [31:0] core_trap_pc;
    logic [31:0] core_trap_instr;

    logic        ee_rd_en;
    logic [31:0] ee_rd_addr;
    logic [31:0] ee_rd_data;
    logic        ee_rd_valid;

    logic        ee_wr_en;
    logic [31:0] ee_wr_addr;
    logic [31:0] ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic        ee_cpu_irq;
    assign ee_cpu_irq = 1'b0;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(
        .STRICT_UNSUPPORTED(1'b1)
    ) u_core (
        .clk(clk), .rst_n(rst_n),
        .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(ee_cpu_irq),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    logic         bios_rd_en;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         bios_rd_valid;

    logic         ee_ram_rd_en;
    logic [24:0]  ee_ram_rd_addr;
    logic [127:0] ee_ram_rd_data;
    logic         ee_ram_rd_valid;
    logic         ee_ram_wr_en;
    logic [24:0]  ee_ram_wr_addr;
    logic [127:0] ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_slt_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events;
    int core_halt_events;
    int core_trap_events;
    int errors;

    initial begin
        core_retired_events = 0;
        core_halt_events    = 0;
        core_trap_events    = 0;
        errors              = 0;
    end

    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0)
                core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0)
                core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction

    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction

    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    function automatic logic [31:0] enc_rtype(input logic [5:0] fn,
                                              input int rd, input int rs,
                                              input int rt);
        return {OP_SPECIAL, rs[4:0], rt[4:0], rd[4:0], 5'd0, fn};
    endfunction

    task automatic bios_j(input int slot, input logic [31:0] tgt);
        bios_word(slot, enc_j(tgt));
    endtask
    task automatic bios_nop(input int slot);
        bios_word(slot, 32'd0);
    endtask
    task automatic bios_ori(input int slot, input int rt, input int rs,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_ORI, rs, rt, imm));
    endtask
    task automatic bios_addiu(input int slot, input int rt, input int rs,
                              input logic [15:0] imm);
        bios_word(slot, enc_i(OP_ADDIU, rs, rt, imm));
    endtask
    task automatic bios_bne(input int slot, input int rs, input int rt,
                            input int target_slot);
        bios_word(slot, enc_i(OP_BNE, rs, rt,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_slt (input int slot, input int rd,
                             input int rs, input int rt);
        bios_word(slot, enc_rtype(FUNC_SLT, rd, rs, rt));
    endtask
    task automatic bios_sltu(input int slot, input int rd,
                             input int rs, input int rt);
        bios_word(slot, enc_rtype(FUNC_SLTU, rd, rs, rt));
    endtask
    task automatic bios_syscall(input int slot);
        bios_word(slot, 32'h0000_000C);
    endtask

    initial begin
        rst_n   = 1'b0;
        core_go = 1'b0;

        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_j  (RESET_SLOT,     BOOTSTRAP_VA);
        bios_nop(RESET_SLOT + 1);

        bios_ori  (B_ORI_2,   2, 0, 16'd5);                // $2 = 5
        bios_addiu(B_ADDIU_3, 3, 0, 16'hFFFF);             // $3 = -1
        bios_ori  (B_ORI_4,   4, 0, 16'd10);               // $4 = 10

        bios_slt (B_SLT_1,  5, 2, 4);                      // $5 = slt  $2,$4  → 1
        bios_slt (B_SLT_2,  6, 3, 4);                      // $6 = slt  $3,$4  → 1
        bios_slt (B_SLT_3,  7, 4, 4);                      // $7 = slt  $4,$4  → 0
        bios_sltu(B_SLTU_1, 8, 3, 4);                      // $8 = sltu $3,$4  → 0
        bios_sltu(B_SLTU_2, 9, 2, 4);                      // $9 = sltu $2,$4  → 1

        bios_ori  (B_ORI_10, 10, 0, 16'd1);                // $10 = 1

        bios_bne(B_BNE_1, 5, 10, B_FAIL);                  // $5 must be 1
        bios_nop(B_DS_1);
        bios_bne(B_BNE_2, 6, 10, B_FAIL);                  // $6 must be 1
        bios_nop(B_DS_2);
        bios_bne(B_BNE_3, 7,  0, B_FAIL);                  // $7 must be 0
        bios_nop(B_DS_3);
        bios_bne(B_BNE_4, 8,  0, B_FAIL);                  // $8 must be 0
        bios_nop(B_DS_4);
        bios_bne(B_BNE_5, 9, 10, B_FAIL);                  // $9 must be 1
        bios_nop(B_DS_5);

        bios_syscall(B_PASS);
        bios_syscall(B_FAIL);

        @(negedge clk);
        core_go = 1'b1;
        @(negedge clk);
        core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        if (core_halt_events != 1) begin
            $error("[tb_ee_core_slt] expected 1 halt, got %0d",
                   core_halt_events);
            errors = errors + 1;
        end
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_slt] unexpected strict trap: %0d",
                   core_trap_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_slt] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc,
                   BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        $display("[tb_ee_core_slt] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);

        if (errors == 0 &&
            core_halt_events == 1 &&
            core_trap_events == 0 &&
            core_pc == BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2))
            $display("[tb_ee_core_slt] PASS");
        else
            $display("[tb_ee_core_slt] FAIL");

        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_slt] timeout");
        $finish;
    end

endmodule : tb_ee_core_slt
