// retroDE_ps2 — tb_ee_core_sd
//
// Ch275 — Focused TB for MIPS-III SD (Store Doubleword), opcode 0x3F.
// qbert.elf hits `sd $ra, 0x20($sp)` (instr 0xFFBF0020) at PC
// 0x00112DAC, a function prologue.
//
// SD writes 64 bits (8 bytes). The model has 32-bit GPRs so we
// emit a 2-beat 32-bit-stripe write through the existing map_wr
// port: beat 0 = rt_val[31:0], beat 1 = 0 (upper 32 bits of $rt
// not modelled — matches Ch271's SQ approximation).
//
// Test sequence:
//   1. Set $v0 (base) = 0x80000400 (kseg0 → EE-RAM phys 0x400).
//   2. Pre-poke phys 0x400/0x404 with junk (0xDEADBEEF/0xCAFEF00D).
//   3. Set $ra to a known sentinel (0xABCD1234).
//   4. Execute `sd $ra, 0($v0)` (encoded with rt=31, op=0x3F).
//   5. LW + BNE chain verifies mem[0x400]=0xABCD1234, mem[0x404]=0.
//   6. Direct hierarchical RAM peek confirms the 8-byte stored block.
//   7. PASS via syscall.
//
// Strict mode ON. Pre-Ch275 this would trap on op=0x3F.

`timescale 1ns/1ps

module tb_ee_core_sd;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 64 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    localparam logic [31:0] TARGET_KSEG0   = 32'h8000_0400;
    localparam int          TARGET_PHYS    = 32'h400;
    localparam logic [31:0] RA_SENTINEL    = 32'hABCD_1234;

    // Slot layout
    localparam int B_LUI_BASE = BOOTSTRAP_SLOT + 0;   // lui $v0, 0x8000
    localparam int B_ORI_BASE = BOOTSTRAP_SLOT + 1;   // ori $v0, $v0, 0x0400
    localparam int B_LUI_RA_H = BOOTSTRAP_SLOT + 2;   // lui $ra, 0xABCD
    localparam int B_ORI_RA_L = BOOTSTRAP_SLOT + 3;   // ori $ra, $ra, 0x1234
    localparam int B_SD       = BOOTSTRAP_SLOT + 4;   // sd  $ra, 0($v0)
    localparam int B_LW_LO    = BOOTSTRAP_SLOT + 5;   // lw $t0, 0($v0)
    localparam int B_LUI_T1   = BOOTSTRAP_SLOT + 6;   // lui $t1, 0xABCD
    localparam int B_ORI_T1   = BOOTSTRAP_SLOT + 7;   // ori $t1, $t1, 0x1234
    localparam int B_BNE_LO   = BOOTSTRAP_SLOT + 8;   // bne $t0, $t1, FAIL
    localparam int B_DS_LO    = BOOTSTRAP_SLOT + 9;
    localparam int B_LW_HI    = BOOTSTRAP_SLOT + 10;  // lw $t0, 4($v0)
    localparam int B_BNE_HI   = BOOTSTRAP_SLOT + 11;  // bne $t0, $0, FAIL
    localparam int B_DS_HI    = BOOTSTRAP_SLOT + 12;
    localparam int B_PASS     = BOOTSTRAP_SLOT + 13;
    localparam int B_FAIL     = BOOTSTRAP_SLOT + 14;

    localparam logic [5:0] OP_J     = 6'h02;
    localparam logic [5:0] OP_BNE   = 6'h05;
    localparam logic [5:0] OP_ORI   = 6'h0D;
    localparam logic [5:0] OP_LUI   = 6'h0F;
    localparam logic [5:0] OP_LW    = 6'h23;
    localparam logic [5:0] OP_SD    = 6'h3F;

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    // ----- EE core -----
    logic        core_go, core_halt, core_trap;
    logic [31:0] core_pc, core_trap_pc, core_trap_instr;
    logic        ee_rd_en, ee_rd_valid, ee_wr_en;
    logic [31:0] ee_rd_addr, ee_rd_data, ee_wr_addr, ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(.STRICT_UNSUPPORTED(1'b1)) u_core (
        .clk(clk), .rst_n(rst_n), .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(1'b0),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    // ----- Map + RAM + BIOS -----
    logic         bios_rd_en, bios_rd_valid;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         ee_ram_rd_en, ee_ram_rd_valid, ee_ram_wr_en;
    logic [24:0]  ee_ram_rd_addr, ee_ram_wr_addr;
    logic [127:0] ee_ram_rd_data, ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_sd_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events, core_halt_events, core_trap_events, errors;
    initial begin
        core_retired_events = 0; core_halt_events = 0;
        core_trap_events = 0; errors = 0;
    end
    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0) core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0) core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction
    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction
    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    // EE-RAM 32-bit word poke via qword backing.
    task automatic ram_word(input logic [31:0] phys_addr, input logic [31:0] word);
        int           qw_idx;
        logic [1:0]   lane;
        logic [127:0] cur;
        qw_idx = phys_addr >> 4;
        lane   = phys_addr[3:2];
        cur    = u_ee_ram.mem[qw_idx];
        case (lane)
            2'd0: cur[ 31:  0] = word;
            2'd1: cur[ 63: 32] = word;
            2'd2: cur[ 95: 64] = word;
            2'd3: cur[127: 96] = word;
        endcase
        u_ee_ram.mem[qw_idx] = cur;
    endtask

    initial begin
        logic [31:0] qbert_sd_raw;

        rst_n = 1'b0; core_go = 1'b0;
        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_word(RESET_SLOT,     enc_j(BOOTSTRAP_VA));
        bios_word(RESET_SLOT + 1, 32'd0);

        // Base = 0x80000400
        bios_word(B_LUI_BASE, enc_i(OP_LUI, 0, 2, 16'h8000));      // lui  $v0, 0x8000
        bios_word(B_ORI_BASE, enc_i(OP_ORI, 2, 2, 16'h0400));      // ori  $v0, $v0, 0x0400

        // $ra = 0xABCD1234 sentinel
        bios_word(B_LUI_RA_H, enc_i(OP_LUI, 0, 31, 16'hABCD));     // lui  $ra, 0xABCD
        bios_word(B_ORI_RA_L, enc_i(OP_ORI, 31, 31, 16'h1234));    // ori  $ra, $ra, 0x1234

        // Encode SD $ra, 0($v0). Sanity-check the encoding matches the
        // qbert variant's shape (op=0x3F, rs=base, rt=source, imm=0).
        qbert_sd_raw = enc_i(OP_SD, /*rs=*/2, /*rt=*/31, 16'h0000);
        bios_word(B_SD, qbert_sd_raw);

        // Verify low word stored $ra.
        bios_word(B_LW_LO,   enc_i(OP_LW,  2, 8, 16'h0000));        // lw $t0, 0($v0)
        bios_word(B_LUI_T1,  enc_i(OP_LUI, 0, 9, 16'hABCD));        // lui $t1, 0xABCD
        bios_word(B_ORI_T1,  enc_i(OP_ORI, 9, 9, 16'h1234));        // ori $t1, $t1, 0x1234
        bios_word(B_BNE_LO,  enc_i(OP_BNE, 8, 9, branch_imm(B_BNE_LO, B_FAIL)));
        bios_word(B_DS_LO,   32'd0);

        // Verify high word stored 0.
        bios_word(B_LW_HI,   enc_i(OP_LW, 2, 8, 16'h0004));         // lw $t0, 4($v0)
        bios_word(B_BNE_HI,  enc_i(OP_BNE, 8, 0, branch_imm(B_BNE_HI, B_FAIL)));
        bios_word(B_DS_HI,   32'd0);

        bios_word(B_PASS, 32'h0000_000C);
        bios_word(B_FAIL, 32'h0000_000C);

        // Pre-poke distinct junk so a missing SD beat leaves residue.
        ram_word(TARGET_PHYS + 32'd0, 32'hDEAD_BEEF);
        ram_word(TARGET_PHYS + 32'd4, 32'hCAFE_F00D);

        @(negedge clk); core_go = 1'b1;
        @(negedge clk); core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        // ---- Checks ----
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_sd] unexpected trap (SD unsupported?): %0d pc=0x%08h instr=0x%08h",
                   core_trap_events, core_trap_pc, core_trap_instr);
            errors = errors + 1;
        end
        if (core_halt_events != 1) begin
            $error("[tb_ee_core_sd] expected 1 halt, got %0d", core_halt_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_sd] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc, BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        // Belt-and-braces: direct hierarchical peek of the qword that
        // SD wrote. Low 32 bits should be RA_SENTINEL; bytes 4..7
        // should be zero; bytes 8..15 untouched (= original junk).
        begin
            int           qw_idx;
            logic [127:0] cur;
            logic [31:0]  lo_w, hi_w;
            qw_idx = TARGET_PHYS >> 4;
            cur    = u_ee_ram.mem[qw_idx];
            lo_w   = cur[31:0];
            hi_w   = cur[63:32];
            if (lo_w !== RA_SENTINEL) begin
                $error("[tb_ee_core_sd] direct RAM low_w = 0x%08h (expected 0x%08h)",
                       lo_w, RA_SENTINEL);
                errors = errors + 1;
            end
            if (hi_w !== 32'd0) begin
                $error("[tb_ee_core_sd] direct RAM high_w = 0x%08h (expected 0)", hi_w);
                errors = errors + 1;
            end
            // Bytes 8..15 should be unchanged junk (we didn't store there).
            // For a 2-MiB image they'd be 0; for our pre-pokes, only
            // bytes 0..7 were set. So bytes 8..15 = 0 from RAM zero-init.
        end

        $display("[tb_ee_core_sd] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);

        if (errors == 0)
            $display("[tb_ee_core_sd] PASS");
        else
            $display("[tb_ee_core_sd] FAIL");
        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_sd] timeout");
        $finish;
    end

endmodule : tb_ee_core_sd
