// retroDE_ps2 — tb_ee_core_branch_zero
//
// Chapter 41 opcode growth: sign-compare-with-zero branch family.
// Real-BIOS (post-ch40 stub) trapped on BLEZ (opcode 0x06) at
// pc=0xBFC4E470 instr=0x18C00007. Added as a batch: BLEZ, BGTZ,
// BLTZ (REGIMM rt=0x00), BGEZ (REGIMM rt=0x01). The four share the
// same branch-target math as BEQ/BNE — only the take condition
// differs. Implemented in rtl/ee/ee_core_stub.sv as extensions to
// is_branch / branch_taken / is_nop_class.
//
// The TB exercises all four with a small positive and a small
// negative witness value in $8 and $9 (0x0000_0001 and
// 0xFFFF_FFFF = -1). Each branch must take in the "correct
// direction" exactly once and fall through in the other. If any
// branch mis-takes or mis-falls-through, the sentinel flow runs
// the FAIL syscall. Otherwise the test halts on the PASS syscall
// at the end of the chain.
//
// Layout (slot indices relative to BOOTSTRAP_SLOT, each slot = 4 bytes):
//   +0   ori  $8, $0, 0x0001     ; $8 = +1
//   +1   lui  $9, 0xFFFF         ; upper half = 0xFFFF
//   +2   ori  $9, $9, 0xFFFF     ; $9 = 0xFFFFFFFF = -1 signed
//   +3   blez $8, FAIL_BLEZ_TAKEN  (+1 is > 0, must NOT take)
//   +4   nop                      (delay slot)
//   +5   blez $9, BLEZ_OK         (-1 is <= 0, MUST take)
//   +6   nop                      (delay slot)
//   +7   syscall FAIL             (unreached)
//   +8   <BLEZ_OK> bgtz $9, FAIL_BGTZ_TAKEN  (-1 NOT > 0)
//   +9   nop
//   +10  bgtz $8, BGTZ_OK          (+1 > 0, take)
//   +11  nop
//   +12  syscall FAIL
//   +13  <BGTZ_OK> bltz $8, FAIL_BLTZ_TAKEN  (+1 NOT < 0)
//   +14  nop
//   +15  bltz $9, BLTZ_OK          (-1 < 0, take)
//   +16  nop
//   +17  syscall FAIL
//   +18  <BLTZ_OK> bgez $9, FAIL_BGEZ_TAKEN  (-1 NOT >= 0)
//   +19  nop
//   +20  bgez $8, PASS             (+1 >= 0, take — lands on PASS)
//   +21  nop
//   +22  syscall FAIL
//   +23  <PASS> syscall            (halt target)
//   +24  <FAIL_*> syscall

`timescale 1ns/1ps

module tb_ee_core_branch_zero;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    localparam int B_ORI_8    = BOOTSTRAP_SLOT + 0;
    localparam int B_LUI_9    = BOOTSTRAP_SLOT + 1;
    localparam int B_ORI_9    = BOOTSTRAP_SLOT + 2;
    localparam int B_BLEZ_P   = BOOTSTRAP_SLOT + 3;    // blez $8 (positive) — must NOT take
    localparam int B_DS_0     = BOOTSTRAP_SLOT + 4;
    localparam int B_BLEZ_N   = BOOTSTRAP_SLOT + 5;    // blez $9 (negative) — MUST take → BLEZ_OK
    localparam int B_DS_1     = BOOTSTRAP_SLOT + 6;
    localparam int B_FAIL_A   = BOOTSTRAP_SLOT + 7;    // unreached
    localparam int B_BLEZ_OK  = BOOTSTRAP_SLOT + 8;
    localparam int B_BGTZ_N   = BOOTSTRAP_SLOT + 8;    // bgtz $9 (negative) — must NOT take
    localparam int B_DS_2     = BOOTSTRAP_SLOT + 9;
    localparam int B_BGTZ_P   = BOOTSTRAP_SLOT + 10;   // bgtz $8 (positive) — MUST take → BGTZ_OK
    localparam int B_DS_3     = BOOTSTRAP_SLOT + 11;
    localparam int B_FAIL_B   = BOOTSTRAP_SLOT + 12;
    localparam int B_BGTZ_OK  = BOOTSTRAP_SLOT + 13;
    localparam int B_BLTZ_P   = BOOTSTRAP_SLOT + 13;   // bltz $8 (positive) — must NOT take
    localparam int B_DS_4     = BOOTSTRAP_SLOT + 14;
    localparam int B_BLTZ_N   = BOOTSTRAP_SLOT + 15;   // bltz $9 (negative) — MUST take → BLTZ_OK
    localparam int B_DS_5     = BOOTSTRAP_SLOT + 16;
    localparam int B_FAIL_C   = BOOTSTRAP_SLOT + 17;
    localparam int B_BLTZ_OK  = BOOTSTRAP_SLOT + 18;
    localparam int B_BGEZ_N   = BOOTSTRAP_SLOT + 18;   // bgez $9 (negative) — must NOT take
    localparam int B_DS_6     = BOOTSTRAP_SLOT + 19;
    localparam int B_BGEZ_P   = BOOTSTRAP_SLOT + 20;   // bgez $8 (positive) — MUST take → PASS
    localparam int B_DS_7     = BOOTSTRAP_SLOT + 21;
    localparam int B_FAIL_D   = BOOTSTRAP_SLOT + 22;
    localparam int B_PASS     = BOOTSTRAP_SLOT + 23;

    localparam logic [5:0] OP_SPECIAL = 6'h00;
    localparam logic [5:0] OP_REGIMM  = 6'h01;
    localparam logic [5:0] OP_J       = 6'h02;
    localparam logic [5:0] OP_BLEZ    = 6'h06;
    localparam logic [5:0] OP_BGTZ    = 6'h07;
    localparam logic [5:0] OP_LUI     = 6'h0F;
    localparam logic [5:0] OP_ORI     = 6'h0D;
    localparam logic [4:0] REGIMM_BLTZ = 5'h00;
    localparam logic [4:0] REGIMM_BGEZ = 5'h01;

    logic clk;
    logic rst_n;

    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go;
    logic        core_halt;
    logic [31:0] core_pc;
    logic        core_trap;
    logic [31:0] core_trap_pc;
    logic [31:0] core_trap_instr;

    logic        ee_rd_en;
    logic [31:0] ee_rd_addr;
    logic [31:0] ee_rd_data;
    logic        ee_rd_valid;

    logic        ee_wr_en;
    logic [31:0] ee_wr_addr;
    logic [31:0] ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic        ee_cpu_irq;
    assign ee_cpu_irq = 1'b0;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(
        .STRICT_UNSUPPORTED(1'b1)
    ) u_core (
        .clk(clk), .rst_n(rst_n),
        .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(ee_cpu_irq),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    logic         bios_rd_en;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         bios_rd_valid;

    logic         ee_ram_rd_en;
    logic [24:0]  ee_ram_rd_addr;
    logic [127:0] ee_ram_rd_data;
    logic         ee_ram_rd_valid;
    logic         ee_ram_wr_en;
    logic [24:0]  ee_ram_wr_addr;
    logic [127:0] ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_branch_zero_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events;
    int core_halt_events;
    int core_trap_events;
    int errors;

    initial begin
        core_retired_events = 0;
        core_halt_events    = 0;
        core_trap_events    = 0;
        errors              = 0;
    end

    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0)
                core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0)
                core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction

    function automatic logic [31:0] enc_j(input logic [5:0] op,
                                          input logic [31:0] target_addr);
        return {op, target_addr[27:2]};
    endfunction

    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    task automatic bios_j(input int slot, input logic [31:0] tgt);
        bios_word(slot, enc_j(OP_J, tgt));
    endtask
    task automatic bios_nop(input int slot);
        bios_word(slot, 32'd0);
    endtask
    task automatic bios_lui(input int slot, input int rt,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_LUI, 0, rt, imm));
    endtask
    task automatic bios_ori(input int slot, input int rt, input int rs,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_ORI, rs, rt, imm));
    endtask
    task automatic bios_syscall(input int slot);
        bios_word(slot, 32'h0000_000C);
    endtask

    // BLEZ/BGTZ use rt=0 (reserved). BLTZ/BGEZ encode the sub-op in
    // the rt field (0x00/0x01). All use branch_imm for the offset.
    task automatic bios_blez(input int slot, input int rs,
                             input int target_slot);
        bios_word(slot, enc_i(OP_BLEZ, rs, 0,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_bgtz(input int slot, input int rs,
                             input int target_slot);
        bios_word(slot, enc_i(OP_BGTZ, rs, 0,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_bltz(input int slot, input int rs,
                             input int target_slot);
        bios_word(slot, enc_i(OP_REGIMM, rs, REGIMM_BLTZ,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_bgez(input int slot, input int rs,
                             input int target_slot);
        bios_word(slot, enc_i(OP_REGIMM, rs, REGIMM_BGEZ,
                              branch_imm(slot, target_slot)));
    endtask

    initial begin
        rst_n   = 1'b0;
        core_go = 1'b0;

        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_j  (RESET_SLOT,     BOOTSTRAP_VA);
        bios_nop(RESET_SLOT + 1);

        // Bootstrap: load $8 = +1, $9 = -1 (signed).
        bios_ori (B_ORI_8, 8, 0, 16'h0001);
        bios_lui (B_LUI_9, 9,    16'hFFFF);
        bios_ori (B_ORI_9, 9, 9, 16'hFFFF);

        // BLEZ: +1 (must NOT take), -1 (MUST take → BLEZ_OK)
        bios_blez(B_BLEZ_P, 8, B_FAIL_A);
        bios_nop (B_DS_0);
        bios_blez(B_BLEZ_N, 9, B_BLEZ_OK);
        bios_nop (B_DS_1);
        bios_syscall(B_FAIL_A);

        // BGTZ: -1 (must NOT take), +1 (MUST take → BGTZ_OK)
        bios_bgtz(B_BGTZ_N, 9, B_FAIL_B);
        bios_nop (B_DS_2);
        bios_bgtz(B_BGTZ_P, 8, B_BGTZ_OK);
        bios_nop (B_DS_3);
        bios_syscall(B_FAIL_B);

        // BLTZ: +1 (must NOT take), -1 (MUST take → BLTZ_OK)
        bios_bltz(B_BLTZ_P, 8, B_FAIL_C);
        bios_nop (B_DS_4);
        bios_bltz(B_BLTZ_N, 9, B_BLTZ_OK);
        bios_nop (B_DS_5);
        bios_syscall(B_FAIL_C);

        // BGEZ: -1 (must NOT take), +1 (MUST take → PASS)
        bios_bgez(B_BGEZ_N, 9, B_FAIL_D);
        bios_nop (B_DS_6);
        bios_bgez(B_BGEZ_P, 8, B_PASS);
        bios_nop (B_DS_7);
        bios_syscall(B_FAIL_D);

        bios_syscall(B_PASS);

        @(negedge clk);
        core_go = 1'b1;
        @(negedge clk);
        core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        if (core_halt_events != 1) begin
            $error("[tb_ee_core_branch_zero] expected 1 halt, got %0d",
                   core_halt_events);
            errors = errors + 1;
        end
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_branch_zero] unexpected strict trap: %0d",
                   core_trap_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_branch_zero] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc,
                   BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        $display("[tb_ee_core_branch_zero] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);

        if (errors == 0 &&
            core_halt_events == 1 &&
            core_trap_events == 0 &&
            core_pc == BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2))
            $display("[tb_ee_core_branch_zero] PASS");
        else
            $display("[tb_ee_core_branch_zero] FAIL");

        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_branch_zero] timeout");
        $finish;
    end

endmodule : tb_ee_core_branch_zero
