// (C) 2001-2026 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// to the terms and conditions of the Altera Program License Subscription 
// Agreement, Altera IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
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module io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_stdfn_inst_iossm #(

   localparam PORT_AXIL_ARADDR_WIDTH                          = 27,
   localparam PORT_AXIL_AWADDR_WIDTH                          = 27,
   localparam PORT_AXIL_BRESP_WIDTH                           = 2,
   localparam PORT_AXIL_RDATA_WIDTH                           = 32,
   localparam PORT_AXIL_RRESP_WIDTH                           = 2,
   localparam PORT_AXIL_WDATA_WIDTH                           = 32,
   localparam PORT_AXIL_WSTRB_WIDTH                           = 4,
   localparam PORT_CALBUS0_ADDR_WIDTH                         = 22,
   localparam PORT_CALBUS0_READDATA_WIDTH                     = 32,
   localparam PORT_CALBUS0_WRITEDATA_WIDTH                    = 32,
   localparam PORT_HADDR_WIDTH                                = 16,
   localparam PORT_HBURST_WIDTH                               = 3,
   localparam PORT_HSIZE_WIDTH                                = 3,
   localparam PORT_HTRANS_WIDTH                               = 2,
   localparam PORT_HWDATA_WIDTH                               = 32,
   localparam PORT_IOFBRADAPT_SSM_C2P_WIDTH                   = 31,
   localparam PORT_IOFBRADAPT_SSM_P2C_WIDTH                   = 8,
   localparam PORT_I_SIM_PARAM_TABLE_WIDTH                    = 16384,
   localparam PORT_MC_HRDATA_WIDTH                            = 32,
   localparam PORT_MC_HRESP_WIDTH                             = 2

) (
   input  [PORT_AXIL_ARADDR_WIDTH-1:0]                         axil_araddr,
   output                                                      axil_arready,
   input                                                       axil_arvalid,
   input  [PORT_AXIL_AWADDR_WIDTH-1:0]                         axil_awaddr,
   output                                                      axil_awready,
   input                                                       axil_awvalid,
   input                                                       axil_bready,
   output [PORT_AXIL_BRESP_WIDTH-1:0]                          axil_bresp,
   output                                                      axil_bvalid,
   output                                                      axil_clk,
   output [PORT_AXIL_RDATA_WIDTH-1:0]                          axil_rdata,
   input                                                       axil_rready,
   output [PORT_AXIL_RRESP_WIDTH-1:0]                          axil_rresp,
   output                                                      axil_rvalid,
   input  [PORT_AXIL_WDATA_WIDTH-1:0]                          axil_wdata,
   output                                                      axil_wready,
   input  [PORT_AXIL_WSTRB_WIDTH-1:0]                          axil_wstrb,
   input                                                       axil_wvalid,

   input                                                       c2p_clk,

   output [PORT_CALBUS0_ADDR_WIDTH-1:0]                        calbus0_addr,
   output                                                      calbus0_clock,
   output                                                      calbus0_read,
   input  [PORT_CALBUS0_READDATA_WIDTH-1:0]                    calbus0_readdata,
   output                                                      calbus0_rst_n,
   output                                                      calbus0_write,
   output [PORT_CALBUS0_WRITEDATA_WIDTH-1:0]                   calbus0_writedata,

   output                                                      clk_en_in,

   output [PORT_HADDR_WIDTH-1:0]                               haddr,
   output [PORT_HBURST_WIDTH-1:0]                              hburst,
   output                                                      hclk,
   output                                                      hready,
   output                                                      hresetn,
   output                                                      hsel,
   output [PORT_HSIZE_WIDTH-1:0]                               hsize,
   output [PORT_HTRANS_WIDTH-1:0]                              htrans,
   output [PORT_HWDATA_WIDTH-1:0]                              hwdata,
   output                                                      hwrite,
   input  [PORT_MC_HRDATA_WIDTH-1:0]                           mc0_hrdata,
   input                                                       mc0_hreadyout,
   input  [PORT_MC_HRESP_WIDTH-1:0]                            mc0_hresp,
   input  [PORT_MC_HRDATA_WIDTH-1:0]                           mc1_hrdata,
   input                                                       mc1_hreadyout,
   input  [PORT_MC_HRESP_WIDTH-1:0]                            mc1_hresp,

   input  [PORT_I_SIM_PARAM_TABLE_WIDTH-1:0]                   i_sim_param_table_0,
   input  [PORT_I_SIM_PARAM_TABLE_WIDTH-1:0]                   i_sim_param_table_1,
   input                                                       mc0_irq,
   input                                                       mc1_irq,
   output                                                      mc0_rst_n,
   output                                                      mc1_rst_n,

   output                                                      i3c_scl,
   output                                                      i3c_sda_dr_en_n,
   output                                                      i3c_sda_pp,
   input                                                       i3c_sda_rx,
   output                                                      i3c_sda_tx,

   input  [PORT_IOFBRADAPT_SSM_C2P_WIDTH-1:0]                  iofbradapt_ssm_c2p,
   output [PORT_IOFBRADAPT_SSM_P2C_WIDTH-1:0]                  iofbradapt_ssm_p2c
);
   timeunit 1ns;
   timeprecision 1ps;
   import io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki_atom_attr_iossm::*;

   tennm_ph2_iossm # (
      .iossm_mem_init_onekb_hexfile                         (IOSSM_MEM_INIT_ONEKB_HEXFILE),
      .iossm_mem_init_onekb                                 (IOSSM_MEM_INIT_ONEKB),
      .iossm_mem_init_hexfile                               (IOSSM_MEM_INIT_HEXFILE),
      .iossm_mem_init_99                                    (IOSSM_MEM_INIT_UPPER[99-64]),
      .iossm_mem_init_98                                    (IOSSM_MEM_INIT_UPPER[98-64]),
      .iossm_mem_init_97                                    (IOSSM_MEM_INIT_UPPER[97-64]),
      .iossm_mem_init_96                                    (IOSSM_MEM_INIT_UPPER[96-64]),
      .iossm_mem_init_95                                    (IOSSM_MEM_INIT_UPPER[95-64]),
      .iossm_mem_init_94                                    (IOSSM_MEM_INIT_UPPER[94-64]),
      .iossm_mem_init_93                                    (IOSSM_MEM_INIT_UPPER[93-64]),
      .iossm_mem_init_92                                    (IOSSM_MEM_INIT_UPPER[92-64]),
      .iossm_mem_init_91                                    (IOSSM_MEM_INIT_UPPER[91-64]),
      .iossm_mem_init_90                                    (IOSSM_MEM_INIT_UPPER[90-64]),
      .iossm_mem_init_9                                     (IOSSM_MEM_INIT_LOWER[9]),
      .iossm_mem_init_89                                    (IOSSM_MEM_INIT_UPPER[89-64]),
      .iossm_mem_init_88                                    (IOSSM_MEM_INIT_UPPER[88-64]),
      .iossm_mem_init_87                                    (IOSSM_MEM_INIT_UPPER[87-64]),
      .iossm_mem_init_86                                    (IOSSM_MEM_INIT_UPPER[86-64]),
      .iossm_mem_init_85                                    (IOSSM_MEM_INIT_UPPER[85-64]),
      .iossm_mem_init_84                                    (IOSSM_MEM_INIT_UPPER[84-64]),
      .iossm_mem_init_83                                    (IOSSM_MEM_INIT_UPPER[83-64]),
      .iossm_mem_init_82                                    (IOSSM_MEM_INIT_UPPER[82-64]),
      .iossm_mem_init_81                                    (IOSSM_MEM_INIT_UPPER[81-64]),
      .iossm_mem_init_80                                    (IOSSM_MEM_INIT_UPPER[80-64]),
      .iossm_mem_init_8                                     (IOSSM_MEM_INIT_LOWER[8]),
      .iossm_mem_init_79                                    (IOSSM_MEM_INIT_UPPER[79-64]),
      .iossm_mem_init_78                                    (IOSSM_MEM_INIT_UPPER[78-64]),
      .iossm_mem_init_77                                    (IOSSM_MEM_INIT_UPPER[77-64]),
      .iossm_mem_init_76                                    (IOSSM_MEM_INIT_UPPER[76-64]),
      .iossm_mem_init_75                                    (IOSSM_MEM_INIT_UPPER[75-64]),
      .iossm_mem_init_74                                    (IOSSM_MEM_INIT_UPPER[74-64]),
      .iossm_mem_init_73                                    (IOSSM_MEM_INIT_UPPER[73-64]),
      .iossm_mem_init_72                                    (IOSSM_MEM_INIT_UPPER[72-64]),
      .iossm_mem_init_71                                    (IOSSM_MEM_INIT_UPPER[71-64]),
      .iossm_mem_init_70                                    (IOSSM_MEM_INIT_UPPER[70-64]),
      .iossm_mem_init_7                                     (IOSSM_MEM_INIT_LOWER[7]),
      .iossm_mem_init_69                                    (IOSSM_MEM_INIT_UPPER[69-64]),
      .iossm_mem_init_68                                    (IOSSM_MEM_INIT_UPPER[68-64]),
      .iossm_mem_init_67                                    (IOSSM_MEM_INIT_UPPER[67-64]),
      .iossm_mem_init_66                                    (IOSSM_MEM_INIT_UPPER[66-64]),
      .iossm_mem_init_65                                    (IOSSM_MEM_INIT_UPPER[65-64]),
      .iossm_mem_init_64                                    (IOSSM_MEM_INIT_UPPER[64-64]),
      .iossm_mem_init_63                                    (IOSSM_MEM_INIT_LOWER[63]),
      .iossm_mem_init_62                                    (IOSSM_MEM_INIT_LOWER[62]),
      .iossm_mem_init_61                                    (IOSSM_MEM_INIT_LOWER[61]),
      .iossm_mem_init_60                                    (IOSSM_MEM_INIT_LOWER[60]),
      .iossm_mem_init_6                                     (IOSSM_MEM_INIT_LOWER[6]),
      .iossm_mem_init_59                                    (IOSSM_MEM_INIT_LOWER[59]),
      .iossm_mem_init_58                                    (IOSSM_MEM_INIT_LOWER[58]),
      .iossm_mem_init_57                                    (IOSSM_MEM_INIT_LOWER[57]),
      .iossm_mem_init_56                                    (IOSSM_MEM_INIT_LOWER[56]),
      .iossm_mem_init_55                                    (IOSSM_MEM_INIT_LOWER[55]),
      .iossm_mem_init_54                                    (IOSSM_MEM_INIT_LOWER[54]),
      .iossm_mem_init_53                                    (IOSSM_MEM_INIT_LOWER[53]),
      .iossm_mem_init_52                                    (IOSSM_MEM_INIT_LOWER[52]),
      .iossm_mem_init_51                                    (IOSSM_MEM_INIT_LOWER[51]),
      .iossm_mem_init_50                                    (IOSSM_MEM_INIT_LOWER[50]),
      .iossm_mem_init_5                                     (IOSSM_MEM_INIT_LOWER[5]),
      .iossm_mem_init_49                                    (IOSSM_MEM_INIT_LOWER[49]),
      .iossm_mem_init_48                                    (IOSSM_MEM_INIT_LOWER[48]),
      .iossm_mem_init_47                                    (IOSSM_MEM_INIT_LOWER[47]),
      .iossm_mem_init_46                                    (IOSSM_MEM_INIT_LOWER[46]),
      .iossm_mem_init_45                                    (IOSSM_MEM_INIT_LOWER[45]),
      .iossm_mem_init_44                                    (IOSSM_MEM_INIT_LOWER[44]),
      .iossm_mem_init_43                                    (IOSSM_MEM_INIT_LOWER[43]),
      .iossm_mem_init_42                                    (IOSSM_MEM_INIT_LOWER[42]),
      .iossm_mem_init_41                                    (IOSSM_MEM_INIT_LOWER[41]),
      .iossm_mem_init_40                                    (IOSSM_MEM_INIT_LOWER[40]),
      .iossm_mem_init_4                                     (IOSSM_MEM_INIT_LOWER[4]),
      .iossm_mem_init_39                                    (IOSSM_MEM_INIT_LOWER[39]),
      .iossm_mem_init_38                                    (IOSSM_MEM_INIT_LOWER[38]),
      .iossm_mem_init_37                                    (IOSSM_MEM_INIT_LOWER[37]),
      .iossm_mem_init_36                                    (IOSSM_MEM_INIT_LOWER[36]),
      .iossm_mem_init_35                                    (IOSSM_MEM_INIT_LOWER[35]),
      .iossm_mem_init_34                                    (IOSSM_MEM_INIT_LOWER[34]),
      .iossm_mem_init_33                                    (IOSSM_MEM_INIT_LOWER[33]),
      .iossm_mem_init_32                                    (IOSSM_MEM_INIT_LOWER[32]),
      .iossm_mem_init_31                                    (IOSSM_MEM_INIT_LOWER[31]),
      .iossm_mem_init_30                                    (IOSSM_MEM_INIT_LOWER[30]),
      .iossm_mem_init_3                                     (IOSSM_MEM_INIT_LOWER[3]),
      .iossm_mem_init_29                                    (IOSSM_MEM_INIT_LOWER[29]),
      .iossm_mem_init_28                                    (IOSSM_MEM_INIT_LOWER[28]),
      .iossm_mem_init_27                                    (IOSSM_MEM_INIT_LOWER[27]),
      .iossm_mem_init_26                                    (IOSSM_MEM_INIT_LOWER[26]),
      .iossm_mem_init_25                                    (IOSSM_MEM_INIT_LOWER[25]),
      .iossm_mem_init_24                                    (IOSSM_MEM_INIT_LOWER[24]),
      .iossm_mem_init_23                                    (IOSSM_MEM_INIT_LOWER[23]),
      .iossm_mem_init_22                                    (IOSSM_MEM_INIT_LOWER[22]),
      .iossm_mem_init_21                                    (IOSSM_MEM_INIT_LOWER[21]),
      .iossm_mem_init_20                                    (IOSSM_MEM_INIT_LOWER[20]),
      .iossm_mem_init_2                                     (IOSSM_MEM_INIT_LOWER[2]),
      .iossm_mem_init_19                                    (IOSSM_MEM_INIT_LOWER[19]),
      .iossm_mem_init_18                                    (IOSSM_MEM_INIT_LOWER[18]),
      .iossm_mem_init_17                                    (IOSSM_MEM_INIT_LOWER[17]),
      .iossm_mem_init_16                                    (IOSSM_MEM_INIT_LOWER[16]),
      .iossm_mem_init_15                                    (IOSSM_MEM_INIT_LOWER[15]),
      .iossm_mem_init_14                                    (IOSSM_MEM_INIT_LOWER[14]),
      .iossm_mem_init_13                                    (IOSSM_MEM_INIT_LOWER[13]),
      .iossm_mem_init_127                                   (IOSSM_MEM_INIT_UPPER[127-64]),
      .iossm_mem_init_126                                   (IOSSM_MEM_INIT_UPPER[126-64]),
      .iossm_mem_init_125                                   (IOSSM_MEM_INIT_UPPER[125-64]),
      .iossm_mem_init_124                                   (IOSSM_MEM_INIT_UPPER[124-64]),
      .iossm_mem_init_123                                   (IOSSM_MEM_INIT_UPPER[123-64]),
      .iossm_mem_init_122                                   (IOSSM_MEM_INIT_UPPER[122-64]),
      .iossm_mem_init_121                                   (IOSSM_MEM_INIT_UPPER[121-64]),
      .iossm_mem_init_120                                   (IOSSM_MEM_INIT_UPPER[120-64]),
      .iossm_mem_init_12                                    (IOSSM_MEM_INIT_LOWER[12]),
      .iossm_mem_init_119                                   (IOSSM_MEM_INIT_UPPER[119-64]),
      .iossm_mem_init_118                                   (IOSSM_MEM_INIT_UPPER[118-64]),
      .iossm_mem_init_117                                   (IOSSM_MEM_INIT_UPPER[117-64]),
      .iossm_mem_init_116                                   (IOSSM_MEM_INIT_UPPER[116-64]),
      .iossm_mem_init_115                                   (IOSSM_MEM_INIT_UPPER[115-64]),
      .iossm_mem_init_114                                   (IOSSM_MEM_INIT_UPPER[114-64]),
      .iossm_mem_init_113                                   (IOSSM_MEM_INIT_UPPER[113-64]),
      .iossm_mem_init_112                                   (IOSSM_MEM_INIT_UPPER[112-64]),
      .iossm_mem_init_111                                   (IOSSM_MEM_INIT_UPPER[111-64]),
      .iossm_mem_init_110                                   (IOSSM_MEM_INIT_UPPER[110-64]),
      .iossm_mem_init_11                                    (IOSSM_MEM_INIT_LOWER[11]),
      .iossm_mem_init_109                                   (IOSSM_MEM_INIT_UPPER[109-64]),
      .iossm_mem_init_108                                   (IOSSM_MEM_INIT_UPPER[108-64]),
      .iossm_mem_init_107                                   (IOSSM_MEM_INIT_UPPER[107-64]),
      .iossm_mem_init_106                                   (IOSSM_MEM_INIT_UPPER[106-64]),
      .iossm_mem_init_105                                   (IOSSM_MEM_INIT_UPPER[105-64]),
      .iossm_mem_init_104                                   (IOSSM_MEM_INIT_UPPER[104-64]),
      .iossm_mem_init_103                                   (IOSSM_MEM_INIT_UPPER[103-64]),
      .iossm_mem_init_102                                   (IOSSM_MEM_INIT_UPPER[102-64]),
      .iossm_mem_init_101                                   (IOSSM_MEM_INIT_UPPER[101-64]),
      .iossm_mem_init_100                                   (IOSSM_MEM_INIT_UPPER[100-64]),
      .iossm_mem_init_10                                    (IOSSM_MEM_INIT_LOWER[10]),
      .iossm_mem_init_1                                     (IOSSM_MEM_INIT_LOWER[1]),
      .iossm_mem_init_0                                     (IOSSM_MEM_INIT_LOWER[0]),
      .parameter_table_hexfile                              (PARAMETER_TABLE_HEXFILE)
   ) iossm (
      .axil_araddr                                          (axil_araddr),
      .axil_arready                                         (axil_arready),
      .axil_arvalid                                         (axil_arvalid),
      .axil_awaddr                                          (axil_awaddr),
      .axil_awready                                         (axil_awready),
      .axil_awvalid                                         (axil_awvalid),
      .axil_bready                                          (axil_bready),
      .axil_bresp                                           (axil_bresp),
      .axil_bvalid                                          (axil_bvalid),
      .axil_clk                                             (axil_clk),
      .axil_rdata                                           (axil_rdata),
      .axil_rready                                          (axil_rready),
      .axil_rresp                                           (axil_rresp),
      .axil_rvalid                                          (axil_rvalid),
      .axil_wdata                                           (axil_wdata),
      .axil_wready                                          (axil_wready),
      .axil_wstrb                                           (axil_wstrb),
      .axil_wvalid                                          (axil_wvalid),
      .c2p_clk                                              (c2p_clk),
      .calbus0_addr                                         (calbus0_addr),
      .calbus0_clock                                        (calbus0_clock),
      .calbus0_read                                         (calbus0_read),
      .calbus0_readdata                                     (calbus0_readdata),
      .calbus0_rst_n                                        (calbus0_rst_n),
      .calbus0_write                                        (calbus0_write),
      .calbus0_writedata                                    (calbus0_writedata),
      .clk_en_in                                            (clk_en_in),
      .haddr                                                (haddr),
      .hburst                                               (hburst),
      .hclk                                                 (hclk),
      .hready                                               (hready),
      .hresetn                                              (hresetn),
      .hsel                                                 (hsel),
      .hsize                                                (hsize),
      .htrans                                               (htrans),
      .hwdata                                               (hwdata),
      .hwrite                                               (hwrite),
      .i3c_scl                                              (i3c_scl),
      .i3c_sda_dr_en_n                                      (i3c_sda_dr_en_n),
      .i3c_sda_pp                                           (i3c_sda_pp),
      .i3c_sda_rx                                           (i3c_sda_rx),
      .i3c_sda_tx                                           (i3c_sda_tx),
      .iofbradapt_ssm_c2p                                   (iofbradapt_ssm_c2p),
      .iofbradapt_ssm_p2c                                   (iofbradapt_ssm_p2c),
      .i_sim_param_table_0                                  (i_sim_param_table_0),
      .i_sim_param_table_1                                  (i_sim_param_table_1),
      .mc0_hrdata                                           (mc0_hrdata),
      .mc0_hreadyout                                        (mc0_hreadyout),
      .mc0_hresp                                            (mc0_hresp),
      .mc0_irq                                              (mc0_irq),
      .mc0_rst_n                                            (mc0_rst_n),
      .mc1_hrdata                                           (mc1_hrdata),
      .mc1_hreadyout                                        (mc1_hreadyout),
      .mc1_hresp                                            (mc1_hresp),
      .mc1_irq                                              (mc1_irq),
      .mc1_rst_n                                            (mc1_rst_n)
   );

endmodule


