// emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.v

// Generated using ACDS version 26.1 110

`timescale 1 ps / 1 ps
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio (
		output wire [0:0] dout,   //   dout.export, Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode: Bypass or simple register - DATA_SIZE = SIZE DDIO - DATA_SIZE = 2 x SIZE
		input  wire [0:0] pad_in  // pad_in.export, Input signal from the pad.
	);

	emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio_altera_gpio_2300_ctzjwfq refclk_gpio (
		.dout   (dout),   //  output,  width = 1,   dout.export
		.pad_in (pad_in)  //   input,  width = 1, pad_in.export
	);

endmodule
