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module io0_emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_420_cy5n3cq_phy_arch_fp_atom_inst_reftree #(
) (
   input   logic pin_to_reftree,
   output  logic reftree_to_pll
);
   timeunit 1ns;
   timeprecision 1ps;

   logic     self_clk_in;
   logic     self_clk_out;
   logic     tp_clk;
   logic     btm_clk;

   assign reftree_to_pll = self_clk_out;

   assign self_clk_in = pin_to_reftree;


   tennm_reftree_bal # (
   ) reftree (
      .self_clk_in                    (self_clk_in),
      .self_clk_out                   (self_clk_out),
      .tp_clk                         (tp_clk),
      .btm_clk                        (btm_clk)
   );

endmodule


