// emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.v

// Generated using ACDS version 26.1 110

`timescale 1 ps / 1 ps
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge (
		input  wire  refclk_in,       //       refclk_in.clk
		output wire  refclk_out,      //      refclk_out.clk
		output wire  refclk_in_gpio,  //  refclk_in_gpio.export
		input  wire  refclk_out_gpio  // refclk_out_gpio.export
	);

	emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi refclk_bridge (
		.refclk_in       (refclk_in),       //   input,  width = 1,       refclk_in.clk
		.refclk_out      (refclk_out),      //  output,  width = 1,      refclk_out.clk
		.refclk_in_gpio  (refclk_in_gpio),  //  output,  width = 1,  refclk_in_gpio.export
		.refclk_out_gpio (refclk_out_gpio)  //   input,  width = 1, refclk_out_gpio.export
	);

endmodule
