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module ed_synth_dut_intel_axi4lite_injector_100_2yowc3a #(
   parameter NUM_ACTIVE_AXI4LITE_S_INTERFACES                   = 0,
   parameter AXI4LITE_QOS                                       = 0,
   parameter NUM_ACTIVE_AXI4_S_INTERFACES                       = 0,
   parameter BUFFER_AXI4_S_READ_RESPONSES                       = 0,
   parameter AXI4_S_TRANSFER_MULTIPLE                           = 0,
   parameter INIU_AXI4_ADDR_WIDTH                               = 0
) (
   input  logic            m_axi4_aclk,
   input  logic            m_axi4_aresetn,
   output logic [6:0]      m_axi4_arid,
   output logic [31:0]     m_axi4_araddr,
   output logic [7:0]      m_axi4_arlen,
   output logic [2:0]      m_axi4_arsize,
   output logic [1:0]      m_axi4_arburst,
   output logic            m_axi4_arlock,
   output logic [2:0]      m_axi4_arprot,
   output logic [3:0]      m_axi4_arqos,
   output logic [10:0]     m_axi4_aruser,
   output logic            m_axi4_arvalid,
   input  logic            m_axi4_arready,
   input  logic [6:0]      m_axi4_rid,
   input  logic [255:0]    m_axi4_rdata,
   input  logic [1:0]      m_axi4_rresp,
   input  logic            m_axi4_rlast,
   input  logic [31:0]     m_axi4_ruser,
   input  logic            m_axi4_rvalid,
   output logic            m_axi4_rready,
   output logic [6:0]      m_axi4_awid,
   output logic [31:0]     m_axi4_awaddr,
   output logic [7:0]      m_axi4_awlen,
   output logic [2:0]      m_axi4_awsize,
   output logic [1:0]      m_axi4_awburst,
   output logic            m_axi4_awlock,
   output logic [2:0]      m_axi4_awprot,
   output logic [3:0]      m_axi4_awqos,
   output logic [10:0]     m_axi4_awuser,
   output logic            m_axi4_awvalid,
   input  logic            m_axi4_awready,
   output logic [255:0]    m_axi4_wdata,
   output logic [31:0]     m_axi4_wstrb,
   output logic            m_axi4_wlast,
   output logic [31:0]     m_axi4_wuser,
   output logic            m_axi4_wvalid,
   input  logic            m_axi4_wready,
   input  logic [6:0]      m_axi4_bid,
   input  logic [1:0]      m_axi4_bresp,
   input  logic            m_axi4_bvalid,
   output logic            m_axi4_bready,
   input  logic            s0_axi4lite_aclk,
   input  logic            s0_axi4lite_aresetn,
   input  logic [31:0]     s0_axi4lite_awaddr,
   input  logic            s0_axi4lite_awvalid,
   output logic            s0_axi4lite_awready,
   input  logic [31:0]     s0_axi4lite_wdata,
   input  logic [3:0]      s0_axi4lite_wstrb,
   input  logic            s0_axi4lite_wvalid,
   output logic            s0_axi4lite_wready,
   output logic [1:0]      s0_axi4lite_bresp,
   output logic            s0_axi4lite_bvalid,
   input  logic            s0_axi4lite_bready,
   input  logic [31:0]     s0_axi4lite_araddr,
   input  logic            s0_axi4lite_arvalid,
   output logic            s0_axi4lite_arready,
   output logic [31:0]     s0_axi4lite_rdata,
   output logic [1:0]      s0_axi4lite_rresp,
   output logic            s0_axi4lite_rvalid,
   input  logic            s0_axi4lite_rready,
   input  logic [2:0]      s0_axi4lite_awprot,
   input  logic [2:0]      s0_axi4lite_arprot,
   input  logic            s1_axi4lite_aclk,
   input  logic            s1_axi4lite_aresetn,
   input  logic [31:0]     s1_axi4lite_awaddr,
   input  logic            s1_axi4lite_awvalid,
   output logic            s1_axi4lite_awready,
   input  logic [31:0]     s1_axi4lite_wdata,
   input  logic [3:0]      s1_axi4lite_wstrb,
   input  logic            s1_axi4lite_wvalid,
   output logic            s1_axi4lite_wready,
   output logic [1:0]      s1_axi4lite_bresp,
   output logic            s1_axi4lite_bvalid,
   input  logic            s1_axi4lite_bready,
   input  logic [31:0]     s1_axi4lite_araddr,
   input  logic            s1_axi4lite_arvalid,
   output logic            s1_axi4lite_arready,
   output logic [31:0]     s1_axi4lite_rdata,
   output logic [1:0]      s1_axi4lite_rresp,
   output logic            s1_axi4lite_rvalid,
   input  logic            s1_axi4lite_rready,
   input  logic [2:0]      s1_axi4lite_awprot,
   input  logic [2:0]      s1_axi4lite_arprot
);
   timeunit 1ns;
   timeprecision 1ps;

   intel_axi4lite_injector_ph2 # (
      .NUM_ACTIVE_AXI4LITE_S_INTERFACES (NUM_ACTIVE_AXI4LITE_S_INTERFACES),
      .AXI4LITE_QOS (AXI4LITE_QOS),
      .NUM_ACTIVE_AXI4_S_INTERFACES (NUM_ACTIVE_AXI4_S_INTERFACES),
      .BUFFER_AXI4_S_READ_RESPONSES (BUFFER_AXI4_S_READ_RESPONSES),
      .AXI4_S_TRANSFER_MULTIPLE (AXI4_S_TRANSFER_MULTIPLE),
      .INIU_AXI4_ADDR_WIDTH (INIU_AXI4_ADDR_WIDTH)
   ) intel_axi4lite_injector_ph2_inst (
      .m_axi4_aclk (m_axi4_aclk),
      .m_axi4_aresetn (m_axi4_aresetn),
      .m_axi4_arid (m_axi4_arid),
      .m_axi4_araddr (m_axi4_araddr),
      .m_axi4_arlen (m_axi4_arlen),
      .m_axi4_arsize (m_axi4_arsize),
      .m_axi4_arburst (m_axi4_arburst),
      .m_axi4_arlock (m_axi4_arlock),
      .m_axi4_arprot (m_axi4_arprot),
      .m_axi4_arqos (m_axi4_arqos),
      .m_axi4_aruser (m_axi4_aruser),
      .m_axi4_arvalid (m_axi4_arvalid),
      .m_axi4_arready (m_axi4_arready),
      .m_axi4_rid (m_axi4_rid),
      .m_axi4_rdata (m_axi4_rdata),
      .m_axi4_rresp (m_axi4_rresp),
      .m_axi4_rlast (m_axi4_rlast),
      .m_axi4_ruser (m_axi4_ruser),
      .m_axi4_rvalid (m_axi4_rvalid),
      .m_axi4_rready (m_axi4_rready),
      .m_axi4_awid (m_axi4_awid),
      .m_axi4_awaddr (m_axi4_awaddr),
      .m_axi4_awlen (m_axi4_awlen),
      .m_axi4_awsize (m_axi4_awsize),
      .m_axi4_awburst (m_axi4_awburst),
      .m_axi4_awlock (m_axi4_awlock),
      .m_axi4_awprot (m_axi4_awprot),
      .m_axi4_awqos (m_axi4_awqos),
      .m_axi4_awuser (m_axi4_awuser),
      .m_axi4_awvalid (m_axi4_awvalid),
      .m_axi4_awready (m_axi4_awready),
      .m_axi4_wdata (m_axi4_wdata),
      .m_axi4_wstrb (m_axi4_wstrb),
      .m_axi4_wlast (m_axi4_wlast),
      .m_axi4_wuser (m_axi4_wuser),
      .m_axi4_wvalid (m_axi4_wvalid),
      .m_axi4_wready (m_axi4_wready),
      .m_axi4_bid (m_axi4_bid),
      .m_axi4_bresp (m_axi4_bresp),
      .m_axi4_bvalid (m_axi4_bvalid),
      .m_axi4_bready (m_axi4_bready),
      .s0_axi4lite_aclk (s0_axi4lite_aclk),
      .s0_axi4lite_aresetn (s0_axi4lite_aresetn),
      .s0_axi4lite_awaddr (s0_axi4lite_awaddr),
      .s0_axi4lite_awvalid (s0_axi4lite_awvalid),
      .s0_axi4lite_awready (s0_axi4lite_awready),
      .s0_axi4lite_wdata (s0_axi4lite_wdata),
      .s0_axi4lite_wstrb (s0_axi4lite_wstrb),
      .s0_axi4lite_wvalid (s0_axi4lite_wvalid),
      .s0_axi4lite_wready (s0_axi4lite_wready),
      .s0_axi4lite_bresp (s0_axi4lite_bresp),
      .s0_axi4lite_bvalid (s0_axi4lite_bvalid),
      .s0_axi4lite_bready (s0_axi4lite_bready),
      .s0_axi4lite_araddr (s0_axi4lite_araddr),
      .s0_axi4lite_arvalid (s0_axi4lite_arvalid),
      .s0_axi4lite_arready (s0_axi4lite_arready),
      .s0_axi4lite_rdata (s0_axi4lite_rdata),
      .s0_axi4lite_rresp (s0_axi4lite_rresp),
      .s0_axi4lite_rvalid (s0_axi4lite_rvalid),
      .s0_axi4lite_rready (s0_axi4lite_rready),
      .s0_axi4lite_awprot (s0_axi4lite_awprot),
      .s0_axi4lite_arprot (s0_axi4lite_arprot),
      .s1_axi4lite_aclk (s1_axi4lite_aclk),
      .s1_axi4lite_aresetn (s1_axi4lite_aresetn),
      .s1_axi4lite_awaddr (s1_axi4lite_awaddr),
      .s1_axi4lite_awvalid (s1_axi4lite_awvalid),
      .s1_axi4lite_awready (s1_axi4lite_awready),
      .s1_axi4lite_wdata (s1_axi4lite_wdata),
      .s1_axi4lite_wstrb (s1_axi4lite_wstrb),
      .s1_axi4lite_wvalid (s1_axi4lite_wvalid),
      .s1_axi4lite_wready (s1_axi4lite_wready),
      .s1_axi4lite_bresp (s1_axi4lite_bresp),
      .s1_axi4lite_bvalid (s1_axi4lite_bvalid),
      .s1_axi4lite_bready (s1_axi4lite_bready),
      .s1_axi4lite_araddr (s1_axi4lite_araddr),
      .s1_axi4lite_arvalid (s1_axi4lite_arvalid),
      .s1_axi4lite_arready (s1_axi4lite_arready),
      .s1_axi4lite_rdata (s1_axi4lite_rdata),
      .s1_axi4lite_rresp (s1_axi4lite_rresp),
      .s1_axi4lite_rvalid (s1_axi4lite_rvalid),
      .s1_axi4lite_rready (s1_axi4lite_rready),
      .s1_axi4lite_awprot (s1_axi4lite_awprot),
      .s1_axi4lite_arprot (s1_axi4lite_arprot)
   );
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "g4C5XhiVgIsot17RhmniMaWr74zBSsEIWWpvrh2OfY7zsE/GRUwh+h8kwFouKZM7aDVnfodYGq3Rk/+aIV/LhmOnotIFWwTLHeCg4q58QY8ebBhDunmhEw9pVeSnxyIfZOF36bcFs+PPu8zFjUpUmwPp0ZayeeNNAzuyoBxofiuKXveyhtMEYKr58+sGPuygd1q2QgWCXeNeK3v7pUsh+Ke+UaVach9SikQZsUX/o1q5dG6bEO/NZ8AQst3yqICQkVlklQPhbpRzpYxDxqq2w2C+JJ6E+xy5Y9+y7f9qb6LryOD4upBkqZ9ZCN9zZw/dBH1WNVHvKM8osJPxb6bjyMKcucVJ7p8mKODdE66uohcuUKs2nWYE9OUe7br9bcv23GHdv7r/pM/1bZICOH37VWUMjChmotzU5E/dkpC4zrRKIEGRHTVWW8Lql5xxb0o+h7AJukS+f1JRh63bqyeqKbxlTDZanfoK4zSaMjCamjwLs4rug5S55YZlZ2lrIzpQDNxKhqrseoWF20OQqn7kRPjaObblu8g1jKmpWErriYzE0u9qY1oBo/6QOrmPMnNwuEXgYJ1vcjNJuC+U9lB5eGrw9v3KRSFj9igE/OQ8uW3MNzu9khYD36qIrnlbwIRsXk+a9CI+TppwtBJkquSa1qnSVnrI1c2g2ROB5rQZFcDvWG55BNgfYFLDZ1fX8479JDQp66ZusAkDNPYndswc0mk9Z9zpWPB4vy5PeuP4OulhXAO9adUH47raRNRx6qMkJLthvqlPgO+nQ4b86jNVAAIok4f3TVEPtudMjqhLLRmAxDASF/L3LXsNJb2w2pTpuzrRnOei4EnTdGZ+3Edq1X0wsykgJy1u3E1nYAnRicd1qOx5EwJebPsCkMdjkfXis7tK3tRWOyVbg9ixqgzVtVkyvrh4W9ldeQZ7XxSt3BzQLp/Z1tL88CbxqNh94GgGLtJ1cyvqXK/tMc0ciVeJ922LbblYkeF1Yp/IKoW9R0MAYADjyJCDmkpl/I00yaJp"
`endif