// emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v

// Generated using ACDS version 26.1 110

`timescale 1 ps / 1 ps
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq (
		output wire         s0_noc_axi4lite_clock,   // io96b0_to_hps.ch0_axil_clk
		output wire         s0_noc_axi4lite_reset_n, //              .ch0_axil_reset_n
		input  wire [26:0]  s0_noc_axi4lite_awaddr,  //              .ch0_axil_awaddr
		input  wire         s0_noc_axi4lite_awvalid, //              .ch0_axil_awvalid
		output wire         s0_noc_axi4lite_awready, //              .ch0_axil_awready
		input  wire [26:0]  s0_noc_axi4lite_araddr,  //              .ch0_axil_araddr
		input  wire         s0_noc_axi4lite_arvalid, //              .ch0_axil_arvalid
		output wire         s0_noc_axi4lite_arready, //              .ch0_axil_arready
		input  wire [31:0]  s0_noc_axi4lite_wdata,   //              .ch0_axil_wdata
		input  wire         s0_noc_axi4lite_wvalid,  //              .ch0_axil_wvalid
		output wire         s0_noc_axi4lite_wready,  //              .ch0_axil_wready
		output wire [1:0]   s0_noc_axi4lite_rresp,   //              .ch0_axil_rresp
		output wire [31:0]  s0_noc_axi4lite_rdata,   //              .ch0_axil_rdata
		output wire         s0_noc_axi4lite_rvalid,  //              .ch0_axil_rvalid
		input  wire         s0_noc_axi4lite_rready,  //              .ch0_axil_rready
		output wire [1:0]   s0_noc_axi4lite_bresp,   //              .ch0_axil_bresp
		output wire         s0_noc_axi4lite_bvalid,  //              .ch0_axil_bvalid
		input  wire         s0_noc_axi4lite_bready,  //              .ch0_axil_bready
		input  wire [2:0]   s0_noc_axi4lite_awprot,  //              .ch0_axil_awprot
		input  wire [2:0]   s0_noc_axi4lite_arprot,  //              .ch0_axil_arprot
		input  wire [3:0]   s0_noc_axi4lite_wstrb,   //              .ch0_axil_wstrb
		input  wire [39:0]  s0_axi4_awaddr,          //              .axi4_ch0_awaddr
		input  wire [1:0]   s0_axi4_awburst,         //              .axi4_ch0_awburst
		input  wire [6:0]   s0_axi4_awid,            //              .axi4_ch0_awid
		input  wire [7:0]   s0_axi4_awlen,           //              .axi4_ch0_awlen
		input  wire         s0_axi4_awlock,          //              .axi4_ch0_awlock
		input  wire [3:0]   s0_axi4_awqos,           //              .axi4_ch0_awqos
		input  wire [2:0]   s0_axi4_awsize,          //              .axi4_ch0_awsize
		input  wire         s0_axi4_awvalid,         //              .axi4_ch0_awvalid
		input  wire [13:0]  s0_axi4_awuser,          //              .axi4_ch0_awuser
		input  wire [2:0]   s0_axi4_awprot,          //              .axi4_ch0_awprot
		output wire         s0_axi4_awready,         //              .axi4_ch0_awready
		input  wire [39:0]  s0_axi4_araddr,          //              .axi4_ch0_araddr
		input  wire [1:0]   s0_axi4_arburst,         //              .axi4_ch0_arburst
		input  wire [6:0]   s0_axi4_arid,            //              .axi4_ch0_arid
		input  wire [7:0]   s0_axi4_arlen,           //              .axi4_ch0_arlen
		input  wire         s0_axi4_arlock,          //              .axi4_ch0_arlock
		input  wire [3:0]   s0_axi4_arqos,           //              .axi4_ch0_arqos
		input  wire [2:0]   s0_axi4_arsize,          //              .axi4_ch0_arsize
		input  wire         s0_axi4_arvalid,         //              .axi4_ch0_arvalid
		input  wire [13:0]  s0_axi4_aruser,          //              .axi4_ch0_aruser
		input  wire [2:0]   s0_axi4_arprot,          //              .axi4_ch0_arprot
		output wire         s0_axi4_arready,         //              .axi4_ch0_arready
		input  wire [255:0] s0_axi4_wdata,           //              .axi4_ch0_wdata
		input  wire [31:0]  s0_axi4_wstrb,           //              .axi4_ch0_wstrb
		input  wire         s0_axi4_wlast,           //              .axi4_ch0_wlast
		input  wire         s0_axi4_wvalid,          //              .axi4_ch0_wvalid
		output wire         s0_axi4_wready,          //              .axi4_ch0_wready
		input  wire         s0_axi4_bready,          //              .axi4_ch0_bready
		output wire [6:0]   s0_axi4_bid,             //              .axi4_ch0_bid
		output wire [1:0]   s0_axi4_bresp,           //              .axi4_ch0_bresp
		output wire         s0_axi4_bvalid,          //              .axi4_ch0_bvalid
		input  wire         s0_axi4_rready,          //              .axi4_ch0_rready
		output wire [255:0] s0_axi4_rdata,           //              .axi4_ch0_rdata
		output wire [6:0]   s0_axi4_rid,             //              .axi4_ch0_rid
		output wire         s0_axi4_rlast,           //              .axi4_ch0_rlast
		output wire [1:0]   s0_axi4_rresp,           //              .axi4_ch0_rresp
		output wire         s0_axi4_rvalid,          //              .axi4_ch0_rvalid
		output wire         noc_aclk_0,              //              .axi4_ch0_clk
		output wire         noc_rst_n_0,             //              .axi4_ch0_reset_n
		input  wire [31:0]  s0_axi4_wuser,           //              .axi4_ch0_wuser
		output wire [31:0]  s0_axi4_ruser,           //              .axi4_ch0_ruser
		output wire [0:0]   mem_0_cs,                //         mem_0.mem_cs
		output wire [5:0]   mem_0_ca,                //              .mem_ca
		output wire [0:0]   mem_0_cke,               //              .mem_cke
		inout  wire [31:0]  mem_0_dq,                //              .mem_dq
		inout  wire [3:0]   mem_0_dqs_t,             //              .mem_dqs_t
		inout  wire [3:0]   mem_0_dqs_c,             //              .mem_dqs_c
		inout  wire [3:0]   mem_0_dmi,               //              .mem_dmi
		output wire [0:0]   mem_0_ck_t,              //      mem_ck_0.mem_ck_t
		output wire [0:0]   mem_0_ck_c,              //              .mem_ck_c
		output wire         mem_0_reset_n,           //   mem_reset_n.mem_reset_n
		input  wire         oct_rzqin_0,             //         oct_0.oct_rzqin
		input  wire         ref_clk                  //       ref_clk.clk
	);

	wire        refclk_bridge_refclk_out_clk;        // refclk_bridge:refclk_out -> emif_0_lpddr4:ref_clk
	wire  [0:0] refclk_gpio_dout_export;             // refclk_gpio:dout -> refclk_bridge:refclk_out_gpio
	wire        refclk_bridge_refclk_in_gpio_export; // refclk_bridge:refclk_in_gpio -> refclk_gpio:pad_in

	emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4 emif_0_lpddr4 (
		.s0_noc_axi4lite_clock   (s0_noc_axi4lite_clock),        //  output,    width = 1, io96b0_to_hps.ch0_axil_clk
		.s0_noc_axi4lite_reset_n (s0_noc_axi4lite_reset_n),      //  output,    width = 1,              .ch0_axil_reset_n
		.s0_noc_axi4lite_awaddr  (s0_noc_axi4lite_awaddr),       //   input,   width = 27,              .ch0_axil_awaddr
		.s0_noc_axi4lite_awvalid (s0_noc_axi4lite_awvalid),      //   input,    width = 1,              .ch0_axil_awvalid
		.s0_noc_axi4lite_awready (s0_noc_axi4lite_awready),      //  output,    width = 1,              .ch0_axil_awready
		.s0_noc_axi4lite_araddr  (s0_noc_axi4lite_araddr),       //   input,   width = 27,              .ch0_axil_araddr
		.s0_noc_axi4lite_arvalid (s0_noc_axi4lite_arvalid),      //   input,    width = 1,              .ch0_axil_arvalid
		.s0_noc_axi4lite_arready (s0_noc_axi4lite_arready),      //  output,    width = 1,              .ch0_axil_arready
		.s0_noc_axi4lite_wdata   (s0_noc_axi4lite_wdata),        //   input,   width = 32,              .ch0_axil_wdata
		.s0_noc_axi4lite_wvalid  (s0_noc_axi4lite_wvalid),       //   input,    width = 1,              .ch0_axil_wvalid
		.s0_noc_axi4lite_wready  (s0_noc_axi4lite_wready),       //  output,    width = 1,              .ch0_axil_wready
		.s0_noc_axi4lite_rresp   (s0_noc_axi4lite_rresp),        //  output,    width = 2,              .ch0_axil_rresp
		.s0_noc_axi4lite_rdata   (s0_noc_axi4lite_rdata),        //  output,   width = 32,              .ch0_axil_rdata
		.s0_noc_axi4lite_rvalid  (s0_noc_axi4lite_rvalid),       //  output,    width = 1,              .ch0_axil_rvalid
		.s0_noc_axi4lite_rready  (s0_noc_axi4lite_rready),       //   input,    width = 1,              .ch0_axil_rready
		.s0_noc_axi4lite_bresp   (s0_noc_axi4lite_bresp),        //  output,    width = 2,              .ch0_axil_bresp
		.s0_noc_axi4lite_bvalid  (s0_noc_axi4lite_bvalid),       //  output,    width = 1,              .ch0_axil_bvalid
		.s0_noc_axi4lite_bready  (s0_noc_axi4lite_bready),       //   input,    width = 1,              .ch0_axil_bready
		.s0_noc_axi4lite_awprot  (s0_noc_axi4lite_awprot),       //   input,    width = 3,              .ch0_axil_awprot
		.s0_noc_axi4lite_arprot  (s0_noc_axi4lite_arprot),       //   input,    width = 3,              .ch0_axil_arprot
		.s0_noc_axi4lite_wstrb   (s0_noc_axi4lite_wstrb),        //   input,    width = 4,              .ch0_axil_wstrb
		.s0_axi4_awaddr          (s0_axi4_awaddr),               //   input,   width = 40,              .axi4_ch0_awaddr
		.s0_axi4_awburst         (s0_axi4_awburst),              //   input,    width = 2,              .axi4_ch0_awburst
		.s0_axi4_awid            (s0_axi4_awid),                 //   input,    width = 7,              .axi4_ch0_awid
		.s0_axi4_awlen           (s0_axi4_awlen),                //   input,    width = 8,              .axi4_ch0_awlen
		.s0_axi4_awlock          (s0_axi4_awlock),               //   input,    width = 1,              .axi4_ch0_awlock
		.s0_axi4_awqos           (s0_axi4_awqos),                //   input,    width = 4,              .axi4_ch0_awqos
		.s0_axi4_awsize          (s0_axi4_awsize),               //   input,    width = 3,              .axi4_ch0_awsize
		.s0_axi4_awvalid         (s0_axi4_awvalid),              //   input,    width = 1,              .axi4_ch0_awvalid
		.s0_axi4_awuser          (s0_axi4_awuser),               //   input,   width = 14,              .axi4_ch0_awuser
		.s0_axi4_awprot          (s0_axi4_awprot),               //   input,    width = 3,              .axi4_ch0_awprot
		.s0_axi4_awready         (s0_axi4_awready),              //  output,    width = 1,              .axi4_ch0_awready
		.s0_axi4_araddr          (s0_axi4_araddr),               //   input,   width = 40,              .axi4_ch0_araddr
		.s0_axi4_arburst         (s0_axi4_arburst),              //   input,    width = 2,              .axi4_ch0_arburst
		.s0_axi4_arid            (s0_axi4_arid),                 //   input,    width = 7,              .axi4_ch0_arid
		.s0_axi4_arlen           (s0_axi4_arlen),                //   input,    width = 8,              .axi4_ch0_arlen
		.s0_axi4_arlock          (s0_axi4_arlock),               //   input,    width = 1,              .axi4_ch0_arlock
		.s0_axi4_arqos           (s0_axi4_arqos),                //   input,    width = 4,              .axi4_ch0_arqos
		.s0_axi4_arsize          (s0_axi4_arsize),               //   input,    width = 3,              .axi4_ch0_arsize
		.s0_axi4_arvalid         (s0_axi4_arvalid),              //   input,    width = 1,              .axi4_ch0_arvalid
		.s0_axi4_aruser          (s0_axi4_aruser),               //   input,   width = 14,              .axi4_ch0_aruser
		.s0_axi4_arprot          (s0_axi4_arprot),               //   input,    width = 3,              .axi4_ch0_arprot
		.s0_axi4_arready         (s0_axi4_arready),              //  output,    width = 1,              .axi4_ch0_arready
		.s0_axi4_wdata           (s0_axi4_wdata),                //   input,  width = 256,              .axi4_ch0_wdata
		.s0_axi4_wstrb           (s0_axi4_wstrb),                //   input,   width = 32,              .axi4_ch0_wstrb
		.s0_axi4_wlast           (s0_axi4_wlast),                //   input,    width = 1,              .axi4_ch0_wlast
		.s0_axi4_wvalid          (s0_axi4_wvalid),               //   input,    width = 1,              .axi4_ch0_wvalid
		.s0_axi4_wready          (s0_axi4_wready),               //  output,    width = 1,              .axi4_ch0_wready
		.s0_axi4_bready          (s0_axi4_bready),               //   input,    width = 1,              .axi4_ch0_bready
		.s0_axi4_bid             (s0_axi4_bid),                  //  output,    width = 7,              .axi4_ch0_bid
		.s0_axi4_bresp           (s0_axi4_bresp),                //  output,    width = 2,              .axi4_ch0_bresp
		.s0_axi4_bvalid          (s0_axi4_bvalid),               //  output,    width = 1,              .axi4_ch0_bvalid
		.s0_axi4_rready          (s0_axi4_rready),               //   input,    width = 1,              .axi4_ch0_rready
		.s0_axi4_rdata           (s0_axi4_rdata),                //  output,  width = 256,              .axi4_ch0_rdata
		.s0_axi4_rid             (s0_axi4_rid),                  //  output,    width = 7,              .axi4_ch0_rid
		.s0_axi4_rlast           (s0_axi4_rlast),                //  output,    width = 1,              .axi4_ch0_rlast
		.s0_axi4_rresp           (s0_axi4_rresp),                //  output,    width = 2,              .axi4_ch0_rresp
		.s0_axi4_rvalid          (s0_axi4_rvalid),               //  output,    width = 1,              .axi4_ch0_rvalid
		.noc_aclk_0              (noc_aclk_0),                   //  output,    width = 1,              .axi4_ch0_clk
		.noc_rst_n_0             (noc_rst_n_0),                  //  output,    width = 1,              .axi4_ch0_reset_n
		.s0_axi4_wuser           (s0_axi4_wuser),                //   input,   width = 32,              .axi4_ch0_wuser
		.s0_axi4_ruser           (s0_axi4_ruser),                //  output,   width = 32,              .axi4_ch0_ruser
		.mem_0_cs                (mem_0_cs),                     //  output,    width = 1,         mem_0.mem_cs
		.mem_0_ca                (mem_0_ca),                     //  output,    width = 6,              .mem_ca
		.mem_0_cke               (mem_0_cke),                    //  output,    width = 1,              .mem_cke
		.mem_0_dq                (mem_0_dq),                     //   inout,   width = 32,              .mem_dq
		.mem_0_dqs_t             (mem_0_dqs_t),                  //   inout,    width = 4,              .mem_dqs_t
		.mem_0_dqs_c             (mem_0_dqs_c),                  //   inout,    width = 4,              .mem_dqs_c
		.mem_0_dmi               (mem_0_dmi),                    //   inout,    width = 4,              .mem_dmi
		.mem_0_ck_t              (mem_0_ck_t),                   //  output,    width = 1,      mem_ck_0.mem_ck_t
		.mem_0_ck_c              (mem_0_ck_c),                   //  output,    width = 1,              .mem_ck_c
		.mem_0_reset_n           (mem_0_reset_n),                //  output,    width = 1,   mem_reset_n.mem_reset_n
		.oct_rzqin_0             (oct_rzqin_0),                  //   input,    width = 1,         oct_0.oct_rzqin
		.ref_clk                 (refclk_bridge_refclk_out_clk)  //   input,    width = 1,       ref_clk.clk
	);

	emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge refclk_bridge (
		.refclk_in       (ref_clk),                             //   input,  width = 1,       refclk_in.clk
		.refclk_out      (refclk_bridge_refclk_out_clk),        //  output,  width = 1,      refclk_out.clk
		.refclk_in_gpio  (refclk_bridge_refclk_in_gpio_export), //  output,  width = 1,  refclk_in_gpio.export
		.refclk_out_gpio (refclk_gpio_dout_export)              //   input,  width = 1, refclk_out_gpio.export
	);

	emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio refclk_gpio (
		.dout   (refclk_gpio_dout_export),             //  output,  width = 1,   dout.export
		.pad_in (refclk_bridge_refclk_in_gpio_export)  //   input,  width = 1, pad_in.export
	);

endmodule
