source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/common/riviera_files.tcl]

namespace eval emif_io96b_hps_emif_io96b_hps_420_dyxenzq {
  proc get_design_libraries {} {
    set libraries [dict create]
    set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_libraries]]
    set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_libraries]]
    set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_libraries]]
    dict set libraries emif_io96b_hps_emif_io96b_hps_420_dyxenzq 1
    return $libraries
  }
  
  proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
    set memory_files [list]
    set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_memory_files "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
    return $memory_files
  }
  
  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
    set design_files [dict create]
    set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
    set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
    set design_files [dict merge $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
    return $design_files
  }
  
  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
    set design_files [list]
    set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/" "$QUARTUS_INSTALL_DIR"]]
    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.v"]\"  -work emif_io96b_hps_emif_io96b_hps_420_dyxenzq"
    return $design_files
  }
  
  proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
    set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
    if {$IS_DUPLICATE == -1} {
      return $NEW_ELAB_OPTION
    } else {
      return ""
    }
  }
  
  
  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
    set ELAB_OPTIONS ""
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ELAB_OPTIONS
  }
  
  
  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
    set SIM_OPTIONS ""
    append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_sim_options $SIMULATOR_TOOL_BITNESS]
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $SIM_OPTIONS
  }
  
  
  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
    set ENV_VARIABLES [dict create]
    set LD_LIBRARY_PATH [dict create]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ENV_VARIABLES
  }
  
  
  proc normalize_path {FILEPATH} {
      if {[catch { package require fileutil } err]} { 
          return $FILEPATH 
      } 
      set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
      if {[file pathtype $FILEPATH] eq "relative"} { 
          set path [fileutil::relative [pwd] $path] 
      } 
      return $path 
  } 
  proc get_dpi_libraries {QSYS_SIMDIR} {
    set libraries [dict create]
    set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/sim/"]]
    set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/sim/"]]
    set libraries [dict merge $libraries [emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge::get_dpi_libraries "$QSYS_SIMDIR/../../ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/sim/"]]
    
    return $libraries
  }
  
}
