// agilex_hps_intel_agilex_5_soc_1300_lzner2a.v

// This file was auto-generated from intel_soc_sundancemesa_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.3.1 100

`timescale 1 ps / 1 ps
module agilex_hps_intel_agilex_5_soc_1300_lzner2a (
		output wire         h2f_reset_reset,                    //                h2f_reset.reset,            Active high reset from the HPS Reset Manager.
		input  wire         hps2fpga_axi_clock_clk,             //       hps2fpga_axi_clock.clk,              Clock from a single source in the FPGA.
		input  wire         hps2fpga_axi_reset_reset,           //       hps2fpga_axi_reset.reset,            Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   hps2fpga_awid,                      //                 hps2fpga.awid,             Identification tag for a write transaction.
		output wire [37:0]  hps2fpga_awaddr,                    //                         .awaddr,           The address of the first transfer in a write transaction.
		output wire [7:0]   hps2fpga_awlen,                     //                         .awlen,            The exact number of data transfers in a write transaction.
		output wire [2:0]   hps2fpga_awsize,                    //                         .awsize,           The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   hps2fpga_awburst,                   //                         .awburst,          Indicates how address changes between each transfer in a write transaction.
		output wire         hps2fpga_awlock,                    //                         .awlock,           Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   hps2fpga_awcache,                   //                         .awcache,          Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_awprot,                    //                         .awprot,           Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         hps2fpga_awvalid,                   //                         .awvalid,          Indicates that the write address channel signals are valid.
		input  wire         hps2fpga_awready,                   //                         .awready,          Indicates that a transfer on the write address channel can be accepted.
		output wire [127:0] hps2fpga_wdata,                     //                         .wdata,            Write data.
		output wire [15:0]  hps2fpga_wstrb,                     //                         .wstrb,            Write strobes, indicate which byte lanes hold valid data.
		output wire         hps2fpga_wlast,                     //                         .wlast,            User-defined extension for the write data channel.
		output wire         hps2fpga_wvalid,                    //                         .wvalid,           Indicates that the write data channel signals are valid.
		input  wire         hps2fpga_wready,                    //                         .wready,           Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   hps2fpga_bid,                       //                         .bid,              Transaction identifier for the write response.
		input  wire [1:0]   hps2fpga_bresp,                     //                         .bresp,            Write response, indicates the status of a write transaction.
		input  wire         hps2fpga_bvalid,                    //                         .bvalid,           Indicates that the write response channel signals are valid.
		output wire         hps2fpga_bready,                    //                         .bready,           Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   hps2fpga_arid,                      //                         .arid,             Transaction identifier for the read transaction.
		output wire [37:0]  hps2fpga_araddr,                    //                         .araddr,           The address of the first transfer in a read transaction.
		output wire [7:0]   hps2fpga_arlen,                     //                         .arlen,            The exact number of data transfers in a read transaction.
		output wire [2:0]   hps2fpga_arsize,                    //                         .arsize,           The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   hps2fpga_arburst,                   //                         .arburst,          Indicates how address changes between each transfer in a read transaction.
		output wire         hps2fpga_arlock,                    //                         .arlock,           Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   hps2fpga_arcache,                   //                         .arcache,          Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_arprot,                    //                         .arprot,           Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         hps2fpga_arvalid,                   //                         .arvalid,          Indicates that the read address channel signals are valid.
		input  wire         hps2fpga_arready,                   //                         .arready,          Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   hps2fpga_rid,                       //                         .rid,              Identification tag for read data and response.
		input  wire [127:0] hps2fpga_rdata,                     //                         .rdata,            Read data.
		input  wire [1:0]   hps2fpga_rresp,                     //                         .rresp,            Read response, indicates the status of a read transfer.
		input  wire         hps2fpga_rlast,                     //                         .rlast,            Indicates whether this is the last data transfer in a read transaction.
		input  wire         hps2fpga_rvalid,                    //                         .rvalid,           Indicates that the read data channel signals are valid.
		output wire         hps2fpga_rready,                    //                         .rready,           Indicates that a transfer on the read data channel can be accepted.
		input  wire         lwhps2fpga_axi_clock_clk,           //     lwhps2fpga_axi_clock.clk,              clock from a single source in the FPGA.
		input  wire         lwhps2fpga_axi_reset_reset,         //     lwhps2fpga_axi_reset.reset,            Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   lwhps2fpga_awid,                    //               lwhps2fpga.awid,             Identification tag for a write transaction.
		output wire [28:0]  lwhps2fpga_awaddr,                  //                         .awaddr,           The address of the first transfer in a write transaction.
		output wire [7:0]   lwhps2fpga_awlen,                   //                         .awlen,            The exact number of data transfers in a write transaction.
		output wire [2:0]   lwhps2fpga_awsize,                  //                         .awsize,           The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   lwhps2fpga_awburst,                 //                         .awburst,          Indicates how address changes between each transfer in a write transaction.
		output wire         lwhps2fpga_awlock,                  //                         .awlock,           Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   lwhps2fpga_awcache,                 //                         .awcache,          Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_awprot,                  //                         .awprot,           Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_awvalid,                 //                         .awvalid,          Indicates that the write address channel signals are valid.
		input  wire         lwhps2fpga_awready,                 //                         .awready,          Indicates that a transfer on the write address channel can be accepted.
		output wire [31:0]  lwhps2fpga_wdata,                   //                         .wdata,            Write data.
		output wire [3:0]   lwhps2fpga_wstrb,                   //                         .wstrb,            Write strobes, indicate which byte lanes hold valid data.
		output wire         lwhps2fpga_wlast,                   //                         .wlast,            User-defined extension for the write data channel.
		output wire         lwhps2fpga_wvalid,                  //                         .wvalid,           Indicates that the write data channel signals are valid.
		input  wire         lwhps2fpga_wready,                  //                         .wready,           Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   lwhps2fpga_bid,                     //                         .bid,              Transaction identifier for the write response.
		input  wire [1:0]   lwhps2fpga_bresp,                   //                         .bresp,            Write response, indicates the status of a write transaction.
		input  wire         lwhps2fpga_bvalid,                  //                         .bvalid,           Indicates that the write response channel signals are valid.
		output wire         lwhps2fpga_bready,                  //                         .bready,           Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   lwhps2fpga_arid,                    //                         .arid,             Transaction identifier for the read transaction.
		output wire [28:0]  lwhps2fpga_araddr,                  //                         .araddr,           The address of the first transfer in a read transaction.
		output wire [7:0]   lwhps2fpga_arlen,                   //                         .arlen,            The exact number of data transfers in a read transaction.
		output wire [2:0]   lwhps2fpga_arsize,                  //                         .arsize,           The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   lwhps2fpga_arburst,                 //                         .arburst,          Indicates how address changes between each transfer in a read transaction.
		output wire         lwhps2fpga_arlock,                  //                         .arlock,           Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   lwhps2fpga_arcache,                 //                         .arcache,          Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_arprot,                  //                         .arprot,           Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_arvalid,                 //                         .arvalid,          Indicates that the read address channel signals are valid.
		input  wire         lwhps2fpga_arready,                 //                         .arready,          Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   lwhps2fpga_rid,                     //                         .rid,              Identification tag for read data and response.
		input  wire [31:0]  lwhps2fpga_rdata,                   //                         .rdata,            Read data.
		input  wire [1:0]   lwhps2fpga_rresp,                   //                         .rresp,            Read response, indicates the status of a read transfer.
		input  wire         lwhps2fpga_rlast,                   //                         .rlast,            Indicates whether this is the last data transfer in a read transaction.
		input  wire         lwhps2fpga_rvalid,                  //                         .rvalid,           Indicates that the read data channel signals are valid.
		output wire         lwhps2fpga_rready,                  //                         .rready,           Indicates that a transfer on the read data channel can be accepted.
		output wire         emac0_app_rst_reset_n,              //            emac0_app_rst.reset_n,          EMAC0 application clock reset output.
		output wire         h2f_warm_reset_handshake_reset_req, // h2f_warm_reset_handshake.reset_req,        HPS warm reset request. Identical to watchdog reset except this is asserted by SDM.
		input  wire         h2f_warm_reset_handshake_reset_ack, //                         .reset_ack,        HPS warm reset acknowledge response to SDM. Should be asserted when all HPS soft logic is successfully in reset.
		input  wire         hps_io_hps_osc_clk,                 //                   hps_io.hps_osc_clk,      HPS input clock pin for EOSC reference clock.
		inout  wire         hps_io_sdmmc_data0,                 //                         .sdmmc_data0,      SDMMC data[0].
		inout  wire         hps_io_sdmmc_data1,                 //                         .sdmmc_data1,      SDMMC data[1].
		output wire         hps_io_sdmmc_cclk,                  //                         .sdmmc_cclk,       SDMMC output clock.
		inout  wire         hps_io_sdmmc_data2,                 //                         .sdmmc_data2,      SDMMC data[2].
		inout  wire         hps_io_sdmmc_data3,                 //                         .sdmmc_data3,      SDMMC data[3].
		inout  wire         hps_io_sdmmc_cmd,                   //                         .sdmmc_cmd,        SDMMC command.
		input  wire         hps_io_usb0_clk,                    //                         .usb0_clk,         ULPI PHY clock input.
		output wire         hps_io_usb0_stp,                    //                         .usb0_stp,         ULPI stop output control.
		input  wire         hps_io_usb0_dir,                    //                         .usb0_dir,         Data bus control.
		inout  wire         hps_io_usb0_data0,                  //                         .usb0_data0,       USB data[0].
		inout  wire         hps_io_usb0_data1,                  //                         .usb0_data1,       USB data[1].
		input  wire         hps_io_usb0_nxt,                    //                         .usb0_nxt,         ULPI next data control.
		inout  wire         hps_io_usb0_data2,                  //                         .usb0_data2,       USB data[2].
		inout  wire         hps_io_usb0_data3,                  //                         .usb0_data3,       USB data[3].
		inout  wire         hps_io_usb0_data4,                  //                         .usb0_data4,       USB data[4].
		inout  wire         hps_io_usb0_data5,                  //                         .usb0_data5,       USB data[5].
		inout  wire         hps_io_usb0_data6,                  //                         .usb0_data6,       USB data[6].
		inout  wire         hps_io_usb0_data7,                  //                         .usb0_data7,       USB data[7].
		output wire         hps_io_emac0_tx_clk,                //                         .emac0_tx_clk,     EMAC0 transmit clock.
		output wire         hps_io_emac0_tx_ctl,                //                         .emac0_tx_ctl,     EMAC0 transmit data enable.
		input  wire         hps_io_emac0_rx_clk,                //                         .emac0_rx_clk,     EMAC0 receive clock.
		input  wire         hps_io_emac0_rx_ctl,                //                         .emac0_rx_ctl,     EMAC0 receive data enable.
		output wire         hps_io_emac0_txd0,                  //                         .emac0_txd0,       EMAC0 transmit data[0].
		output wire         hps_io_emac0_txd1,                  //                         .emac0_txd1,       EMAC0 transmit data[1].
		input  wire         hps_io_emac0_rxd0,                  //                         .emac0_rxd0,       EMAC0 receive data[0].
		input  wire         hps_io_emac0_rxd1,                  //                         .emac0_rxd1,       EMAC0 receive data[1].
		output wire         hps_io_emac0_txd2,                  //                         .emac0_txd2,       EMAC0 transmit data[2].
		output wire         hps_io_emac0_txd3,                  //                         .emac0_txd3,       EMAC0 transmit data[3].
		input  wire         hps_io_emac0_rxd2,                  //                         .emac0_rxd2,       EMAC0 receive data[2].
		input  wire         hps_io_emac0_rxd3,                  //                         .emac0_rxd3,       EMAC0 receive data[3].
		inout  wire         hps_io_mdio0_mdio,                  //                         .mdio0_mdio,       EMAC0 MDIO data.
		output wire         hps_io_mdio0_mdc,                   //                         .mdio0_mdc,        EMAC0 MDIO clock.
		output wire         hps_io_uart1_tx,                    //                         .uart1_tx,         UART1 transmit data.
		input  wire         hps_io_uart1_rx,                    //                         .uart1_rx,         UART1 receive data.
		inout  wire         hps_io_i2c1_sda,                    //                         .i2c1_sda,         I2C1 serial data.
		inout  wire         hps_io_i2c1_scl,                    //                         .i2c1_scl,         I2C1 clock.
		inout  wire         hps_io_gpio28,                      //                         .gpio28,           GPIO1 IO4
		inout  wire         hps_io_gpio34,                      //                         .gpio34,           GPIO1 IO10
		inout  wire         hps_io_gpio40,                      //                         .gpio40,           GPIO1 IO16
		inout  wire         hps_io_gpio41,                      //                         .gpio41,           GPIO1 IO17
		input  wire [31:0]  fpga2hps_interrupt_irq1_irq,        //  fpga2hps_interrupt_irq1.irq,              FPGA-to-HPS interrupts (higher 32 bits).
		input  wire [31:0]  fpga2hps_interrupt_irq0_irq,        //  fpga2hps_interrupt_irq0.irq,              FPGA-to-HPS interrupts (lower 32 bits).
		input  wire         f2sdram_axi_clock_clk,              //        f2sdram_axi_clock.clk,              Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         f2sdram_axi_reset_reset,            //        f2sdram_axi_reset.reset,            Active high reset for f2sdram soft logic on FPGA. The actual bridge reset is driven by internal HPS Reset Manager.
		input  wire [31:0]  f2sdram_araddr,                     //                  f2sdram.araddr,           Address of the first transfer in a read transaction.
		input  wire [1:0]   f2sdram_arburst,                    //                         .arburst,          Burst type indicating how address changes between each transfer in a read transaction.
		input  wire [3:0]   f2sdram_arcache,                    //                         .arcache,          Indicates how a read transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_arid,                       //                         .arid,             Identification tag for a read transaction.
		input  wire [7:0]   f2sdram_arlen,                      //                         .arlen,            The exact number of data transfers in a read transaction.
		input  wire         f2sdram_arlock,                     //                         .arlock,           Provides info on atomic characteristics of a read transaction.
		input  wire [2:0]   f2sdram_arprot,                     //                         .arprot,           Protection attributes of a read transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_arqos,                      //                         .arqos,            Quality service identifier for a read transaction.
		output wire         f2sdram_arready,                    //                         .arready,          Indicates that a transfer on the read address channel can be accepted.
		input  wire [2:0]   f2sdram_arsize,                     //                         .arsize,           The number of bytes in each data transfer of a read transaction.
		input  wire         f2sdram_arvalid,                    //                         .arvalid,          Indicates the read address channel signals are valid.
		input  wire [31:0]  f2sdram_awaddr,                     //                         .awaddr,           The address of the first transfer in a write transaction.
		input  wire [1:0]   f2sdram_awburst,                    //                         .awburst,          Burst type indicating how address changes between each transfer in a write transaction.
		input  wire [3:0]   f2sdram_awcache,                    //                         .awcache,          Indicates how a write transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_awid,                       //                         .awid,             Identification tag for a write transaction.
		input  wire [7:0]   f2sdram_awlen,                      //                         .awlen,            The exact number of data transfers in a write transaction.
		input  wire         f2sdram_awlock,                     //                         .awlock,           Provides info on atomic characteristics of a write transaction.
		input  wire [2:0]   f2sdram_awprot,                     //                         .awprot,           Protection attributes of a write transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_awqos,                      //                         .awqos,            Quality of servide identifier for a write transaction.
		output wire         f2sdram_awready,                    //                         .awready,          Indicates that a transfer on the write channel address can be accepted.
		input  wire [2:0]   f2sdram_awsize,                     //                         .awsize,           The number of bytes in each data transfer of a write transaction.
		input  wire         f2sdram_awvalid,                    //                         .awvalid,          Indicates the write address channel signals are valid.
		output wire [4:0]   f2sdram_bid,                        //                         .bid,              Identification tag for a write response.
		input  wire         f2sdram_bready,                     //                         .bready,           Indicates that a transfer on the write response channel can be accepted.
		output wire [1:0]   f2sdram_bresp,                      //                         .bresp,            Write response indicating the status of a write transaction.
		output wire         f2sdram_bvalid,                     //                         .bvalid,           Indicates that the write response channel signals are valid.
		output wire [255:0] f2sdram_rdata,                      //                         .rdata,            Read data.
		output wire [4:0]   f2sdram_rid,                        //                         .rid,              Identification tag for read data and response.
		output wire         f2sdram_rlast,                      //                         .rlast,            Indicates the last data transfer in a read transaction.
		input  wire         f2sdram_rready,                     //                         .rready,           Indicates a transfer on the read data channel can be accepted.
		output wire [1:0]   f2sdram_rresp,                      //                         .rresp,            Read response indicating the status of a read transfer.
		output wire         f2sdram_rvalid,                     //                         .rvalid,           Indicates the read channel data channel signals are valid.
		input  wire [255:0] f2sdram_wdata,                      //                         .wdata,            Write data.
		input  wire         f2sdram_wlast,                      //                         .wlast,            Indicates the last data transfer in a write transaction.
		output wire         f2sdram_wready,                     //                         .wready,           Indicates a transfer on the write data channel can be accepted.
		input  wire [31:0]  f2sdram_wstrb,                      //                         .wstrb,            Write strobes indicating which bye lanes hold valid data.
		input  wire         f2sdram_wvalid,                     //                         .wvalid,           Indicates the write channel data signals are valid.
		input  wire [7:0]   f2sdram_aruser,                     //                         .aruser,           Extension for the read address channel.
		input  wire [7:0]   f2sdram_awuser,                     //                         .awuser,           Extension for the write address channel.
		input  wire [7:0]   f2sdram_wuser,                      //                         .wuser,            Extension for the write data channel.
		output wire [7:0]   f2sdram_buser,                      //                         .buser,            Extension for the write response channel.
		input  wire [3:0]   f2sdram_arregion,                   //                         .arregion,         Region indicator for a read transaction.
		output wire [7:0]   f2sdram_ruser,                      //                         .ruser,            Extension for the read data channel.
		input  wire [3:0]   f2sdram_awregion,                   //                         .awregion,         Region indicator for a write transaction.
		input  wire         io96b0_to_hps_ch0_axil_clk,         //            io96b0_to_hps.ch0_axil_clk,     Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_to_hps_ch0_axil_reset_n,     //                         .ch0_axil_reset_n, Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_to_hps_ch0_axil_arready,     //                         .ch0_axil_arready, Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_to_hps_ch0_axil_awready,     //                         .ch0_axil_awready, Indicates a transfer on the write address channel can be accepted.
		input  wire [1:0]   io96b0_to_hps_ch0_axil_bresp,       //                         .ch0_axil_bresp,   Indicates status of write transaction.
		input  wire         io96b0_to_hps_ch0_axil_bvalid,      //                         .ch0_axil_bvalid,  Indicates write response channel signals are valid.
		input  wire [31:0]  io96b0_to_hps_ch0_axil_rdata,       //                         .ch0_axil_rdata,   Read data.
		input  wire [1:0]   io96b0_to_hps_ch0_axil_rresp,       //                         .ch0_axil_rresp,   Indicates status of read transaction.
		input  wire         io96b0_to_hps_ch0_axil_rvalid,      //                         .ch0_axil_rvalid,  Indicates read data channel signals are valid.
		input  wire         io96b0_to_hps_ch0_axil_wready,      //                         .ch0_axil_wready,  Indicates a transfer on the write data channel can be accepted.
		output wire [26:0]  io96b0_to_hps_ch0_axil_araddr,      //                         .ch0_axil_araddr,  The address of the first transfer in a read transaction.
		output wire         io96b0_to_hps_ch0_axil_arvalid,     //                         .ch0_axil_arvalid, Indicates read address channel signals are valid.
		output wire [26:0]  io96b0_to_hps_ch0_axil_awaddr,      //                         .ch0_axil_awaddr,  The address of the first transfer in a write transaction.
		output wire         io96b0_to_hps_ch0_axil_awvalid,     //                         .ch0_axil_awvalid, Indicates write address channel signals are valid.
		output wire         io96b0_to_hps_ch0_axil_bready,      //                         .ch0_axil_bready,  Indicates a transfer on the write response channel can be accepted.
		output wire         io96b0_to_hps_ch0_axil_rready,      //                         .ch0_axil_rready,  Indicates a transfer on the read data channel can be accepted.
		output wire [31:0]  io96b0_to_hps_ch0_axil_wdata,       //                         .ch0_axil_wdata,   Write data.
		output wire [3:0]   io96b0_to_hps_ch0_axil_wstrb,       //                         .ch0_axil_wstrb,   Write strobes indicating which bye lanes hold valid data.
		output wire         io96b0_to_hps_ch0_axil_wvalid,      //                         .ch0_axil_wvalid,  Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_to_hps_ch0_axil_arprot,      //                         .ch0_axil_arprot,  Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_to_hps_ch0_axil_awprot,      //                         .ch0_axil_awprot,  Placegolder AWPROT. Protection attributes not supported for this bridge.
		input  wire         io96b0_to_hps_axi4_ch0_clk,         //                         .axi4_ch0_clk,     Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_to_hps_axi4_ch0_reset_n,     //                         .axi4_ch0_reset_n, Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_to_hps_axi4_ch0_arready,     //                         .axi4_ch0_arready, Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_to_hps_axi4_ch0_awready,     //                         .axi4_ch0_awready, Indicates a transfer on the write address channel can be accepted.
		input  wire [6:0]   io96b0_to_hps_axi4_ch0_bid,         //                         .axi4_ch0_bid,     Identification tag for a write response.
		input  wire [1:0]   io96b0_to_hps_axi4_ch0_bresp,       //                         .axi4_ch0_bresp,   Indicates the status of a write transaction.
		input  wire         io96b0_to_hps_axi4_ch0_bvalid,      //                         .axi4_ch0_bvalid,  Indicates write response channel signals are valid.
		input  wire [255:0] io96b0_to_hps_axi4_ch0_rdata,       //                         .axi4_ch0_rdata,   Read data.
		input  wire [6:0]   io96b0_to_hps_axi4_ch0_rid,         //                         .axi4_ch0_rid,     Identification tag for read data and response.
		input  wire         io96b0_to_hps_axi4_ch0_rlast,       //                         .axi4_ch0_rlast,   Indicates the last data transfer in a read transaction.
		input  wire [1:0]   io96b0_to_hps_axi4_ch0_rresp,       //                         .axi4_ch0_rresp,   Indicates the status of a read transfer.
		input  wire [31:0]  io96b0_to_hps_axi4_ch0_ruser,       //                         .axi4_ch0_ruser,   Extension of read data channel.
		input  wire         io96b0_to_hps_axi4_ch0_rvalid,      //                         .axi4_ch0_rvalid,  Indicates read data channel signals are valid.
		input  wire         io96b0_to_hps_axi4_ch0_wready,      //                         .axi4_ch0_wready,  Indicates a transfer on the write data channel can be accepted.
		output wire [39:0]  io96b0_to_hps_axi4_ch0_araddr,      //                         .axi4_ch0_araddr,  The address of the first transfer in a read transaction.
		output wire [1:0]   io96b0_to_hps_axi4_ch0_arburst,     //                         .axi4_ch0_arburst, Burst type indicating how address changes between each transfer in a read transaction.
		output wire [6:0]   io96b0_to_hps_axi4_ch0_arid,        //                         .axi4_ch0_arid,    Identification tag for a read transaction.
		output wire [7:0]   io96b0_to_hps_axi4_ch0_arlen,       //                         .axi4_ch0_arlen,   Exact number of data transfers in a read transaction.
		output wire         io96b0_to_hps_axi4_ch0_arlock,      //                         .axi4_ch0_arlock,  Provides info on atomic characteristics of a read transaction.
		output wire [3:0]   io96b0_to_hps_axi4_ch0_arqos,       //                         .axi4_ch0_arqos,   Quality of service identifier for a read transaction.
		output wire [2:0]   io96b0_to_hps_axi4_ch0_arsize,      //                         .axi4_ch0_arsize,  The number of bytes in each data transfer in a read transaction.
		output wire [13:0]  io96b0_to_hps_axi4_ch0_aruser,      //                         .axi4_ch0_aruser,  Extension of read address channel.
		output wire         io96b0_to_hps_axi4_ch0_arvalid,     //                         .axi4_ch0_arvalid, Indicates read address channel signals are valid.
		output wire [39:0]  io96b0_to_hps_axi4_ch0_awaddr,      //                         .axi4_ch0_awaddr,  The address of the first transfer in a write transaction.
		output wire [1:0]   io96b0_to_hps_axi4_ch0_awburst,     //                         .axi4_ch0_awburst, Burst type indicating how address changes between each transfer in a write transaction.
		output wire [6:0]   io96b0_to_hps_axi4_ch0_awid,        //                         .axi4_ch0_awid,    Identification tag for a write transaction.
		output wire [7:0]   io96b0_to_hps_axi4_ch0_awlen,       //                         .axi4_ch0_awlen,   Exact number of data transfers in a write transaction.
		output wire         io96b0_to_hps_axi4_ch0_awlock,      //                         .axi4_ch0_awlock,  Provides info on atomic characteristics of a write transaction.
		output wire [3:0]   io96b0_to_hps_axi4_ch0_awqos,       //                         .axi4_ch0_awqos,   Quality of service identifier for a write transaction.
		output wire [2:0]   io96b0_to_hps_axi4_ch0_awsize,      //                         .axi4_ch0_awsize,  Number of bytes in each data transfer in a write transaction.
		output wire [13:0]  io96b0_to_hps_axi4_ch0_awuser,      //                         .axi4_ch0_awuser,  Extension of write address channel.
		output wire         io96b0_to_hps_axi4_ch0_awvalid,     //                         .axi4_ch0_awvalid, Indicates write address channel signals are valid.
		output wire         io96b0_to_hps_axi4_ch0_bready,      //                         .axi4_ch0_bready,  Indicates a transfer on write response channel can be accepted.
		output wire         io96b0_to_hps_axi4_ch0_rready,      //                         .axi4_ch0_rready,  Indicates a transfer on read data channel can be accepted.
		output wire [255:0] io96b0_to_hps_axi4_ch0_wdata,       //                         .axi4_ch0_wdata,   Write data.
		output wire         io96b0_to_hps_axi4_ch0_wlast,       //                         .axi4_ch0_wlast,   Indicates the last data transfer in a write transaction.
		output wire [31:0]  io96b0_to_hps_axi4_ch0_wstrb,       //                         .axi4_ch0_wstrb,   Write strobes indicating which byte lanes hold valid data.
		output wire [31:0]  io96b0_to_hps_axi4_ch0_wuser,       //                         .axi4_ch0_wuser,   Extension of the write data channel.
		output wire         io96b0_to_hps_axi4_ch0_wvalid,      //                         .axi4_ch0_wvalid,  Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_to_hps_axi4_ch0_arprot,      //                         .axi4_ch0_arprot,  Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_to_hps_axi4_ch0_awprot       //                         .axi4_ch0_awprot,  Placeholder AWPROT. Protection attributes not supported for this bridge.
	);

	wire    [1:0] sm_hps_hps_dmi0_interconnect_awburst;   // sm_hps:hps2mpfe_dmi0_awburst -> sm_mpfe:hps2mpfe_dmi0_awburst
	wire    [7:0] sm_hps_hps_dmi0_interconnect_arlen;     // sm_hps:hps2mpfe_dmi0_arlen -> sm_mpfe:hps2mpfe_dmi0_arlen
	wire    [3:0] sm_hps_hps_dmi0_interconnect_arqos;     // sm_hps:hps2mpfe_dmi0_arqos -> sm_mpfe:hps2mpfe_dmi0_arqos
	wire    [7:0] sm_hps_hps_dmi0_interconnect_awuser;    // sm_hps:hps2mpfe_dmi0_awuser -> sm_mpfe:hps2mpfe_dmi0_awuser
	wire          sm_hps_hps_dmi0_interconnect_wready;    // sm_mpfe:hps2mpfe_dmi0_wready -> sm_hps:hps2mpfe_dmi0_wready
	wire   [31:0] sm_hps_hps_dmi0_interconnect_wstrb;     // sm_hps:hps2mpfe_dmi0_wstrb -> sm_mpfe:hps2mpfe_dmi0_wstrb
	wire    [9:0] sm_hps_hps_dmi0_interconnect_rid;       // sm_mpfe:hps2mpfe_dmi0_rid -> sm_hps:hps2mpfe_dmi0_rid
	wire          sm_hps_hps_dmi0_interconnect_rready;    // sm_hps:hps2mpfe_dmi0_rready -> sm_mpfe:hps2mpfe_dmi0_rready
	wire    [7:0] sm_hps_hps_dmi0_interconnect_awlen;     // sm_hps:hps2mpfe_dmi0_awlen -> sm_mpfe:hps2mpfe_dmi0_awlen
	wire    [3:0] sm_hps_hps_dmi0_interconnect_awqos;     // sm_hps:hps2mpfe_dmi0_awqos -> sm_mpfe:hps2mpfe_dmi0_awqos
	wire    [3:0] sm_hps_hps_dmi0_interconnect_arcache;   // sm_hps:hps2mpfe_dmi0_arcache -> sm_mpfe:hps2mpfe_dmi0_arcache
	wire   [43:0] sm_hps_hps_dmi0_interconnect_araddr;    // sm_hps:hps2mpfe_dmi0_araddr -> sm_mpfe:hps2mpfe_dmi0_araddr
	wire          sm_hps_hps_dmi0_interconnect_wvalid;    // sm_hps:hps2mpfe_dmi0_wvalid -> sm_mpfe:hps2mpfe_dmi0_wvalid
	wire    [2:0] sm_hps_hps_dmi0_interconnect_arprot;    // sm_hps:hps2mpfe_dmi0_arprot -> sm_mpfe:hps2mpfe_dmi0_arprot
	wire          sm_hps_hps_dmi0_interconnect_arvalid;   // sm_hps:hps2mpfe_dmi0_arvalid -> sm_mpfe:hps2mpfe_dmi0_arvalid
	wire    [2:0] sm_hps_hps_dmi0_interconnect_awprot;    // sm_hps:hps2mpfe_dmi0_awprot -> sm_mpfe:hps2mpfe_dmi0_awprot
	wire  [255:0] sm_hps_hps_dmi0_interconnect_wdata;     // sm_hps:hps2mpfe_dmi0_wdata -> sm_mpfe:hps2mpfe_dmi0_wdata
	wire    [9:0] sm_hps_hps_dmi0_interconnect_arid;      // sm_hps:hps2mpfe_dmi0_arid -> sm_mpfe:hps2mpfe_dmi0_arid
	wire    [3:0] sm_hps_hps_dmi0_interconnect_awcache;   // sm_hps:hps2mpfe_dmi0_awcache -> sm_mpfe:hps2mpfe_dmi0_awcache
	wire          sm_hps_hps_dmi0_interconnect_arlock;    // sm_hps:hps2mpfe_dmi0_arlock -> sm_mpfe:hps2mpfe_dmi0_arlock
	wire          sm_hps_hps_dmi0_interconnect_awlock;    // sm_hps:hps2mpfe_dmi0_awlock -> sm_mpfe:hps2mpfe_dmi0_awlock
	wire   [43:0] sm_hps_hps_dmi0_interconnect_awaddr;    // sm_hps:hps2mpfe_dmi0_awaddr -> sm_mpfe:hps2mpfe_dmi0_awaddr
	wire          sm_hps_hps_dmi0_interconnect_arready;   // sm_mpfe:hps2mpfe_dmi0_arready -> sm_hps:hps2mpfe_dmi0_arready
	wire    [1:0] sm_hps_hps_dmi0_interconnect_bresp;     // sm_mpfe:hps2mpfe_dmi0_bresp -> sm_hps:hps2mpfe_dmi0_bresp
	wire  [255:0] sm_hps_hps_dmi0_interconnect_rdata;     // sm_mpfe:hps2mpfe_dmi0_rdata -> sm_hps:hps2mpfe_dmi0_rdata
	wire    [1:0] sm_hps_hps_dmi0_interconnect_arburst;   // sm_hps:hps2mpfe_dmi0_arburst -> sm_mpfe:hps2mpfe_dmi0_arburst
	wire          sm_hps_hps_dmi0_interconnect_awready;   // sm_mpfe:hps2mpfe_dmi0_awready -> sm_hps:hps2mpfe_dmi0_awready
	wire    [2:0] sm_hps_hps_dmi0_interconnect_arsize;    // sm_hps:hps2mpfe_dmi0_arsize -> sm_mpfe:hps2mpfe_dmi0_arsize
	wire          sm_hps_hps_dmi0_interconnect_bready;    // sm_hps:hps2mpfe_dmi0_bready -> sm_mpfe:hps2mpfe_dmi0_bready
	wire          sm_hps_hps_dmi0_interconnect_rlast;     // sm_mpfe:hps2mpfe_dmi0_rlast -> sm_hps:hps2mpfe_dmi0_rlast
	wire          sm_hps_hps_dmi0_interconnect_wlast;     // sm_hps:hps2mpfe_dmi0_wlast -> sm_mpfe:hps2mpfe_dmi0_wlast
	wire    [1:0] sm_hps_hps_dmi0_interconnect_rresp;     // sm_mpfe:hps2mpfe_dmi0_rresp -> sm_hps:hps2mpfe_dmi0_rresp
	wire    [9:0] sm_hps_hps_dmi0_interconnect_awid;      // sm_hps:hps2mpfe_dmi0_awid -> sm_mpfe:hps2mpfe_dmi0_awid
	wire    [9:0] sm_hps_hps_dmi0_interconnect_bid;       // sm_mpfe:hps2mpfe_dmi0_bid -> sm_hps:hps2mpfe_dmi0_bid
	wire          sm_hps_hps_dmi0_interconnect_bvalid;    // sm_mpfe:hps2mpfe_dmi0_bvalid -> sm_hps:hps2mpfe_dmi0_bvalid
	wire    [7:0] sm_hps_hps_dmi0_interconnect_aruser;    // sm_hps:hps2mpfe_dmi0_aruser -> sm_mpfe:hps2mpfe_dmi0_aruser
	wire    [2:0] sm_hps_hps_dmi0_interconnect_awsize;    // sm_hps:hps2mpfe_dmi0_awsize -> sm_mpfe:hps2mpfe_dmi0_awsize
	wire          sm_hps_hps_dmi0_interconnect_awvalid;   // sm_hps:hps2mpfe_dmi0_awvalid -> sm_mpfe:hps2mpfe_dmi0_awvalid
	wire          sm_hps_hps_dmi0_interconnect_rvalid;    // sm_mpfe:hps2mpfe_dmi0_rvalid -> sm_hps:hps2mpfe_dmi0_rvalid
	wire    [1:0] sm_hps_hps_dmi1_interconnect_awburst;   // sm_hps:hps2mpfe_dmi1_awburst -> sm_mpfe:hps2mpfe_dmi1_awburst
	wire    [7:0] sm_hps_hps_dmi1_interconnect_arlen;     // sm_hps:hps2mpfe_dmi1_arlen -> sm_mpfe:hps2mpfe_dmi1_arlen
	wire    [3:0] sm_hps_hps_dmi1_interconnect_arqos;     // sm_hps:hps2mpfe_dmi1_arqos -> sm_mpfe:hps2mpfe_dmi1_arqos
	wire    [7:0] sm_hps_hps_dmi1_interconnect_awuser;    // sm_hps:hps2mpfe_dmi1_awuser -> sm_mpfe:hps2mpfe_dmi1_awuser
	wire          sm_hps_hps_dmi1_interconnect_wready;    // sm_mpfe:hps2mpfe_dmi1_wready -> sm_hps:hps2mpfe_dmi1_wready
	wire   [31:0] sm_hps_hps_dmi1_interconnect_wstrb;     // sm_hps:hps2mpfe_dmi1_wstrb -> sm_mpfe:hps2mpfe_dmi1_wstrb
	wire    [9:0] sm_hps_hps_dmi1_interconnect_rid;       // sm_mpfe:hps2mpfe_dmi1_rid -> sm_hps:hps2mpfe_dmi1_rid
	wire          sm_hps_hps_dmi1_interconnect_rready;    // sm_hps:hps2mpfe_dmi1_rready -> sm_mpfe:hps2mpfe_dmi1_rready
	wire    [7:0] sm_hps_hps_dmi1_interconnect_awlen;     // sm_hps:hps2mpfe_dmi1_awlen -> sm_mpfe:hps2mpfe_dmi1_awlen
	wire    [3:0] sm_hps_hps_dmi1_interconnect_awqos;     // sm_hps:hps2mpfe_dmi1_awqos -> sm_mpfe:hps2mpfe_dmi1_awqos
	wire    [3:0] sm_hps_hps_dmi1_interconnect_arcache;   // sm_hps:hps2mpfe_dmi1_arcache -> sm_mpfe:hps2mpfe_dmi1_arcache
	wire   [43:0] sm_hps_hps_dmi1_interconnect_araddr;    // sm_hps:hps2mpfe_dmi1_araddr -> sm_mpfe:hps2mpfe_dmi1_araddr
	wire          sm_hps_hps_dmi1_interconnect_wvalid;    // sm_hps:hps2mpfe_dmi1_wvalid -> sm_mpfe:hps2mpfe_dmi1_wvalid
	wire    [2:0] sm_hps_hps_dmi1_interconnect_arprot;    // sm_hps:hps2mpfe_dmi1_arprot -> sm_mpfe:hps2mpfe_dmi1_arprot
	wire          sm_hps_hps_dmi1_interconnect_arvalid;   // sm_hps:hps2mpfe_dmi1_arvalid -> sm_mpfe:hps2mpfe_dmi1_arvalid
	wire    [2:0] sm_hps_hps_dmi1_interconnect_awprot;    // sm_hps:hps2mpfe_dmi1_awprot -> sm_mpfe:hps2mpfe_dmi1_awprot
	wire  [255:0] sm_hps_hps_dmi1_interconnect_wdata;     // sm_hps:hps2mpfe_dmi1_wdata -> sm_mpfe:hps2mpfe_dmi1_wdata
	wire    [9:0] sm_hps_hps_dmi1_interconnect_arid;      // sm_hps:hps2mpfe_dmi1_arid -> sm_mpfe:hps2mpfe_dmi1_arid
	wire    [3:0] sm_hps_hps_dmi1_interconnect_awcache;   // sm_hps:hps2mpfe_dmi1_awcache -> sm_mpfe:hps2mpfe_dmi1_awcache
	wire          sm_hps_hps_dmi1_interconnect_arlock;    // sm_hps:hps2mpfe_dmi1_arlock -> sm_mpfe:hps2mpfe_dmi1_arlock
	wire          sm_hps_hps_dmi1_interconnect_awlock;    // sm_hps:hps2mpfe_dmi1_awlock -> sm_mpfe:hps2mpfe_dmi1_awlock
	wire   [43:0] sm_hps_hps_dmi1_interconnect_awaddr;    // sm_hps:hps2mpfe_dmi1_awaddr -> sm_mpfe:hps2mpfe_dmi1_awaddr
	wire          sm_hps_hps_dmi1_interconnect_arready;   // sm_mpfe:hps2mpfe_dmi1_arready -> sm_hps:hps2mpfe_dmi1_arready
	wire    [1:0] sm_hps_hps_dmi1_interconnect_bresp;     // sm_mpfe:hps2mpfe_dmi1_bresp -> sm_hps:hps2mpfe_dmi1_bresp
	wire  [255:0] sm_hps_hps_dmi1_interconnect_rdata;     // sm_mpfe:hps2mpfe_dmi1_rdata -> sm_hps:hps2mpfe_dmi1_rdata
	wire    [1:0] sm_hps_hps_dmi1_interconnect_arburst;   // sm_hps:hps2mpfe_dmi1_arburst -> sm_mpfe:hps2mpfe_dmi1_arburst
	wire          sm_hps_hps_dmi1_interconnect_awready;   // sm_mpfe:hps2mpfe_dmi1_awready -> sm_hps:hps2mpfe_dmi1_awready
	wire    [2:0] sm_hps_hps_dmi1_interconnect_arsize;    // sm_hps:hps2mpfe_dmi1_arsize -> sm_mpfe:hps2mpfe_dmi1_arsize
	wire          sm_hps_hps_dmi1_interconnect_bready;    // sm_hps:hps2mpfe_dmi1_bready -> sm_mpfe:hps2mpfe_dmi1_bready
	wire          sm_hps_hps_dmi1_interconnect_rlast;     // sm_mpfe:hps2mpfe_dmi1_rlast -> sm_hps:hps2mpfe_dmi1_rlast
	wire          sm_hps_hps_dmi1_interconnect_wlast;     // sm_hps:hps2mpfe_dmi1_wlast -> sm_mpfe:hps2mpfe_dmi1_wlast
	wire    [1:0] sm_hps_hps_dmi1_interconnect_rresp;     // sm_mpfe:hps2mpfe_dmi1_rresp -> sm_hps:hps2mpfe_dmi1_rresp
	wire    [9:0] sm_hps_hps_dmi1_interconnect_awid;      // sm_hps:hps2mpfe_dmi1_awid -> sm_mpfe:hps2mpfe_dmi1_awid
	wire    [9:0] sm_hps_hps_dmi1_interconnect_bid;       // sm_mpfe:hps2mpfe_dmi1_bid -> sm_hps:hps2mpfe_dmi1_bid
	wire          sm_hps_hps_dmi1_interconnect_bvalid;    // sm_mpfe:hps2mpfe_dmi1_bvalid -> sm_hps:hps2mpfe_dmi1_bvalid
	wire    [7:0] sm_hps_hps_dmi1_interconnect_aruser;    // sm_hps:hps2mpfe_dmi1_aruser -> sm_mpfe:hps2mpfe_dmi1_aruser
	wire    [2:0] sm_hps_hps_dmi1_interconnect_awsize;    // sm_hps:hps2mpfe_dmi1_awsize -> sm_mpfe:hps2mpfe_dmi1_awsize
	wire          sm_hps_hps_dmi1_interconnect_awvalid;   // sm_hps:hps2mpfe_dmi1_awvalid -> sm_mpfe:hps2mpfe_dmi1_awvalid
	wire          sm_hps_hps_dmi1_interconnect_rvalid;    // sm_mpfe:hps2mpfe_dmi1_rvalid -> sm_hps:hps2mpfe_dmi1_rvalid
	wire          sm_hps_hps_ccu_interconnect_clk_clk;    // sm_hps:hps2mpfe_ccu_clk -> sm_mpfe:hps2mpfe_ccu_clk
	wire          sm_hps_hps_ccu_interconnect_rst_reset;  // sm_hps:hps2mpfe_ccu_rst -> sm_mpfe:hps2mpfe_ccu_rst
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_awburst; // sm_hps:hps2mpfe_csr_awburst -> sm_mpfe:hps2mpfe_csr_awburst
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_arlen;   // sm_hps:hps2mpfe_csr_arlen -> sm_mpfe:hps2mpfe_csr_arlen
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_awuser;  // sm_hps:hps2mpfe_csr_awuser -> sm_mpfe:hps2mpfe_csr_awuser
	wire          sm_hps_hps_s2mpfe_interconnect_wready;  // sm_mpfe:hps2mpfe_csr_wready -> sm_hps:hps2mpfe_csr_wready
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_wstrb;   // sm_hps:hps2mpfe_csr_wstrb -> sm_mpfe:hps2mpfe_csr_wstrb
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_rid;     // sm_mpfe:hps2mpfe_csr_rid -> sm_hps:hps2mpfe_csr_rid
	wire          sm_hps_hps_s2mpfe_interconnect_rready;  // sm_hps:hps2mpfe_csr_rready -> sm_mpfe:hps2mpfe_csr_rready
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_awlen;   // sm_hps:hps2mpfe_csr_awlen -> sm_mpfe:hps2mpfe_csr_awlen
	wire    [3:0] sm_hps_hps_s2mpfe_interconnect_arcache; // sm_hps:hps2mpfe_csr_arcache -> sm_mpfe:hps2mpfe_csr_arcache
	wire   [43:0] sm_hps_hps_s2mpfe_interconnect_araddr;  // sm_hps:hps2mpfe_csr_araddr -> sm_mpfe:hps2mpfe_csr_araddr
	wire          sm_hps_hps_s2mpfe_interconnect_wvalid;  // sm_hps:hps2mpfe_csr_wvalid -> sm_mpfe:hps2mpfe_csr_wvalid
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_arprot;  // sm_hps:hps2mpfe_csr_arprot -> sm_mpfe:hps2mpfe_csr_arprot
	wire          sm_hps_hps_s2mpfe_interconnect_arvalid; // sm_hps:hps2mpfe_csr_arvalid -> sm_mpfe:hps2mpfe_csr_arvalid
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_awprot;  // sm_hps:hps2mpfe_csr_awprot -> sm_mpfe:hps2mpfe_csr_awprot
	wire   [63:0] sm_hps_hps_s2mpfe_interconnect_wdata;   // sm_hps:hps2mpfe_csr_wdata -> sm_mpfe:hps2mpfe_csr_wdata
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_arid;    // sm_hps:hps2mpfe_csr_arid -> sm_mpfe:hps2mpfe_csr_arid
	wire    [3:0] sm_hps_hps_s2mpfe_interconnect_awcache; // sm_hps:hps2mpfe_csr_awcache -> sm_mpfe:hps2mpfe_csr_awcache
	wire          sm_hps_hps_s2mpfe_interconnect_arlock;  // sm_hps:hps2mpfe_csr_arlock -> sm_mpfe:hps2mpfe_csr_arlock
	wire          sm_hps_hps_s2mpfe_interconnect_awlock;  // sm_hps:hps2mpfe_csr_awlock -> sm_mpfe:hps2mpfe_csr_awlock
	wire   [43:0] sm_hps_hps_s2mpfe_interconnect_awaddr;  // sm_hps:hps2mpfe_csr_awaddr -> sm_mpfe:hps2mpfe_csr_awaddr
	wire          sm_hps_hps_s2mpfe_interconnect_arready; // sm_mpfe:hps2mpfe_csr_arready -> sm_hps:hps2mpfe_csr_arready
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_bresp;   // sm_mpfe:hps2mpfe_csr_bresp -> sm_hps:hps2mpfe_csr_bresp
	wire   [63:0] sm_hps_hps_s2mpfe_interconnect_rdata;   // sm_mpfe:hps2mpfe_csr_rdata -> sm_hps:hps2mpfe_csr_rdata
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_arburst; // sm_hps:hps2mpfe_csr_arburst -> sm_mpfe:hps2mpfe_csr_arburst
	wire          sm_hps_hps_s2mpfe_interconnect_awready; // sm_mpfe:hps2mpfe_csr_awready -> sm_hps:hps2mpfe_csr_awready
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_arsize;  // sm_hps:hps2mpfe_csr_arsize -> sm_mpfe:hps2mpfe_csr_arsize
	wire          sm_hps_hps_s2mpfe_interconnect_bready;  // sm_hps:hps2mpfe_csr_bready -> sm_mpfe:hps2mpfe_csr_bready
	wire          sm_hps_hps_s2mpfe_interconnect_rlast;   // sm_mpfe:hps2mpfe_csr_rlast -> sm_hps:hps2mpfe_csr_rlast
	wire          sm_hps_hps_s2mpfe_interconnect_wlast;   // sm_hps:hps2mpfe_csr_wlast -> sm_mpfe:hps2mpfe_csr_wlast
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_rresp;   // sm_mpfe:hps2mpfe_csr_rresp -> sm_hps:hps2mpfe_csr_rresp
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_awid;    // sm_hps:hps2mpfe_csr_awid -> sm_mpfe:hps2mpfe_csr_awid
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_bid;     // sm_mpfe:hps2mpfe_csr_bid -> sm_hps:hps2mpfe_csr_bid
	wire          sm_hps_hps_s2mpfe_interconnect_bvalid;  // sm_mpfe:hps2mpfe_csr_bvalid -> sm_hps:hps2mpfe_csr_bvalid
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_aruser;  // sm_hps:hps2mpfe_csr_aruser -> sm_mpfe:hps2mpfe_csr_aruser
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_awsize;  // sm_hps:hps2mpfe_csr_awsize -> sm_mpfe:hps2mpfe_csr_awsize
	wire          sm_hps_hps_s2mpfe_interconnect_awvalid; // sm_hps:hps2mpfe_csr_awvalid -> sm_mpfe:hps2mpfe_csr_awvalid
	wire          sm_hps_hps_s2mpfe_interconnect_rvalid;  // sm_mpfe:hps2mpfe_csr_rvalid -> sm_hps:hps2mpfe_csr_rvalid
	wire          sm_mpfe_sdram2hps_interconnect_tbu_ras; // sm_mpfe:sdram_tbu_ras_irpt -> sm_hps:fpga2sdram_tbu_ras_irpt
	wire          sm_mpfe_sdram2hps_interconnect_ack;     // sm_mpfe:sdram_bridge_ack -> sm_hps:fpga2sdram_bridge_ack
	wire          sm_hps_hps2sdram_interconnect_reset_n;  // sm_hps:fpga2sdram_bridge_rst_n -> sm_mpfe:sdram_bridge_rst_n
	wire          sm_mpfe_sdram2hps_interconnect_tbu_pmu; // sm_mpfe:sdram_tbu_pmu_irpt -> sm_hps:fpga2sdram_tbu_pmu_irpt
	wire          sm_hps_hps2sdram_interconnect_req;      // sm_hps:fpga2sdram_bridge_req -> sm_mpfe:sdram_bridge_req

	agilex_hps_intel_sundancemesa_hps_100_soonmgi sm_hps (
		.h2f_reset                   (h2f_reset_reset),                        //  output,    width = 1,                   h2f_reset.reset
		.hps2fpga_clk                (hps2fpga_axi_clock_clk),                 //   input,    width = 1,          hps2fpga_axi_clock.clk
		.hps2fpga_rst                (hps2fpga_axi_reset_reset),               //   input,    width = 1,          hps2fpga_axi_reset.reset
		.hps2fpga_awid               (hps2fpga_awid),                          //  output,    width = 4,                    hps2fpga.awid
		.hps2fpga_awaddr             (hps2fpga_awaddr),                        //  output,   width = 38,                            .awaddr
		.hps2fpga_awlen              (hps2fpga_awlen),                         //  output,    width = 8,                            .awlen
		.hps2fpga_awsize             (hps2fpga_awsize),                        //  output,    width = 3,                            .awsize
		.hps2fpga_awburst            (hps2fpga_awburst),                       //  output,    width = 2,                            .awburst
		.hps2fpga_awlock             (hps2fpga_awlock),                        //  output,    width = 1,                            .awlock
		.hps2fpga_awcache            (hps2fpga_awcache),                       //  output,    width = 4,                            .awcache
		.hps2fpga_awprot             (hps2fpga_awprot),                        //  output,    width = 3,                            .awprot
		.hps2fpga_awvalid            (hps2fpga_awvalid),                       //  output,    width = 1,                            .awvalid
		.hps2fpga_awready            (hps2fpga_awready),                       //   input,    width = 1,                            .awready
		.hps2fpga_wdata              (hps2fpga_wdata),                         //  output,  width = 128,                            .wdata
		.hps2fpga_wstrb              (hps2fpga_wstrb),                         //  output,   width = 16,                            .wstrb
		.hps2fpga_wlast              (hps2fpga_wlast),                         //  output,    width = 1,                            .wlast
		.hps2fpga_wvalid             (hps2fpga_wvalid),                        //  output,    width = 1,                            .wvalid
		.hps2fpga_wready             (hps2fpga_wready),                        //   input,    width = 1,                            .wready
		.hps2fpga_bid                (hps2fpga_bid),                           //   input,    width = 4,                            .bid
		.hps2fpga_bresp              (hps2fpga_bresp),                         //   input,    width = 2,                            .bresp
		.hps2fpga_bvalid             (hps2fpga_bvalid),                        //   input,    width = 1,                            .bvalid
		.hps2fpga_bready             (hps2fpga_bready),                        //  output,    width = 1,                            .bready
		.hps2fpga_arid               (hps2fpga_arid),                          //  output,    width = 4,                            .arid
		.hps2fpga_araddr             (hps2fpga_araddr),                        //  output,   width = 38,                            .araddr
		.hps2fpga_arlen              (hps2fpga_arlen),                         //  output,    width = 8,                            .arlen
		.hps2fpga_arsize             (hps2fpga_arsize),                        //  output,    width = 3,                            .arsize
		.hps2fpga_arburst            (hps2fpga_arburst),                       //  output,    width = 2,                            .arburst
		.hps2fpga_arlock             (hps2fpga_arlock),                        //  output,    width = 1,                            .arlock
		.hps2fpga_arcache            (hps2fpga_arcache),                       //  output,    width = 4,                            .arcache
		.hps2fpga_arprot             (hps2fpga_arprot),                        //  output,    width = 3,                            .arprot
		.hps2fpga_arvalid            (hps2fpga_arvalid),                       //  output,    width = 1,                            .arvalid
		.hps2fpga_arready            (hps2fpga_arready),                       //   input,    width = 1,                            .arready
		.hps2fpga_rid                (hps2fpga_rid),                           //   input,    width = 4,                            .rid
		.hps2fpga_rdata              (hps2fpga_rdata),                         //   input,  width = 128,                            .rdata
		.hps2fpga_rresp              (hps2fpga_rresp),                         //   input,    width = 2,                            .rresp
		.hps2fpga_rlast              (hps2fpga_rlast),                         //   input,    width = 1,                            .rlast
		.hps2fpga_rvalid             (hps2fpga_rvalid),                        //   input,    width = 1,                            .rvalid
		.hps2fpga_rready             (hps2fpga_rready),                        //  output,    width = 1,                            .rready
		.lwhps2fpga_clk              (lwhps2fpga_axi_clock_clk),               //   input,    width = 1,        lwhps2fpga_axi_clock.clk
		.lwhps2fpga_rst              (lwhps2fpga_axi_reset_reset),             //   input,    width = 1,        lwhps2fpga_axi_reset.reset
		.lwhps2fpga_awid             (lwhps2fpga_awid),                        //  output,    width = 4,                  lwhps2fpga.awid
		.lwhps2fpga_awaddr           (lwhps2fpga_awaddr),                      //  output,   width = 29,                            .awaddr
		.lwhps2fpga_awlen            (lwhps2fpga_awlen),                       //  output,    width = 8,                            .awlen
		.lwhps2fpga_awsize           (lwhps2fpga_awsize),                      //  output,    width = 3,                            .awsize
		.lwhps2fpga_awburst          (lwhps2fpga_awburst),                     //  output,    width = 2,                            .awburst
		.lwhps2fpga_awlock           (lwhps2fpga_awlock),                      //  output,    width = 1,                            .awlock
		.lwhps2fpga_awcache          (lwhps2fpga_awcache),                     //  output,    width = 4,                            .awcache
		.lwhps2fpga_awprot           (lwhps2fpga_awprot),                      //  output,    width = 3,                            .awprot
		.lwhps2fpga_awvalid          (lwhps2fpga_awvalid),                     //  output,    width = 1,                            .awvalid
		.lwhps2fpga_awready          (lwhps2fpga_awready),                     //   input,    width = 1,                            .awready
		.lwhps2fpga_wdata            (lwhps2fpga_wdata),                       //  output,   width = 32,                            .wdata
		.lwhps2fpga_wstrb            (lwhps2fpga_wstrb),                       //  output,    width = 4,                            .wstrb
		.lwhps2fpga_wlast            (lwhps2fpga_wlast),                       //  output,    width = 1,                            .wlast
		.lwhps2fpga_wvalid           (lwhps2fpga_wvalid),                      //  output,    width = 1,                            .wvalid
		.lwhps2fpga_wready           (lwhps2fpga_wready),                      //   input,    width = 1,                            .wready
		.lwhps2fpga_bid              (lwhps2fpga_bid),                         //   input,    width = 4,                            .bid
		.lwhps2fpga_bresp            (lwhps2fpga_bresp),                       //   input,    width = 2,                            .bresp
		.lwhps2fpga_bvalid           (lwhps2fpga_bvalid),                      //   input,    width = 1,                            .bvalid
		.lwhps2fpga_bready           (lwhps2fpga_bready),                      //  output,    width = 1,                            .bready
		.lwhps2fpga_arid             (lwhps2fpga_arid),                        //  output,    width = 4,                            .arid
		.lwhps2fpga_araddr           (lwhps2fpga_araddr),                      //  output,   width = 29,                            .araddr
		.lwhps2fpga_arlen            (lwhps2fpga_arlen),                       //  output,    width = 8,                            .arlen
		.lwhps2fpga_arsize           (lwhps2fpga_arsize),                      //  output,    width = 3,                            .arsize
		.lwhps2fpga_arburst          (lwhps2fpga_arburst),                     //  output,    width = 2,                            .arburst
		.lwhps2fpga_arlock           (lwhps2fpga_arlock),                      //  output,    width = 1,                            .arlock
		.lwhps2fpga_arcache          (lwhps2fpga_arcache),                     //  output,    width = 4,                            .arcache
		.lwhps2fpga_arprot           (lwhps2fpga_arprot),                      //  output,    width = 3,                            .arprot
		.lwhps2fpga_arvalid          (lwhps2fpga_arvalid),                     //  output,    width = 1,                            .arvalid
		.lwhps2fpga_arready          (lwhps2fpga_arready),                     //   input,    width = 1,                            .arready
		.lwhps2fpga_rid              (lwhps2fpga_rid),                         //   input,    width = 4,                            .rid
		.lwhps2fpga_rdata            (lwhps2fpga_rdata),                       //   input,   width = 32,                            .rdata
		.lwhps2fpga_rresp            (lwhps2fpga_rresp),                       //   input,    width = 2,                            .rresp
		.lwhps2fpga_rlast            (lwhps2fpga_rlast),                       //   input,    width = 1,                            .rlast
		.lwhps2fpga_rvalid           (lwhps2fpga_rvalid),                      //   input,    width = 1,                            .rvalid
		.lwhps2fpga_rready           (lwhps2fpga_rready),                      //  output,    width = 1,                            .rready
		.emac0_rst_clk_app_n_o       (emac0_app_rst_reset_n),                  //  output,    width = 1,               emac0_app_rst.reset_n
		.h2f_pending_rst_req_n       (h2f_warm_reset_handshake_reset_req),     //  output,    width = 1,    h2f_warm_reset_handshake.reset_req
		.f2h_pending_rst_ack_n       (h2f_warm_reset_handshake_reset_ack),     //   input,    width = 1,                            .reset_ack
		.hps_osc_clk                 (hps_io_hps_osc_clk),                     //   input,    width = 1,                      hps_io.hps_osc_clk
		.sdmmc_data0                 (hps_io_sdmmc_data0),                     //   inout,    width = 1,                            .sdmmc_data0
		.sdmmc_data1                 (hps_io_sdmmc_data1),                     //   inout,    width = 1,                            .sdmmc_data1
		.sdmmc_cclk                  (hps_io_sdmmc_cclk),                      //  output,    width = 1,                            .sdmmc_cclk
		.sdmmc_data2                 (hps_io_sdmmc_data2),                     //   inout,    width = 1,                            .sdmmc_data2
		.sdmmc_data3                 (hps_io_sdmmc_data3),                     //   inout,    width = 1,                            .sdmmc_data3
		.sdmmc_cmd                   (hps_io_sdmmc_cmd),                       //   inout,    width = 1,                            .sdmmc_cmd
		.usb0_clk                    (hps_io_usb0_clk),                        //   input,    width = 1,                            .usb0_clk
		.usb0_stp                    (hps_io_usb0_stp),                        //  output,    width = 1,                            .usb0_stp
		.usb0_dir                    (hps_io_usb0_dir),                        //   input,    width = 1,                            .usb0_dir
		.usb0_data0                  (hps_io_usb0_data0),                      //   inout,    width = 1,                            .usb0_data0
		.usb0_data1                  (hps_io_usb0_data1),                      //   inout,    width = 1,                            .usb0_data1
		.usb0_nxt                    (hps_io_usb0_nxt),                        //   input,    width = 1,                            .usb0_nxt
		.usb0_data2                  (hps_io_usb0_data2),                      //   inout,    width = 1,                            .usb0_data2
		.usb0_data3                  (hps_io_usb0_data3),                      //   inout,    width = 1,                            .usb0_data3
		.usb0_data4                  (hps_io_usb0_data4),                      //   inout,    width = 1,                            .usb0_data4
		.usb0_data5                  (hps_io_usb0_data5),                      //   inout,    width = 1,                            .usb0_data5
		.usb0_data6                  (hps_io_usb0_data6),                      //   inout,    width = 1,                            .usb0_data6
		.usb0_data7                  (hps_io_usb0_data7),                      //   inout,    width = 1,                            .usb0_data7
		.emac0_tx_clk                (hps_io_emac0_tx_clk),                    //  output,    width = 1,                            .emac0_tx_clk
		.emac0_tx_ctl                (hps_io_emac0_tx_ctl),                    //  output,    width = 1,                            .emac0_tx_ctl
		.emac0_rx_clk                (hps_io_emac0_rx_clk),                    //   input,    width = 1,                            .emac0_rx_clk
		.emac0_rx_ctl                (hps_io_emac0_rx_ctl),                    //   input,    width = 1,                            .emac0_rx_ctl
		.emac0_txd0                  (hps_io_emac0_txd0),                      //  output,    width = 1,                            .emac0_txd0
		.emac0_txd1                  (hps_io_emac0_txd1),                      //  output,    width = 1,                            .emac0_txd1
		.emac0_rxd0                  (hps_io_emac0_rxd0),                      //   input,    width = 1,                            .emac0_rxd0
		.emac0_rxd1                  (hps_io_emac0_rxd1),                      //   input,    width = 1,                            .emac0_rxd1
		.emac0_txd2                  (hps_io_emac0_txd2),                      //  output,    width = 1,                            .emac0_txd2
		.emac0_txd3                  (hps_io_emac0_txd3),                      //  output,    width = 1,                            .emac0_txd3
		.emac0_rxd2                  (hps_io_emac0_rxd2),                      //   input,    width = 1,                            .emac0_rxd2
		.emac0_rxd3                  (hps_io_emac0_rxd3),                      //   input,    width = 1,                            .emac0_rxd3
		.mdio0_mdio                  (hps_io_mdio0_mdio),                      //   inout,    width = 1,                            .mdio0_mdio
		.mdio0_mdc                   (hps_io_mdio0_mdc),                       //  output,    width = 1,                            .mdio0_mdc
		.uart1_io_tx                 (hps_io_uart1_tx),                        //  output,    width = 1,                            .uart1_tx
		.uart1_io_rx                 (hps_io_uart1_rx),                        //   input,    width = 1,                            .uart1_rx
		.i2c1_sda                    (hps_io_i2c1_sda),                        //   inout,    width = 1,                            .i2c1_sda
		.i2c1_scl                    (hps_io_i2c1_scl),                        //   inout,    width = 1,                            .i2c1_scl
		.gpio28                      (hps_io_gpio28),                          //   inout,    width = 1,                            .gpio28
		.gpio34                      (hps_io_gpio34),                          //   inout,    width = 1,                            .gpio34
		.gpio40                      (hps_io_gpio40),                          //   inout,    width = 1,                            .gpio40
		.gpio41                      (hps_io_gpio41),                          //   inout,    width = 1,                            .gpio41
		.hps2mpfe_ccu_clk            (sm_hps_hps_ccu_interconnect_clk_clk),    //  output,    width = 1,    hps_ccu_interconnect_clk.clk
		.hps2mpfe_ccu_rst            (sm_hps_hps_ccu_interconnect_rst_reset),  //  output,    width = 1,    hps_ccu_interconnect_rst.reset
		.hps2mpfe_dmi0_araddr        (sm_hps_hps_dmi0_interconnect_araddr),    //  output,   width = 44,       hps_dmi0_interconnect.araddr
		.hps2mpfe_dmi0_arburst       (sm_hps_hps_dmi0_interconnect_arburst),   //  output,    width = 2,                            .arburst
		.hps2mpfe_dmi0_arcache       (sm_hps_hps_dmi0_interconnect_arcache),   //  output,    width = 4,                            .arcache
		.hps2mpfe_dmi0_arid          (sm_hps_hps_dmi0_interconnect_arid),      //  output,   width = 10,                            .arid
		.hps2mpfe_dmi0_arlen         (sm_hps_hps_dmi0_interconnect_arlen),     //  output,    width = 8,                            .arlen
		.hps2mpfe_dmi0_arlock        (sm_hps_hps_dmi0_interconnect_arlock),    //  output,    width = 1,                            .arlock
		.hps2mpfe_dmi0_arprot        (sm_hps_hps_dmi0_interconnect_arprot),    //  output,    width = 3,                            .arprot
		.hps2mpfe_dmi0_arqos         (sm_hps_hps_dmi0_interconnect_arqos),     //  output,    width = 4,                            .arqos
		.hps2mpfe_dmi0_arready       (sm_hps_hps_dmi0_interconnect_arready),   //   input,    width = 1,                            .arready
		.hps2mpfe_dmi0_arsize        (sm_hps_hps_dmi0_interconnect_arsize),    //  output,    width = 3,                            .arsize
		.hps2mpfe_dmi0_aruser        (sm_hps_hps_dmi0_interconnect_aruser),    //  output,    width = 8,                            .aruser
		.hps2mpfe_dmi0_arvalid       (sm_hps_hps_dmi0_interconnect_arvalid),   //  output,    width = 1,                            .arvalid
		.hps2mpfe_dmi0_awaddr        (sm_hps_hps_dmi0_interconnect_awaddr),    //  output,   width = 44,                            .awaddr
		.hps2mpfe_dmi0_awburst       (sm_hps_hps_dmi0_interconnect_awburst),   //  output,    width = 2,                            .awburst
		.hps2mpfe_dmi0_awcache       (sm_hps_hps_dmi0_interconnect_awcache),   //  output,    width = 4,                            .awcache
		.hps2mpfe_dmi0_awid          (sm_hps_hps_dmi0_interconnect_awid),      //  output,   width = 10,                            .awid
		.hps2mpfe_dmi0_awlen         (sm_hps_hps_dmi0_interconnect_awlen),     //  output,    width = 8,                            .awlen
		.hps2mpfe_dmi0_awlock        (sm_hps_hps_dmi0_interconnect_awlock),    //  output,    width = 1,                            .awlock
		.hps2mpfe_dmi0_awprot        (sm_hps_hps_dmi0_interconnect_awprot),    //  output,    width = 3,                            .awprot
		.hps2mpfe_dmi0_awqos         (sm_hps_hps_dmi0_interconnect_awqos),     //  output,    width = 4,                            .awqos
		.hps2mpfe_dmi0_awready       (sm_hps_hps_dmi0_interconnect_awready),   //   input,    width = 1,                            .awready
		.hps2mpfe_dmi0_awsize        (sm_hps_hps_dmi0_interconnect_awsize),    //  output,    width = 3,                            .awsize
		.hps2mpfe_dmi0_awuser        (sm_hps_hps_dmi0_interconnect_awuser),    //  output,    width = 8,                            .awuser
		.hps2mpfe_dmi0_awvalid       (sm_hps_hps_dmi0_interconnect_awvalid),   //  output,    width = 1,                            .awvalid
		.hps2mpfe_dmi0_bid           (sm_hps_hps_dmi0_interconnect_bid),       //   input,   width = 10,                            .bid
		.hps2mpfe_dmi0_bready        (sm_hps_hps_dmi0_interconnect_bready),    //  output,    width = 1,                            .bready
		.hps2mpfe_dmi0_bresp         (sm_hps_hps_dmi0_interconnect_bresp),     //   input,    width = 2,                            .bresp
		.hps2mpfe_dmi0_bvalid        (sm_hps_hps_dmi0_interconnect_bvalid),    //   input,    width = 1,                            .bvalid
		.hps2mpfe_dmi0_rdata         (sm_hps_hps_dmi0_interconnect_rdata),     //   input,  width = 256,                            .rdata
		.hps2mpfe_dmi0_rid           (sm_hps_hps_dmi0_interconnect_rid),       //   input,   width = 10,                            .rid
		.hps2mpfe_dmi0_rlast         (sm_hps_hps_dmi0_interconnect_rlast),     //   input,    width = 1,                            .rlast
		.hps2mpfe_dmi0_rready        (sm_hps_hps_dmi0_interconnect_rready),    //  output,    width = 1,                            .rready
		.hps2mpfe_dmi0_rresp         (sm_hps_hps_dmi0_interconnect_rresp),     //   input,    width = 2,                            .rresp
		.hps2mpfe_dmi0_rvalid        (sm_hps_hps_dmi0_interconnect_rvalid),    //   input,    width = 1,                            .rvalid
		.hps2mpfe_dmi0_wdata         (sm_hps_hps_dmi0_interconnect_wdata),     //  output,  width = 256,                            .wdata
		.hps2mpfe_dmi0_wlast         (sm_hps_hps_dmi0_interconnect_wlast),     //  output,    width = 1,                            .wlast
		.hps2mpfe_dmi0_wready        (sm_hps_hps_dmi0_interconnect_wready),    //   input,    width = 1,                            .wready
		.hps2mpfe_dmi0_wstrb         (sm_hps_hps_dmi0_interconnect_wstrb),     //  output,   width = 32,                            .wstrb
		.hps2mpfe_dmi0_wvalid        (sm_hps_hps_dmi0_interconnect_wvalid),    //  output,    width = 1,                            .wvalid
		.hps2mpfe_dmi1_araddr        (sm_hps_hps_dmi1_interconnect_araddr),    //  output,   width = 44,       hps_dmi1_interconnect.araddr
		.hps2mpfe_dmi1_arburst       (sm_hps_hps_dmi1_interconnect_arburst),   //  output,    width = 2,                            .arburst
		.hps2mpfe_dmi1_arcache       (sm_hps_hps_dmi1_interconnect_arcache),   //  output,    width = 4,                            .arcache
		.hps2mpfe_dmi1_arid          (sm_hps_hps_dmi1_interconnect_arid),      //  output,   width = 10,                            .arid
		.hps2mpfe_dmi1_arlen         (sm_hps_hps_dmi1_interconnect_arlen),     //  output,    width = 8,                            .arlen
		.hps2mpfe_dmi1_arlock        (sm_hps_hps_dmi1_interconnect_arlock),    //  output,    width = 1,                            .arlock
		.hps2mpfe_dmi1_arprot        (sm_hps_hps_dmi1_interconnect_arprot),    //  output,    width = 3,                            .arprot
		.hps2mpfe_dmi1_arqos         (sm_hps_hps_dmi1_interconnect_arqos),     //  output,    width = 4,                            .arqos
		.hps2mpfe_dmi1_arready       (sm_hps_hps_dmi1_interconnect_arready),   //   input,    width = 1,                            .arready
		.hps2mpfe_dmi1_arsize        (sm_hps_hps_dmi1_interconnect_arsize),    //  output,    width = 3,                            .arsize
		.hps2mpfe_dmi1_aruser        (sm_hps_hps_dmi1_interconnect_aruser),    //  output,    width = 8,                            .aruser
		.hps2mpfe_dmi1_arvalid       (sm_hps_hps_dmi1_interconnect_arvalid),   //  output,    width = 1,                            .arvalid
		.hps2mpfe_dmi1_awaddr        (sm_hps_hps_dmi1_interconnect_awaddr),    //  output,   width = 44,                            .awaddr
		.hps2mpfe_dmi1_awburst       (sm_hps_hps_dmi1_interconnect_awburst),   //  output,    width = 2,                            .awburst
		.hps2mpfe_dmi1_awcache       (sm_hps_hps_dmi1_interconnect_awcache),   //  output,    width = 4,                            .awcache
		.hps2mpfe_dmi1_awid          (sm_hps_hps_dmi1_interconnect_awid),      //  output,   width = 10,                            .awid
		.hps2mpfe_dmi1_awlen         (sm_hps_hps_dmi1_interconnect_awlen),     //  output,    width = 8,                            .awlen
		.hps2mpfe_dmi1_awlock        (sm_hps_hps_dmi1_interconnect_awlock),    //  output,    width = 1,                            .awlock
		.hps2mpfe_dmi1_awprot        (sm_hps_hps_dmi1_interconnect_awprot),    //  output,    width = 3,                            .awprot
		.hps2mpfe_dmi1_awqos         (sm_hps_hps_dmi1_interconnect_awqos),     //  output,    width = 4,                            .awqos
		.hps2mpfe_dmi1_awready       (sm_hps_hps_dmi1_interconnect_awready),   //   input,    width = 1,                            .awready
		.hps2mpfe_dmi1_awsize        (sm_hps_hps_dmi1_interconnect_awsize),    //  output,    width = 3,                            .awsize
		.hps2mpfe_dmi1_awuser        (sm_hps_hps_dmi1_interconnect_awuser),    //  output,    width = 8,                            .awuser
		.hps2mpfe_dmi1_awvalid       (sm_hps_hps_dmi1_interconnect_awvalid),   //  output,    width = 1,                            .awvalid
		.hps2mpfe_dmi1_bid           (sm_hps_hps_dmi1_interconnect_bid),       //   input,   width = 10,                            .bid
		.hps2mpfe_dmi1_bready        (sm_hps_hps_dmi1_interconnect_bready),    //  output,    width = 1,                            .bready
		.hps2mpfe_dmi1_bresp         (sm_hps_hps_dmi1_interconnect_bresp),     //   input,    width = 2,                            .bresp
		.hps2mpfe_dmi1_bvalid        (sm_hps_hps_dmi1_interconnect_bvalid),    //   input,    width = 1,                            .bvalid
		.hps2mpfe_dmi1_rdata         (sm_hps_hps_dmi1_interconnect_rdata),     //   input,  width = 256,                            .rdata
		.hps2mpfe_dmi1_rid           (sm_hps_hps_dmi1_interconnect_rid),       //   input,   width = 10,                            .rid
		.hps2mpfe_dmi1_rlast         (sm_hps_hps_dmi1_interconnect_rlast),     //   input,    width = 1,                            .rlast
		.hps2mpfe_dmi1_rready        (sm_hps_hps_dmi1_interconnect_rready),    //  output,    width = 1,                            .rready
		.hps2mpfe_dmi1_rresp         (sm_hps_hps_dmi1_interconnect_rresp),     //   input,    width = 2,                            .rresp
		.hps2mpfe_dmi1_rvalid        (sm_hps_hps_dmi1_interconnect_rvalid),    //   input,    width = 1,                            .rvalid
		.hps2mpfe_dmi1_wdata         (sm_hps_hps_dmi1_interconnect_wdata),     //  output,  width = 256,                            .wdata
		.hps2mpfe_dmi1_wlast         (sm_hps_hps_dmi1_interconnect_wlast),     //  output,    width = 1,                            .wlast
		.hps2mpfe_dmi1_wready        (sm_hps_hps_dmi1_interconnect_wready),    //   input,    width = 1,                            .wready
		.hps2mpfe_dmi1_wstrb         (sm_hps_hps_dmi1_interconnect_wstrb),     //  output,   width = 32,                            .wstrb
		.hps2mpfe_dmi1_wvalid        (sm_hps_hps_dmi1_interconnect_wvalid),    //  output,    width = 1,                            .wvalid
		.hps2mpfe_csr_araddr         (sm_hps_hps_s2mpfe_interconnect_araddr),  //  output,   width = 44,     hps_s2mpfe_interconnect.araddr
		.hps2mpfe_csr_arburst        (sm_hps_hps_s2mpfe_interconnect_arburst), //  output,    width = 2,                            .arburst
		.hps2mpfe_csr_arcache        (sm_hps_hps_s2mpfe_interconnect_arcache), //  output,    width = 4,                            .arcache
		.hps2mpfe_csr_arid           (sm_hps_hps_s2mpfe_interconnect_arid),    //  output,   width = 10,                            .arid
		.hps2mpfe_csr_arlen          (sm_hps_hps_s2mpfe_interconnect_arlen),   //  output,    width = 8,                            .arlen
		.hps2mpfe_csr_arlock         (sm_hps_hps_s2mpfe_interconnect_arlock),  //  output,    width = 1,                            .arlock
		.hps2mpfe_csr_arprot         (sm_hps_hps_s2mpfe_interconnect_arprot),  //  output,    width = 3,                            .arprot
		.hps2mpfe_csr_arready        (sm_hps_hps_s2mpfe_interconnect_arready), //   input,    width = 1,                            .arready
		.hps2mpfe_csr_arsize         (sm_hps_hps_s2mpfe_interconnect_arsize),  //  output,    width = 3,                            .arsize
		.hps2mpfe_csr_aruser         (sm_hps_hps_s2mpfe_interconnect_aruser),  //  output,    width = 8,                            .aruser
		.hps2mpfe_csr_arvalid        (sm_hps_hps_s2mpfe_interconnect_arvalid), //  output,    width = 1,                            .arvalid
		.hps2mpfe_csr_awaddr         (sm_hps_hps_s2mpfe_interconnect_awaddr),  //  output,   width = 44,                            .awaddr
		.hps2mpfe_csr_awburst        (sm_hps_hps_s2mpfe_interconnect_awburst), //  output,    width = 2,                            .awburst
		.hps2mpfe_csr_awcache        (sm_hps_hps_s2mpfe_interconnect_awcache), //  output,    width = 4,                            .awcache
		.hps2mpfe_csr_awid           (sm_hps_hps_s2mpfe_interconnect_awid),    //  output,   width = 10,                            .awid
		.hps2mpfe_csr_awlen          (sm_hps_hps_s2mpfe_interconnect_awlen),   //  output,    width = 8,                            .awlen
		.hps2mpfe_csr_awlock         (sm_hps_hps_s2mpfe_interconnect_awlock),  //  output,    width = 1,                            .awlock
		.hps2mpfe_csr_awprot         (sm_hps_hps_s2mpfe_interconnect_awprot),  //  output,    width = 3,                            .awprot
		.hps2mpfe_csr_awready        (sm_hps_hps_s2mpfe_interconnect_awready), //   input,    width = 1,                            .awready
		.hps2mpfe_csr_awsize         (sm_hps_hps_s2mpfe_interconnect_awsize),  //  output,    width = 3,                            .awsize
		.hps2mpfe_csr_awuser         (sm_hps_hps_s2mpfe_interconnect_awuser),  //  output,    width = 8,                            .awuser
		.hps2mpfe_csr_awvalid        (sm_hps_hps_s2mpfe_interconnect_awvalid), //  output,    width = 1,                            .awvalid
		.hps2mpfe_csr_bid            (sm_hps_hps_s2mpfe_interconnect_bid),     //   input,   width = 10,                            .bid
		.hps2mpfe_csr_bready         (sm_hps_hps_s2mpfe_interconnect_bready),  //  output,    width = 1,                            .bready
		.hps2mpfe_csr_bresp          (sm_hps_hps_s2mpfe_interconnect_bresp),   //   input,    width = 2,                            .bresp
		.hps2mpfe_csr_bvalid         (sm_hps_hps_s2mpfe_interconnect_bvalid),  //   input,    width = 1,                            .bvalid
		.hps2mpfe_csr_rdata          (sm_hps_hps_s2mpfe_interconnect_rdata),   //   input,   width = 64,                            .rdata
		.hps2mpfe_csr_rid            (sm_hps_hps_s2mpfe_interconnect_rid),     //   input,   width = 10,                            .rid
		.hps2mpfe_csr_rlast          (sm_hps_hps_s2mpfe_interconnect_rlast),   //   input,    width = 1,                            .rlast
		.hps2mpfe_csr_rready         (sm_hps_hps_s2mpfe_interconnect_rready),  //  output,    width = 1,                            .rready
		.hps2mpfe_csr_rresp          (sm_hps_hps_s2mpfe_interconnect_rresp),   //   input,    width = 2,                            .rresp
		.hps2mpfe_csr_rvalid         (sm_hps_hps_s2mpfe_interconnect_rvalid),  //   input,    width = 1,                            .rvalid
		.hps2mpfe_csr_wdata          (sm_hps_hps_s2mpfe_interconnect_wdata),   //  output,   width = 64,                            .wdata
		.hps2mpfe_csr_wlast          (sm_hps_hps_s2mpfe_interconnect_wlast),   //  output,    width = 1,                            .wlast
		.hps2mpfe_csr_wready         (sm_hps_hps_s2mpfe_interconnect_wready),  //   input,    width = 1,                            .wready
		.hps2mpfe_csr_wstrb          (sm_hps_hps_s2mpfe_interconnect_wstrb),   //  output,    width = 8,                            .wstrb
		.hps2mpfe_csr_wvalid         (sm_hps_hps_s2mpfe_interconnect_wvalid),  //  output,    width = 1,                            .wvalid
		.fpga2sdram_bridge_rst_n     (sm_hps_hps2sdram_interconnect_reset_n),  //  output,    width = 1,      hps2sdram_interconnect.reset_n
		.fpga2sdram_bridge_ack       (sm_mpfe_sdram2hps_interconnect_ack),     //   input,    width = 1,                            .ack
		.fpga2sdram_bridge_req       (sm_hps_hps2sdram_interconnect_req),      //  output,    width = 1,                            .req
		.fpga2sdram_tbu_pmu_irpt     (sm_mpfe_sdram2hps_interconnect_tbu_pmu), //   input,    width = 1,                            .tbu_pmu
		.fpga2sdram_tbu_ras_irpt     (sm_mpfe_sdram2hps_interconnect_tbu_ras), //   input,    width = 1,                            .tbu_ras
		.f2h_fpga_irq64              (fpga2hps_interrupt_irq1_irq),            //   input,   width = 32,     fpga2hps_interrupt_irq1.irq
		.f2h_fpga_irq32              (fpga2hps_interrupt_irq0_irq),            //   input,   width = 32,     fpga2hps_interrupt_irq0.irq
		.h2emif_interconnect_axi_rst ()                                        //  output,    width = 1, h2emif_interconnect_axi_rst.reset_n
	);

	agilex_hps_intel_sundancemesa_mpfe_100_d7hziti sm_mpfe (
		.f2sdram_clk           (f2sdram_axi_clock_clk),                  //   input,    width = 1,         f2sdram_axi_clock.clk
		.f2sdram_rst           (f2sdram_axi_reset_reset),                //   input,    width = 1,         f2sdram_axi_reset.reset
		.f2sdram_araddr        (f2sdram_araddr),                         //   input,   width = 32,                   f2sdram.araddr
		.f2sdram_arburst       (f2sdram_arburst),                        //   input,    width = 2,                          .arburst
		.f2sdram_arcache       (f2sdram_arcache),                        //   input,    width = 4,                          .arcache
		.f2sdram_arid          (f2sdram_arid),                           //   input,    width = 5,                          .arid
		.f2sdram_arlen         (f2sdram_arlen),                          //   input,    width = 8,                          .arlen
		.f2sdram_arlock        (f2sdram_arlock),                         //   input,    width = 1,                          .arlock
		.f2sdram_arprot        (f2sdram_arprot),                         //   input,    width = 3,                          .arprot
		.f2sdram_arqos         (f2sdram_arqos),                          //   input,    width = 4,                          .arqos
		.f2sdram_arready       (f2sdram_arready),                        //  output,    width = 1,                          .arready
		.f2sdram_arsize        (f2sdram_arsize),                         //   input,    width = 3,                          .arsize
		.f2sdram_arvalid       (f2sdram_arvalid),                        //   input,    width = 1,                          .arvalid
		.f2sdram_awaddr        (f2sdram_awaddr),                         //   input,   width = 32,                          .awaddr
		.f2sdram_awburst       (f2sdram_awburst),                        //   input,    width = 2,                          .awburst
		.f2sdram_awcache       (f2sdram_awcache),                        //   input,    width = 4,                          .awcache
		.f2sdram_awid          (f2sdram_awid),                           //   input,    width = 5,                          .awid
		.f2sdram_awlen         (f2sdram_awlen),                          //   input,    width = 8,                          .awlen
		.f2sdram_awlock        (f2sdram_awlock),                         //   input,    width = 1,                          .awlock
		.f2sdram_awprot        (f2sdram_awprot),                         //   input,    width = 3,                          .awprot
		.f2sdram_awqos         (f2sdram_awqos),                          //   input,    width = 4,                          .awqos
		.f2sdram_awready       (f2sdram_awready),                        //  output,    width = 1,                          .awready
		.f2sdram_awsize        (f2sdram_awsize),                         //   input,    width = 3,                          .awsize
		.f2sdram_awvalid       (f2sdram_awvalid),                        //   input,    width = 1,                          .awvalid
		.f2sdram_bid           (f2sdram_bid),                            //  output,    width = 5,                          .bid
		.f2sdram_bready        (f2sdram_bready),                         //   input,    width = 1,                          .bready
		.f2sdram_bresp         (f2sdram_bresp),                          //  output,    width = 2,                          .bresp
		.f2sdram_bvalid        (f2sdram_bvalid),                         //  output,    width = 1,                          .bvalid
		.f2sdram_rdata         (f2sdram_rdata),                          //  output,  width = 256,                          .rdata
		.f2sdram_rid           (f2sdram_rid),                            //  output,    width = 5,                          .rid
		.f2sdram_rlast         (f2sdram_rlast),                          //  output,    width = 1,                          .rlast
		.f2sdram_rready        (f2sdram_rready),                         //   input,    width = 1,                          .rready
		.f2sdram_rresp         (f2sdram_rresp),                          //  output,    width = 2,                          .rresp
		.f2sdram_rvalid        (f2sdram_rvalid),                         //  output,    width = 1,                          .rvalid
		.f2sdram_wdata         (f2sdram_wdata),                          //   input,  width = 256,                          .wdata
		.f2sdram_wlast         (f2sdram_wlast),                          //   input,    width = 1,                          .wlast
		.f2sdram_wready        (f2sdram_wready),                         //  output,    width = 1,                          .wready
		.f2sdram_wstrb         (f2sdram_wstrb),                          //   input,   width = 32,                          .wstrb
		.f2sdram_wvalid        (f2sdram_wvalid),                         //   input,    width = 1,                          .wvalid
		.f2sdram_aruser        (f2sdram_aruser),                         //   input,    width = 8,                          .aruser
		.f2sdram_awuser        (f2sdram_awuser),                         //   input,    width = 8,                          .awuser
		.f2sdram_wuser         (f2sdram_wuser),                          //   input,    width = 8,                          .wuser
		.f2sdram_buser         (f2sdram_buser),                          //  output,    width = 8,                          .buser
		.f2sdram_arregion      (f2sdram_arregion),                       //   input,    width = 4,                          .arregion
		.f2sdram_ruser         (f2sdram_ruser),                          //  output,    width = 8,                          .ruser
		.f2sdram_awregion      (f2sdram_awregion),                       //   input,    width = 4,                          .awregion
		.sdram_bridge_rst_n    (sm_hps_hps2sdram_interconnect_reset_n),  //   input,    width = 1,    sdram2hps_interconnect.reset_n
		.sdram_bridge_ack      (sm_mpfe_sdram2hps_interconnect_ack),     //  output,    width = 1,                          .ack
		.sdram_bridge_req      (sm_hps_hps2sdram_interconnect_req),      //   input,    width = 1,                          .req
		.sdram_tbu_pmu_irpt    (sm_mpfe_sdram2hps_interconnect_tbu_pmu), //  output,    width = 1,                          .tbu_pmu
		.sdram_tbu_ras_irpt    (sm_mpfe_sdram2hps_interconnect_tbu_ras), //  output,    width = 1,                          .tbu_ras
		.emif_csr_axi_clk      (io96b0_to_hps_ch0_axil_clk),             //   input,    width = 1,             io96b0_to_hps.ch0_axil_clk
		.emif_csr_axi_rst      (io96b0_to_hps_ch0_axil_reset_n),         //   input,    width = 1,                          .ch0_axil_reset_n
		.emif_mem_cfg_arready  (io96b0_to_hps_ch0_axil_arready),         //   input,    width = 1,                          .ch0_axil_arready
		.emif_mem_cfg_awready  (io96b0_to_hps_ch0_axil_awready),         //   input,    width = 1,                          .ch0_axil_awready
		.emif_mem_cfg_bresp    (io96b0_to_hps_ch0_axil_bresp),           //   input,    width = 2,                          .ch0_axil_bresp
		.emif_mem_cfg_bvalid   (io96b0_to_hps_ch0_axil_bvalid),          //   input,    width = 1,                          .ch0_axil_bvalid
		.emif_mem_cfg_rdata    (io96b0_to_hps_ch0_axil_rdata),           //   input,   width = 32,                          .ch0_axil_rdata
		.emif_mem_cfg_rresp    (io96b0_to_hps_ch0_axil_rresp),           //   input,    width = 2,                          .ch0_axil_rresp
		.emif_mem_cfg_rvalid   (io96b0_to_hps_ch0_axil_rvalid),          //   input,    width = 1,                          .ch0_axil_rvalid
		.emif_mem_cfg_wready   (io96b0_to_hps_ch0_axil_wready),          //   input,    width = 1,                          .ch0_axil_wready
		.emif_mem_cfg_araddr   (io96b0_to_hps_ch0_axil_araddr),          //  output,   width = 27,                          .ch0_axil_araddr
		.emif_mem_cfg_arvalid  (io96b0_to_hps_ch0_axil_arvalid),         //  output,    width = 1,                          .ch0_axil_arvalid
		.emif_mem_cfg_awaddr   (io96b0_to_hps_ch0_axil_awaddr),          //  output,   width = 27,                          .ch0_axil_awaddr
		.emif_mem_cfg_awvalid  (io96b0_to_hps_ch0_axil_awvalid),         //  output,    width = 1,                          .ch0_axil_awvalid
		.emif_mem_cfg_bready   (io96b0_to_hps_ch0_axil_bready),          //  output,    width = 1,                          .ch0_axil_bready
		.emif_mem_cfg_rready   (io96b0_to_hps_ch0_axil_rready),          //  output,    width = 1,                          .ch0_axil_rready
		.emif_mem_cfg_wdata    (io96b0_to_hps_ch0_axil_wdata),           //  output,   width = 32,                          .ch0_axil_wdata
		.emif_mem_cfg_wstrb    (io96b0_to_hps_ch0_axil_wstrb),           //  output,    width = 4,                          .ch0_axil_wstrb
		.emif_mem_cfg_wvalid   (io96b0_to_hps_ch0_axil_wvalid),          //  output,    width = 1,                          .ch0_axil_wvalid
		.emif_mem_cfg_arprot   (io96b0_to_hps_ch0_axil_arprot),          //  output,    width = 3,                          .ch0_axil_arprot
		.emif_mem_cfg_awprot   (io96b0_to_hps_ch0_axil_awprot),          //  output,    width = 3,                          .ch0_axil_awprot
		.emif_ch0_axi_clk      (io96b0_to_hps_axi4_ch0_clk),             //   input,    width = 1,                          .axi4_ch0_clk
		.emif_ch0_axi_rst      (io96b0_to_hps_axi4_ch0_reset_n),         //   input,    width = 1,                          .axi4_ch0_reset_n
		.emif0_arready         (io96b0_to_hps_axi4_ch0_arready),         //   input,    width = 1,                          .axi4_ch0_arready
		.emif0_awready         (io96b0_to_hps_axi4_ch0_awready),         //   input,    width = 1,                          .axi4_ch0_awready
		.emif0_bid             (io96b0_to_hps_axi4_ch0_bid),             //   input,    width = 7,                          .axi4_ch0_bid
		.emif0_bresp           (io96b0_to_hps_axi4_ch0_bresp),           //   input,    width = 2,                          .axi4_ch0_bresp
		.emif0_bvalid          (io96b0_to_hps_axi4_ch0_bvalid),          //   input,    width = 1,                          .axi4_ch0_bvalid
		.emif0_rdata           (io96b0_to_hps_axi4_ch0_rdata),           //   input,  width = 256,                          .axi4_ch0_rdata
		.emif0_rid             (io96b0_to_hps_axi4_ch0_rid),             //   input,    width = 7,                          .axi4_ch0_rid
		.emif0_rlast           (io96b0_to_hps_axi4_ch0_rlast),           //   input,    width = 1,                          .axi4_ch0_rlast
		.emif0_rresp           (io96b0_to_hps_axi4_ch0_rresp),           //   input,    width = 2,                          .axi4_ch0_rresp
		.emif0_ruser           (io96b0_to_hps_axi4_ch0_ruser),           //   input,   width = 32,                          .axi4_ch0_ruser
		.emif0_rvalid          (io96b0_to_hps_axi4_ch0_rvalid),          //   input,    width = 1,                          .axi4_ch0_rvalid
		.emif0_wready          (io96b0_to_hps_axi4_ch0_wready),          //   input,    width = 1,                          .axi4_ch0_wready
		.emif0_araddr          (io96b0_to_hps_axi4_ch0_araddr),          //  output,   width = 40,                          .axi4_ch0_araddr
		.emif0_arburst         (io96b0_to_hps_axi4_ch0_arburst),         //  output,    width = 2,                          .axi4_ch0_arburst
		.emif0_arid            (io96b0_to_hps_axi4_ch0_arid),            //  output,    width = 7,                          .axi4_ch0_arid
		.emif0_arlen           (io96b0_to_hps_axi4_ch0_arlen),           //  output,    width = 8,                          .axi4_ch0_arlen
		.emif0_arlock          (io96b0_to_hps_axi4_ch0_arlock),          //  output,    width = 1,                          .axi4_ch0_arlock
		.emif0_arqos           (io96b0_to_hps_axi4_ch0_arqos),           //  output,    width = 4,                          .axi4_ch0_arqos
		.emif0_arsize          (io96b0_to_hps_axi4_ch0_arsize),          //  output,    width = 3,                          .axi4_ch0_arsize
		.emif0_aruser          (io96b0_to_hps_axi4_ch0_aruser),          //  output,   width = 14,                          .axi4_ch0_aruser
		.emif0_arvalid         (io96b0_to_hps_axi4_ch0_arvalid),         //  output,    width = 1,                          .axi4_ch0_arvalid
		.emif0_awaddr          (io96b0_to_hps_axi4_ch0_awaddr),          //  output,   width = 40,                          .axi4_ch0_awaddr
		.emif0_awburst         (io96b0_to_hps_axi4_ch0_awburst),         //  output,    width = 2,                          .axi4_ch0_awburst
		.emif0_awid            (io96b0_to_hps_axi4_ch0_awid),            //  output,    width = 7,                          .axi4_ch0_awid
		.emif0_awlen           (io96b0_to_hps_axi4_ch0_awlen),           //  output,    width = 8,                          .axi4_ch0_awlen
		.emif0_awlock          (io96b0_to_hps_axi4_ch0_awlock),          //  output,    width = 1,                          .axi4_ch0_awlock
		.emif0_awqos           (io96b0_to_hps_axi4_ch0_awqos),           //  output,    width = 4,                          .axi4_ch0_awqos
		.emif0_awsize          (io96b0_to_hps_axi4_ch0_awsize),          //  output,    width = 3,                          .axi4_ch0_awsize
		.emif0_awuser          (io96b0_to_hps_axi4_ch0_awuser),          //  output,   width = 14,                          .axi4_ch0_awuser
		.emif0_awvalid         (io96b0_to_hps_axi4_ch0_awvalid),         //  output,    width = 1,                          .axi4_ch0_awvalid
		.emif0_bready          (io96b0_to_hps_axi4_ch0_bready),          //  output,    width = 1,                          .axi4_ch0_bready
		.emif0_rready          (io96b0_to_hps_axi4_ch0_rready),          //  output,    width = 1,                          .axi4_ch0_rready
		.emif0_wdata           (io96b0_to_hps_axi4_ch0_wdata),           //  output,  width = 256,                          .axi4_ch0_wdata
		.emif0_wlast           (io96b0_to_hps_axi4_ch0_wlast),           //  output,    width = 1,                          .axi4_ch0_wlast
		.emif0_wstrb           (io96b0_to_hps_axi4_ch0_wstrb),           //  output,   width = 32,                          .axi4_ch0_wstrb
		.emif0_wuser           (io96b0_to_hps_axi4_ch0_wuser),           //  output,   width = 32,                          .axi4_ch0_wuser
		.emif0_wvalid          (io96b0_to_hps_axi4_ch0_wvalid),          //  output,    width = 1,                          .axi4_ch0_wvalid
		.emif0_arprot          (io96b0_to_hps_axi4_ch0_arprot),          //  output,    width = 3,                          .axi4_ch0_arprot
		.emif0_awprot          (io96b0_to_hps_axi4_ch0_awprot),          //  output,    width = 3,                          .axi4_ch0_awprot
		.hps2mpfe_ccu_clk      (sm_hps_hps_ccu_interconnect_clk_clk),    //   input,    width = 1, mpfe_ccu_interconnect_clk.clk
		.hps2mpfe_ccu_rst      (sm_hps_hps_ccu_interconnect_rst_reset),  //   input,    width = 1, mpfe_ccu_interconnect_rst.reset
		.hps2mpfe_dmi0_araddr  (sm_hps_hps_dmi0_interconnect_araddr),    //   input,   width = 44,    mpfe_dmi0_interconnect.araddr
		.hps2mpfe_dmi0_arburst (sm_hps_hps_dmi0_interconnect_arburst),   //   input,    width = 2,                          .arburst
		.hps2mpfe_dmi0_arcache (sm_hps_hps_dmi0_interconnect_arcache),   //   input,    width = 4,                          .arcache
		.hps2mpfe_dmi0_arid    (sm_hps_hps_dmi0_interconnect_arid),      //   input,   width = 10,                          .arid
		.hps2mpfe_dmi0_arlen   (sm_hps_hps_dmi0_interconnect_arlen),     //   input,    width = 8,                          .arlen
		.hps2mpfe_dmi0_arlock  (sm_hps_hps_dmi0_interconnect_arlock),    //   input,    width = 1,                          .arlock
		.hps2mpfe_dmi0_arprot  (sm_hps_hps_dmi0_interconnect_arprot),    //   input,    width = 3,                          .arprot
		.hps2mpfe_dmi0_arqos   (sm_hps_hps_dmi0_interconnect_arqos),     //   input,    width = 4,                          .arqos
		.hps2mpfe_dmi0_arready (sm_hps_hps_dmi0_interconnect_arready),   //  output,    width = 1,                          .arready
		.hps2mpfe_dmi0_arsize  (sm_hps_hps_dmi0_interconnect_arsize),    //   input,    width = 3,                          .arsize
		.hps2mpfe_dmi0_aruser  (sm_hps_hps_dmi0_interconnect_aruser),    //   input,    width = 8,                          .aruser
		.hps2mpfe_dmi0_arvalid (sm_hps_hps_dmi0_interconnect_arvalid),   //   input,    width = 1,                          .arvalid
		.hps2mpfe_dmi0_awaddr  (sm_hps_hps_dmi0_interconnect_awaddr),    //   input,   width = 44,                          .awaddr
		.hps2mpfe_dmi0_awburst (sm_hps_hps_dmi0_interconnect_awburst),   //   input,    width = 2,                          .awburst
		.hps2mpfe_dmi0_awcache (sm_hps_hps_dmi0_interconnect_awcache),   //   input,    width = 4,                          .awcache
		.hps2mpfe_dmi0_awid    (sm_hps_hps_dmi0_interconnect_awid),      //   input,   width = 10,                          .awid
		.hps2mpfe_dmi0_awlen   (sm_hps_hps_dmi0_interconnect_awlen),     //   input,    width = 8,                          .awlen
		.hps2mpfe_dmi0_awlock  (sm_hps_hps_dmi0_interconnect_awlock),    //   input,    width = 1,                          .awlock
		.hps2mpfe_dmi0_awprot  (sm_hps_hps_dmi0_interconnect_awprot),    //   input,    width = 3,                          .awprot
		.hps2mpfe_dmi0_awqos   (sm_hps_hps_dmi0_interconnect_awqos),     //   input,    width = 4,                          .awqos
		.hps2mpfe_dmi0_awready (sm_hps_hps_dmi0_interconnect_awready),   //  output,    width = 1,                          .awready
		.hps2mpfe_dmi0_awsize  (sm_hps_hps_dmi0_interconnect_awsize),    //   input,    width = 3,                          .awsize
		.hps2mpfe_dmi0_awuser  (sm_hps_hps_dmi0_interconnect_awuser),    //   input,    width = 8,                          .awuser
		.hps2mpfe_dmi0_awvalid (sm_hps_hps_dmi0_interconnect_awvalid),   //   input,    width = 1,                          .awvalid
		.hps2mpfe_dmi0_bid     (sm_hps_hps_dmi0_interconnect_bid),       //  output,   width = 10,                          .bid
		.hps2mpfe_dmi0_bready  (sm_hps_hps_dmi0_interconnect_bready),    //   input,    width = 1,                          .bready
		.hps2mpfe_dmi0_bresp   (sm_hps_hps_dmi0_interconnect_bresp),     //  output,    width = 2,                          .bresp
		.hps2mpfe_dmi0_bvalid  (sm_hps_hps_dmi0_interconnect_bvalid),    //  output,    width = 1,                          .bvalid
		.hps2mpfe_dmi0_rdata   (sm_hps_hps_dmi0_interconnect_rdata),     //  output,  width = 256,                          .rdata
		.hps2mpfe_dmi0_rid     (sm_hps_hps_dmi0_interconnect_rid),       //  output,   width = 10,                          .rid
		.hps2mpfe_dmi0_rlast   (sm_hps_hps_dmi0_interconnect_rlast),     //  output,    width = 1,                          .rlast
		.hps2mpfe_dmi0_rready  (sm_hps_hps_dmi0_interconnect_rready),    //   input,    width = 1,                          .rready
		.hps2mpfe_dmi0_rresp   (sm_hps_hps_dmi0_interconnect_rresp),     //  output,    width = 2,                          .rresp
		.hps2mpfe_dmi0_rvalid  (sm_hps_hps_dmi0_interconnect_rvalid),    //  output,    width = 1,                          .rvalid
		.hps2mpfe_dmi0_wdata   (sm_hps_hps_dmi0_interconnect_wdata),     //   input,  width = 256,                          .wdata
		.hps2mpfe_dmi0_wlast   (sm_hps_hps_dmi0_interconnect_wlast),     //   input,    width = 1,                          .wlast
		.hps2mpfe_dmi0_wready  (sm_hps_hps_dmi0_interconnect_wready),    //  output,    width = 1,                          .wready
		.hps2mpfe_dmi0_wstrb   (sm_hps_hps_dmi0_interconnect_wstrb),     //   input,   width = 32,                          .wstrb
		.hps2mpfe_dmi0_wvalid  (sm_hps_hps_dmi0_interconnect_wvalid),    //   input,    width = 1,                          .wvalid
		.hps2mpfe_dmi1_araddr  (sm_hps_hps_dmi1_interconnect_araddr),    //   input,   width = 44,    mpfe_dmi1_interconnect.araddr
		.hps2mpfe_dmi1_arburst (sm_hps_hps_dmi1_interconnect_arburst),   //   input,    width = 2,                          .arburst
		.hps2mpfe_dmi1_arcache (sm_hps_hps_dmi1_interconnect_arcache),   //   input,    width = 4,                          .arcache
		.hps2mpfe_dmi1_arid    (sm_hps_hps_dmi1_interconnect_arid),      //   input,   width = 10,                          .arid
		.hps2mpfe_dmi1_arlen   (sm_hps_hps_dmi1_interconnect_arlen),     //   input,    width = 8,                          .arlen
		.hps2mpfe_dmi1_arlock  (sm_hps_hps_dmi1_interconnect_arlock),    //   input,    width = 1,                          .arlock
		.hps2mpfe_dmi1_arprot  (sm_hps_hps_dmi1_interconnect_arprot),    //   input,    width = 3,                          .arprot
		.hps2mpfe_dmi1_arqos   (sm_hps_hps_dmi1_interconnect_arqos),     //   input,    width = 4,                          .arqos
		.hps2mpfe_dmi1_arready (sm_hps_hps_dmi1_interconnect_arready),   //  output,    width = 1,                          .arready
		.hps2mpfe_dmi1_arsize  (sm_hps_hps_dmi1_interconnect_arsize),    //   input,    width = 3,                          .arsize
		.hps2mpfe_dmi1_aruser  (sm_hps_hps_dmi1_interconnect_aruser),    //   input,    width = 8,                          .aruser
		.hps2mpfe_dmi1_arvalid (sm_hps_hps_dmi1_interconnect_arvalid),   //   input,    width = 1,                          .arvalid
		.hps2mpfe_dmi1_awaddr  (sm_hps_hps_dmi1_interconnect_awaddr),    //   input,   width = 44,                          .awaddr
		.hps2mpfe_dmi1_awburst (sm_hps_hps_dmi1_interconnect_awburst),   //   input,    width = 2,                          .awburst
		.hps2mpfe_dmi1_awcache (sm_hps_hps_dmi1_interconnect_awcache),   //   input,    width = 4,                          .awcache
		.hps2mpfe_dmi1_awid    (sm_hps_hps_dmi1_interconnect_awid),      //   input,   width = 10,                          .awid
		.hps2mpfe_dmi1_awlen   (sm_hps_hps_dmi1_interconnect_awlen),     //   input,    width = 8,                          .awlen
		.hps2mpfe_dmi1_awlock  (sm_hps_hps_dmi1_interconnect_awlock),    //   input,    width = 1,                          .awlock
		.hps2mpfe_dmi1_awprot  (sm_hps_hps_dmi1_interconnect_awprot),    //   input,    width = 3,                          .awprot
		.hps2mpfe_dmi1_awqos   (sm_hps_hps_dmi1_interconnect_awqos),     //   input,    width = 4,                          .awqos
		.hps2mpfe_dmi1_awready (sm_hps_hps_dmi1_interconnect_awready),   //  output,    width = 1,                          .awready
		.hps2mpfe_dmi1_awsize  (sm_hps_hps_dmi1_interconnect_awsize),    //   input,    width = 3,                          .awsize
		.hps2mpfe_dmi1_awuser  (sm_hps_hps_dmi1_interconnect_awuser),    //   input,    width = 8,                          .awuser
		.hps2mpfe_dmi1_awvalid (sm_hps_hps_dmi1_interconnect_awvalid),   //   input,    width = 1,                          .awvalid
		.hps2mpfe_dmi1_bid     (sm_hps_hps_dmi1_interconnect_bid),       //  output,   width = 10,                          .bid
		.hps2mpfe_dmi1_bready  (sm_hps_hps_dmi1_interconnect_bready),    //   input,    width = 1,                          .bready
		.hps2mpfe_dmi1_bresp   (sm_hps_hps_dmi1_interconnect_bresp),     //  output,    width = 2,                          .bresp
		.hps2mpfe_dmi1_bvalid  (sm_hps_hps_dmi1_interconnect_bvalid),    //  output,    width = 1,                          .bvalid
		.hps2mpfe_dmi1_rdata   (sm_hps_hps_dmi1_interconnect_rdata),     //  output,  width = 256,                          .rdata
		.hps2mpfe_dmi1_rid     (sm_hps_hps_dmi1_interconnect_rid),       //  output,   width = 10,                          .rid
		.hps2mpfe_dmi1_rlast   (sm_hps_hps_dmi1_interconnect_rlast),     //  output,    width = 1,                          .rlast
		.hps2mpfe_dmi1_rready  (sm_hps_hps_dmi1_interconnect_rready),    //   input,    width = 1,                          .rready
		.hps2mpfe_dmi1_rresp   (sm_hps_hps_dmi1_interconnect_rresp),     //  output,    width = 2,                          .rresp
		.hps2mpfe_dmi1_rvalid  (sm_hps_hps_dmi1_interconnect_rvalid),    //  output,    width = 1,                          .rvalid
		.hps2mpfe_dmi1_wdata   (sm_hps_hps_dmi1_interconnect_wdata),     //   input,  width = 256,                          .wdata
		.hps2mpfe_dmi1_wlast   (sm_hps_hps_dmi1_interconnect_wlast),     //   input,    width = 1,                          .wlast
		.hps2mpfe_dmi1_wready  (sm_hps_hps_dmi1_interconnect_wready),    //  output,    width = 1,                          .wready
		.hps2mpfe_dmi1_wstrb   (sm_hps_hps_dmi1_interconnect_wstrb),     //   input,   width = 32,                          .wstrb
		.hps2mpfe_dmi1_wvalid  (sm_hps_hps_dmi1_interconnect_wvalid),    //   input,    width = 1,                          .wvalid
		.hps2mpfe_csr_araddr   (sm_hps_hps_s2mpfe_interconnect_araddr),  //   input,   width = 44,  mpfe_s2mpfe_interconnect.araddr
		.hps2mpfe_csr_arburst  (sm_hps_hps_s2mpfe_interconnect_arburst), //   input,    width = 2,                          .arburst
		.hps2mpfe_csr_arcache  (sm_hps_hps_s2mpfe_interconnect_arcache), //   input,    width = 4,                          .arcache
		.hps2mpfe_csr_arid     (sm_hps_hps_s2mpfe_interconnect_arid),    //   input,   width = 10,                          .arid
		.hps2mpfe_csr_arlen    (sm_hps_hps_s2mpfe_interconnect_arlen),   //   input,    width = 8,                          .arlen
		.hps2mpfe_csr_arlock   (sm_hps_hps_s2mpfe_interconnect_arlock),  //   input,    width = 1,                          .arlock
		.hps2mpfe_csr_arprot   (sm_hps_hps_s2mpfe_interconnect_arprot),  //   input,    width = 3,                          .arprot
		.hps2mpfe_csr_arready  (sm_hps_hps_s2mpfe_interconnect_arready), //  output,    width = 1,                          .arready
		.hps2mpfe_csr_arsize   (sm_hps_hps_s2mpfe_interconnect_arsize),  //   input,    width = 3,                          .arsize
		.hps2mpfe_csr_aruser   (sm_hps_hps_s2mpfe_interconnect_aruser),  //   input,    width = 8,                          .aruser
		.hps2mpfe_csr_arvalid  (sm_hps_hps_s2mpfe_interconnect_arvalid), //   input,    width = 1,                          .arvalid
		.hps2mpfe_csr_awaddr   (sm_hps_hps_s2mpfe_interconnect_awaddr),  //   input,   width = 44,                          .awaddr
		.hps2mpfe_csr_awburst  (sm_hps_hps_s2mpfe_interconnect_awburst), //   input,    width = 2,                          .awburst
		.hps2mpfe_csr_awcache  (sm_hps_hps_s2mpfe_interconnect_awcache), //   input,    width = 4,                          .awcache
		.hps2mpfe_csr_awid     (sm_hps_hps_s2mpfe_interconnect_awid),    //   input,   width = 10,                          .awid
		.hps2mpfe_csr_awlen    (sm_hps_hps_s2mpfe_interconnect_awlen),   //   input,    width = 8,                          .awlen
		.hps2mpfe_csr_awlock   (sm_hps_hps_s2mpfe_interconnect_awlock),  //   input,    width = 1,                          .awlock
		.hps2mpfe_csr_awprot   (sm_hps_hps_s2mpfe_interconnect_awprot),  //   input,    width = 3,                          .awprot
		.hps2mpfe_csr_awready  (sm_hps_hps_s2mpfe_interconnect_awready), //  output,    width = 1,                          .awready
		.hps2mpfe_csr_awsize   (sm_hps_hps_s2mpfe_interconnect_awsize),  //   input,    width = 3,                          .awsize
		.hps2mpfe_csr_awuser   (sm_hps_hps_s2mpfe_interconnect_awuser),  //   input,    width = 8,                          .awuser
		.hps2mpfe_csr_awvalid  (sm_hps_hps_s2mpfe_interconnect_awvalid), //   input,    width = 1,                          .awvalid
		.hps2mpfe_csr_bid      (sm_hps_hps_s2mpfe_interconnect_bid),     //  output,   width = 10,                          .bid
		.hps2mpfe_csr_bready   (sm_hps_hps_s2mpfe_interconnect_bready),  //   input,    width = 1,                          .bready
		.hps2mpfe_csr_bresp    (sm_hps_hps_s2mpfe_interconnect_bresp),   //  output,    width = 2,                          .bresp
		.hps2mpfe_csr_bvalid   (sm_hps_hps_s2mpfe_interconnect_bvalid),  //  output,    width = 1,                          .bvalid
		.hps2mpfe_csr_rdata    (sm_hps_hps_s2mpfe_interconnect_rdata),   //  output,   width = 64,                          .rdata
		.hps2mpfe_csr_rid      (sm_hps_hps_s2mpfe_interconnect_rid),     //  output,   width = 10,                          .rid
		.hps2mpfe_csr_rlast    (sm_hps_hps_s2mpfe_interconnect_rlast),   //  output,    width = 1,                          .rlast
		.hps2mpfe_csr_rready   (sm_hps_hps_s2mpfe_interconnect_rready),  //   input,    width = 1,                          .rready
		.hps2mpfe_csr_rresp    (sm_hps_hps_s2mpfe_interconnect_rresp),   //  output,    width = 2,                          .rresp
		.hps2mpfe_csr_rvalid   (sm_hps_hps_s2mpfe_interconnect_rvalid),  //  output,    width = 1,                          .rvalid
		.hps2mpfe_csr_wdata    (sm_hps_hps_s2mpfe_interconnect_wdata),   //   input,   width = 64,                          .wdata
		.hps2mpfe_csr_wlast    (sm_hps_hps_s2mpfe_interconnect_wlast),   //   input,    width = 1,                          .wlast
		.hps2mpfe_csr_wready   (sm_hps_hps_s2mpfe_interconnect_wready),  //  output,    width = 1,                          .wready
		.hps2mpfe_csr_wstrb    (sm_hps_hps_s2mpfe_interconnect_wstrb),   //   input,    width = 8,                          .wstrb
		.hps2mpfe_csr_wvalid   (sm_hps_hps_s2mpfe_interconnect_wvalid)   //   input,    width = 1,                          .wvalid
	);

endmodule
