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`timescale 1ps/1ps

module rd_response_mem_cwyib4q #(
    parameter ST_DATA_W = 35,
    parameter ID_W      = 10,
    parameter PIPELINE_OUT = 0,
    parameter PIPELINE_CMP = 0
) ( 
    input                 clk,
    input                 rst,
    input                 in_valid,
    input [ST_DATA_W-1:0] in_data,
    output                in_ready,
    output logic          out_valid,
    output[ST_DATA_W-1:0] out_data,
    input                 out_ready,
    output                cmd_valid,
    output [ID_W-1:0]     cmd_id,
    input                 cmd_ready,
    input                 rsp_valid,
    input [ID_W-1:0]      rsp_id,
    output logic          rsp_ready    
);

localparam PIPELINE_CNT = PIPELINE_OUT + PIPELINE_CMP ;


	  localparam [4:0] depth = 1;
	  localparam [4:0] depth_index = 1;


logic [ST_DATA_W:0] dout0;
logic [1-1:0] sel_index;
logic [1-1 :0] demuxed,demuxed_valid;
logic ready_out_mem;
logic [1 -1 :0] shift_occurred;

rd_sipo_plus_cwyib4q #(
    .TOTAL_W (ST_DATA_W+1),
    .ID_W    (ID_W) 
) mem (
    .clk             (clk),
    .rst             (rst),
    .in_valid        (in_valid  & cmd_ready),
    .in_data         (in_data),
    .in_ready       (ready_out_mem),
    .clr             (demuxed_valid), 
    .shift_occurred  (shift_occurred),
    .dout0           (dout0)
);


rd_comp_sel_cwyib4q #(
    .PIPELINE_OUT(PIPELINE_OUT),
    .PIPELINE_CMP(PIPELINE_CMP),
    .WIDTH       (ID_W)
) comp_sel (
    .clk            (clk),
    .in_0           ({dout0[ST_DATA_W],dout0[ID_W-1:0]}),
    .base           (rsp_id),
    .shift_occurred (shift_occurred),
    .sel            (),
    .sel_index      (sel_index),
    .clr            (demuxed_valid)
);

rd_demux_cwyib4q demux ( .index(sel_index), .demuxed(demuxed)  );

generate 
genvar i;
    for (i=0;i<1;i++) begin : MY_LABEL_0
        assign demuxed_valid[i] = demuxed[i] & rsp_valid & rsp_ready;
    end
endgenerate 
rd_mux_cwyib4q #(
    .DATA_W(ST_DATA_W)
) mux (
    .index (sel_index),
    .in0           (dout0[ST_DATA_W-1:0]),
    .muxed (out_data)
);

assign in_ready = ready_out_mem;
generate 
    if (PIPELINE_CMP==1) begin : PPL_1
        always @ (posedge clk) begin
            out_valid <= rsp_valid;
            rsp_ready    <= out_ready;
        end
    end
    else begin : PPL_0
        assign out_valid = rsp_valid;
        assign rsp_ready    = out_ready;
    end
endgenerate


assign cmd_valid = in_valid & in_ready;
assign cmd_id    = in_data[ID_W-1:0];

endmodule

module rd_demux_cwyib4q (
    input  [1-1:0] index,
    output [1 -1 :0] demuxed
);

generate 
genvar i;
    for (i=0;i<1;i++) begin : MY_LABEL_1
        assign demuxed[i] = (i==index);
    end
endgenerate
endmodule


module rd_mux_cwyib4q #(
    parameter DATA_W = 10
) (
    input [1-1:0] index,

    input  [DATA_W-1:0] in0,

    output logic [DATA_W-1:0] muxed
);
  
always @ * 
    case (index)
     default : muxed = in0;

    endcase

endmodule

`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "g4C5XhiVgIsot17RhmniMaWr74zBSsEIWWpvrh2OfY7zsE/GRUwh+h8kwFouKZM7aDVnfodYGq3Rk/+aIV/LhmOnotIFWwTLHeCg4q58QY8ebBhDunmhEw9pVeSnxyIfZOF36bcFs+PPu8zFjUpUmwPp0ZayeeNNAzuyoBxofiuKXveyhtMEYKr58+sGPuygd1q2QgWCXeNeK3v7pUsh+Ke+UaVach9SikQZsUX/o1o1GunTJfTXbaX/+1CrH3mIqS1/rV62F6BQffKHqNgzWF4yhAq7pO6o3E+Wp4BtfLO8wS/8P1VKDRV8Pg/a576JRIQt89JyFRCxX7PxYPD11e4jyEdcxn1oYPDiK+gYyjWf2EOd4lu6+yiJoQKHiNTGdmrmWYQmIjEFK0bOLgzd4B6FaUP7QDA30637Cy5WUoN/qAF9WQxx/QLJ9vMVd0HboY7ByeBIa3bQO6NF7XfW20cdFW37HYg+EfxHWpl1eZkZBVjNyeO4zIVdp/h13fWShqoJTAoaigV9nDtCB823C2KfadXiPdmKTy6KiVEqFTszyPDhfN2pky+i+LxkMAxwrw5hHrY2veys/qZlabUyz1lVxwWmlZJGMOlUBYis6eWji2r38J9kaDSTZ0HNdWI5tKI9Ig6vXXmWThJF6q++iBMqXwI2MtbuMx7gYbu0RNefWorUKjSt5NLixQzEL70gK3kxU1HEnzBfZ1U21YAGe2uclK2CbJbeM+2dg+v4WUZUZMQonZpDYhW5unvAeSuGCLyKRgtnL3ALengpD7DsYUxk51iqpEzhLmFpDnbzKzsH5ruQDqGsTOJZF0yqRRTTI6U+OH8ICACrP2i+3GDatimY0SQzBhQQafL0126ikKd3pErx9UpA2n+zIYxVvlNDsVnc+9U1MHkqzVAuho6+phM64iS9Yju5XbJQ7Qx1bpATr3trXTaTSkCPgVopvnjDnQDZgDoH+5Td0nwIRce4FlvYl/8gNU7VjXYvaQ9RV0aUtmeOxUdMq1Sz55NfQLhM"
`endif