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module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_420_cy5n3cq #() (
   output logic         s0_noc_axi4lite_clock  ,
   output logic         s0_noc_axi4lite_reset_n,
   input  logic [26:0]  s0_noc_axi4lite_awaddr ,
   input  logic         s0_noc_axi4lite_awvalid,
   output logic         s0_noc_axi4lite_awready,
   input  logic [26:0]  s0_noc_axi4lite_araddr ,
   input  logic         s0_noc_axi4lite_arvalid,
   output logic         s0_noc_axi4lite_arready,
   input  logic [31:0]  s0_noc_axi4lite_wdata  ,
   input  logic         s0_noc_axi4lite_wvalid ,
   output logic         s0_noc_axi4lite_wready ,
   output logic [1:0]   s0_noc_axi4lite_rresp  ,
   output logic [31:0]  s0_noc_axi4lite_rdata  ,
   output logic         s0_noc_axi4lite_rvalid ,
   input  logic         s0_noc_axi4lite_rready ,
   output logic [1:0]   s0_noc_axi4lite_bresp  ,
   output logic         s0_noc_axi4lite_bvalid ,
   input  logic         s0_noc_axi4lite_bready ,
   input  logic [2:0]   s0_noc_axi4lite_awprot ,
   input  logic [2:0]   s0_noc_axi4lite_arprot ,
   input  logic [3:0]   s0_noc_axi4lite_wstrb  ,
   input  logic [39:0]  s0_axi4_awaddr         ,
   input  logic [1:0]   s0_axi4_awburst        ,
   input  logic [6:0]   s0_axi4_awid           ,
   input  logic [7:0]   s0_axi4_awlen          ,
   input  logic         s0_axi4_awlock         ,
   input  logic [3:0]   s0_axi4_awqos          ,
   input  logic [2:0]   s0_axi4_awsize         ,
   input  logic         s0_axi4_awvalid        ,
   input  logic [13:0]  s0_axi4_awuser         ,
   input  logic [2:0]   s0_axi4_awprot         ,
   output logic         s0_axi4_awready        ,
   input  logic [39:0]  s0_axi4_araddr         ,
   input  logic [1:0]   s0_axi4_arburst        ,
   input  logic [6:0]   s0_axi4_arid           ,
   input  logic [7:0]   s0_axi4_arlen          ,
   input  logic         s0_axi4_arlock         ,
   input  logic [3:0]   s0_axi4_arqos          ,
   input  logic [2:0]   s0_axi4_arsize         ,
   input  logic         s0_axi4_arvalid        ,
   input  logic [13:0]  s0_axi4_aruser         ,
   input  logic [2:0]   s0_axi4_arprot         ,
   output logic         s0_axi4_arready        ,
   input  logic [255:0] s0_axi4_wdata          ,
   input  logic [31:0]  s0_axi4_wstrb          ,
   input  logic         s0_axi4_wlast          ,
   input  logic         s0_axi4_wvalid         ,
   output logic         s0_axi4_wready         ,
   input  logic         s0_axi4_bready         ,
   output logic [6:0]   s0_axi4_bid            ,
   output logic [1:0]   s0_axi4_bresp          ,
   output logic         s0_axi4_bvalid         ,
   input  logic         s0_axi4_rready         ,
   output logic [255:0] s0_axi4_rdata          ,
   output logic [6:0]   s0_axi4_rid            ,
   output logic         s0_axi4_rlast          ,
   output logic [1:0]   s0_axi4_rresp          ,
   output logic         s0_axi4_rvalid         ,
   output logic         noc_aclk_0             ,
   output logic         noc_rst_n_0            ,
   input  logic [31:0]  s0_axi4_wuser          ,
   output logic [31:0]  s0_axi4_ruser          ,
   output logic         mem_0_cs               ,
   output logic [5:0]   mem_0_ca               ,
   output logic         mem_0_cke              ,
   inout  tri   [31:0]  mem_0_dq               ,
   inout  tri   [3:0]   mem_0_dqs_t            ,
   inout  tri   [3:0]   mem_0_dqs_c            ,
   inout  tri   [3:0]   mem_0_dmi              ,
   output logic         mem_0_ck_t             ,
   output logic         mem_0_ck_c             ,
   output logic         mem_0_reset_n          ,
   input  logic         oct_rzqin_0            ,
   input  logic         ref_clk                
);

   emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_420_cy5n3cq_arch_top #() emif_arch_top (
      .s0_noc_axi4lite_clock   (s0_noc_axi4lite_clock  ),
      .s0_noc_axi4lite_reset_n (s0_noc_axi4lite_reset_n),
      .s0_noc_axi4lite_awaddr  (s0_noc_axi4lite_awaddr ),
      .s0_noc_axi4lite_awvalid (s0_noc_axi4lite_awvalid),
      .s0_noc_axi4lite_awready (s0_noc_axi4lite_awready),
      .s0_noc_axi4lite_araddr  (s0_noc_axi4lite_araddr ),
      .s0_noc_axi4lite_arvalid (s0_noc_axi4lite_arvalid),
      .s0_noc_axi4lite_arready (s0_noc_axi4lite_arready),
      .s0_noc_axi4lite_wdata   (s0_noc_axi4lite_wdata  ),
      .s0_noc_axi4lite_wvalid  (s0_noc_axi4lite_wvalid ),
      .s0_noc_axi4lite_wready  (s0_noc_axi4lite_wready ),
      .s0_noc_axi4lite_rresp   (s0_noc_axi4lite_rresp  ),
      .s0_noc_axi4lite_rdata   (s0_noc_axi4lite_rdata  ),
      .s0_noc_axi4lite_rvalid  (s0_noc_axi4lite_rvalid ),
      .s0_noc_axi4lite_rready  (s0_noc_axi4lite_rready ),
      .s0_noc_axi4lite_bresp   (s0_noc_axi4lite_bresp  ),
      .s0_noc_axi4lite_bvalid  (s0_noc_axi4lite_bvalid ),
      .s0_noc_axi4lite_bready  (s0_noc_axi4lite_bready ),
      .s0_noc_axi4lite_awprot  (s0_noc_axi4lite_awprot ),
      .s0_noc_axi4lite_arprot  (s0_noc_axi4lite_arprot ),
      .s0_noc_axi4lite_wstrb   (s0_noc_axi4lite_wstrb  ),
      .s0_axi4_awaddr          (s0_axi4_awaddr         ),
      .s0_axi4_awburst         (s0_axi4_awburst        ),
      .s0_axi4_awid            (s0_axi4_awid           ),
      .s0_axi4_awlen           (s0_axi4_awlen          ),
      .s0_axi4_awlock          (s0_axi4_awlock         ),
      .s0_axi4_awqos           (s0_axi4_awqos          ),
      .s0_axi4_awsize          (s0_axi4_awsize         ),
      .s0_axi4_awvalid         (s0_axi4_awvalid        ),
      .s0_axi4_awuser          (s0_axi4_awuser         ),
      .s0_axi4_awprot          (s0_axi4_awprot         ),
      .s0_axi4_awready         (s0_axi4_awready        ),
      .s0_axi4_araddr          (s0_axi4_araddr         ),
      .s0_axi4_arburst         (s0_axi4_arburst        ),
      .s0_axi4_arid            (s0_axi4_arid           ),
      .s0_axi4_arlen           (s0_axi4_arlen          ),
      .s0_axi4_arlock          (s0_axi4_arlock         ),
      .s0_axi4_arqos           (s0_axi4_arqos          ),
      .s0_axi4_arsize          (s0_axi4_arsize         ),
      .s0_axi4_arvalid         (s0_axi4_arvalid        ),
      .s0_axi4_aruser          (s0_axi4_aruser         ),
      .s0_axi4_arprot          (s0_axi4_arprot         ),
      .s0_axi4_arready         (s0_axi4_arready        ),
      .s0_axi4_wdata           (s0_axi4_wdata          ),
      .s0_axi4_wstrb           (s0_axi4_wstrb          ),
      .s0_axi4_wlast           (s0_axi4_wlast          ),
      .s0_axi4_wvalid          (s0_axi4_wvalid         ),
      .s0_axi4_wready          (s0_axi4_wready         ),
      .s0_axi4_bready          (s0_axi4_bready         ),
      .s0_axi4_bid             (s0_axi4_bid            ),
      .s0_axi4_bresp           (s0_axi4_bresp          ),
      .s0_axi4_bvalid          (s0_axi4_bvalid         ),
      .s0_axi4_rready          (s0_axi4_rready         ),
      .s0_axi4_rdata           (s0_axi4_rdata          ),
      .s0_axi4_rid             (s0_axi4_rid            ),
      .s0_axi4_rlast           (s0_axi4_rlast          ),
      .s0_axi4_rresp           (s0_axi4_rresp          ),
      .s0_axi4_rvalid          (s0_axi4_rvalid         ),
      .noc_aclk_0              (noc_aclk_0             ),
      .noc_rst_n_0             (noc_rst_n_0            ),
      .s0_axi4_wuser           (s0_axi4_wuser          ),
      .s0_axi4_ruser           (s0_axi4_ruser          ),
      .mem_0_cs                (mem_0_cs               ),
      .mem_0_ca                (mem_0_ca               ),
      .mem_0_cke               (mem_0_cke              ),
      .mem_0_dq                (mem_0_dq               ),
      .mem_0_dqs_t             (mem_0_dqs_t            ),
      .mem_0_dqs_c             (mem_0_dqs_c            ),
      .mem_0_dmi               (mem_0_dmi              ),
      .mem_0_ck_t              (mem_0_ck_t             ),
      .mem_0_ck_c              (mem_0_ck_c             ),
      .mem_0_reset_n           (mem_0_reset_n          ),
      .oct_rzqin_0             (oct_rzqin_0            ),
      .ref_clk                 (ref_clk                )
   );
endmodule


