	emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4 u0 (
		.s0_noc_axi4lite_clock   (_connected_to_s0_noc_axi4lite_clock_),   //  output,    width = 1, io96b0_to_hps.ch0_axil_clk
		.s0_noc_axi4lite_reset_n (_connected_to_s0_noc_axi4lite_reset_n_), //  output,    width = 1,              .ch0_axil_reset_n
		.s0_noc_axi4lite_awaddr  (_connected_to_s0_noc_axi4lite_awaddr_),  //   input,   width = 27,              .ch0_axil_awaddr
		.s0_noc_axi4lite_awvalid (_connected_to_s0_noc_axi4lite_awvalid_), //   input,    width = 1,              .ch0_axil_awvalid
		.s0_noc_axi4lite_awready (_connected_to_s0_noc_axi4lite_awready_), //  output,    width = 1,              .ch0_axil_awready
		.s0_noc_axi4lite_araddr  (_connected_to_s0_noc_axi4lite_araddr_),  //   input,   width = 27,              .ch0_axil_araddr
		.s0_noc_axi4lite_arvalid (_connected_to_s0_noc_axi4lite_arvalid_), //   input,    width = 1,              .ch0_axil_arvalid
		.s0_noc_axi4lite_arready (_connected_to_s0_noc_axi4lite_arready_), //  output,    width = 1,              .ch0_axil_arready
		.s0_noc_axi4lite_wdata   (_connected_to_s0_noc_axi4lite_wdata_),   //   input,   width = 32,              .ch0_axil_wdata
		.s0_noc_axi4lite_wvalid  (_connected_to_s0_noc_axi4lite_wvalid_),  //   input,    width = 1,              .ch0_axil_wvalid
		.s0_noc_axi4lite_wready  (_connected_to_s0_noc_axi4lite_wready_),  //  output,    width = 1,              .ch0_axil_wready
		.s0_noc_axi4lite_rresp   (_connected_to_s0_noc_axi4lite_rresp_),   //  output,    width = 2,              .ch0_axil_rresp
		.s0_noc_axi4lite_rdata   (_connected_to_s0_noc_axi4lite_rdata_),   //  output,   width = 32,              .ch0_axil_rdata
		.s0_noc_axi4lite_rvalid  (_connected_to_s0_noc_axi4lite_rvalid_),  //  output,    width = 1,              .ch0_axil_rvalid
		.s0_noc_axi4lite_rready  (_connected_to_s0_noc_axi4lite_rready_),  //   input,    width = 1,              .ch0_axil_rready
		.s0_noc_axi4lite_bresp   (_connected_to_s0_noc_axi4lite_bresp_),   //  output,    width = 2,              .ch0_axil_bresp
		.s0_noc_axi4lite_bvalid  (_connected_to_s0_noc_axi4lite_bvalid_),  //  output,    width = 1,              .ch0_axil_bvalid
		.s0_noc_axi4lite_bready  (_connected_to_s0_noc_axi4lite_bready_),  //   input,    width = 1,              .ch0_axil_bready
		.s0_noc_axi4lite_awprot  (_connected_to_s0_noc_axi4lite_awprot_),  //   input,    width = 3,              .ch0_axil_awprot
		.s0_noc_axi4lite_arprot  (_connected_to_s0_noc_axi4lite_arprot_),  //   input,    width = 3,              .ch0_axil_arprot
		.s0_noc_axi4lite_wstrb   (_connected_to_s0_noc_axi4lite_wstrb_),   //   input,    width = 4,              .ch0_axil_wstrb
		.s0_axi4_awaddr          (_connected_to_s0_axi4_awaddr_),          //   input,   width = 40,              .axi4_ch0_awaddr
		.s0_axi4_awburst         (_connected_to_s0_axi4_awburst_),         //   input,    width = 2,              .axi4_ch0_awburst
		.s0_axi4_awid            (_connected_to_s0_axi4_awid_),            //   input,    width = 7,              .axi4_ch0_awid
		.s0_axi4_awlen           (_connected_to_s0_axi4_awlen_),           //   input,    width = 8,              .axi4_ch0_awlen
		.s0_axi4_awlock          (_connected_to_s0_axi4_awlock_),          //   input,    width = 1,              .axi4_ch0_awlock
		.s0_axi4_awqos           (_connected_to_s0_axi4_awqos_),           //   input,    width = 4,              .axi4_ch0_awqos
		.s0_axi4_awsize          (_connected_to_s0_axi4_awsize_),          //   input,    width = 3,              .axi4_ch0_awsize
		.s0_axi4_awvalid         (_connected_to_s0_axi4_awvalid_),         //   input,    width = 1,              .axi4_ch0_awvalid
		.s0_axi4_awuser          (_connected_to_s0_axi4_awuser_),          //   input,   width = 14,              .axi4_ch0_awuser
		.s0_axi4_awprot          (_connected_to_s0_axi4_awprot_),          //   input,    width = 3,              .axi4_ch0_awprot
		.s0_axi4_awready         (_connected_to_s0_axi4_awready_),         //  output,    width = 1,              .axi4_ch0_awready
		.s0_axi4_araddr          (_connected_to_s0_axi4_araddr_),          //   input,   width = 40,              .axi4_ch0_araddr
		.s0_axi4_arburst         (_connected_to_s0_axi4_arburst_),         //   input,    width = 2,              .axi4_ch0_arburst
		.s0_axi4_arid            (_connected_to_s0_axi4_arid_),            //   input,    width = 7,              .axi4_ch0_arid
		.s0_axi4_arlen           (_connected_to_s0_axi4_arlen_),           //   input,    width = 8,              .axi4_ch0_arlen
		.s0_axi4_arlock          (_connected_to_s0_axi4_arlock_),          //   input,    width = 1,              .axi4_ch0_arlock
		.s0_axi4_arqos           (_connected_to_s0_axi4_arqos_),           //   input,    width = 4,              .axi4_ch0_arqos
		.s0_axi4_arsize          (_connected_to_s0_axi4_arsize_),          //   input,    width = 3,              .axi4_ch0_arsize
		.s0_axi4_arvalid         (_connected_to_s0_axi4_arvalid_),         //   input,    width = 1,              .axi4_ch0_arvalid
		.s0_axi4_aruser          (_connected_to_s0_axi4_aruser_),          //   input,   width = 14,              .axi4_ch0_aruser
		.s0_axi4_arprot          (_connected_to_s0_axi4_arprot_),          //   input,    width = 3,              .axi4_ch0_arprot
		.s0_axi4_arready         (_connected_to_s0_axi4_arready_),         //  output,    width = 1,              .axi4_ch0_arready
		.s0_axi4_wdata           (_connected_to_s0_axi4_wdata_),           //   input,  width = 256,              .axi4_ch0_wdata
		.s0_axi4_wstrb           (_connected_to_s0_axi4_wstrb_),           //   input,   width = 32,              .axi4_ch0_wstrb
		.s0_axi4_wlast           (_connected_to_s0_axi4_wlast_),           //   input,    width = 1,              .axi4_ch0_wlast
		.s0_axi4_wvalid          (_connected_to_s0_axi4_wvalid_),          //   input,    width = 1,              .axi4_ch0_wvalid
		.s0_axi4_wready          (_connected_to_s0_axi4_wready_),          //  output,    width = 1,              .axi4_ch0_wready
		.s0_axi4_bready          (_connected_to_s0_axi4_bready_),          //   input,    width = 1,              .axi4_ch0_bready
		.s0_axi4_bid             (_connected_to_s0_axi4_bid_),             //  output,    width = 7,              .axi4_ch0_bid
		.s0_axi4_bresp           (_connected_to_s0_axi4_bresp_),           //  output,    width = 2,              .axi4_ch0_bresp
		.s0_axi4_bvalid          (_connected_to_s0_axi4_bvalid_),          //  output,    width = 1,              .axi4_ch0_bvalid
		.s0_axi4_rready          (_connected_to_s0_axi4_rready_),          //   input,    width = 1,              .axi4_ch0_rready
		.s0_axi4_rdata           (_connected_to_s0_axi4_rdata_),           //  output,  width = 256,              .axi4_ch0_rdata
		.s0_axi4_rid             (_connected_to_s0_axi4_rid_),             //  output,    width = 7,              .axi4_ch0_rid
		.s0_axi4_rlast           (_connected_to_s0_axi4_rlast_),           //  output,    width = 1,              .axi4_ch0_rlast
		.s0_axi4_rresp           (_connected_to_s0_axi4_rresp_),           //  output,    width = 2,              .axi4_ch0_rresp
		.s0_axi4_rvalid          (_connected_to_s0_axi4_rvalid_),          //  output,    width = 1,              .axi4_ch0_rvalid
		.noc_aclk_0              (_connected_to_noc_aclk_0_),              //  output,    width = 1,              .axi4_ch0_clk
		.noc_rst_n_0             (_connected_to_noc_rst_n_0_),             //  output,    width = 1,              .axi4_ch0_reset_n
		.s0_axi4_wuser           (_connected_to_s0_axi4_wuser_),           //   input,   width = 32,              .axi4_ch0_wuser
		.s0_axi4_ruser           (_connected_to_s0_axi4_ruser_),           //  output,   width = 32,              .axi4_ch0_ruser
		.mem_0_cs                (_connected_to_mem_0_cs_),                //  output,    width = 1,         mem_0.mem_cs
		.mem_0_ca                (_connected_to_mem_0_ca_),                //  output,    width = 6,              .mem_ca
		.mem_0_cke               (_connected_to_mem_0_cke_),               //  output,    width = 1,              .mem_cke
		.mem_0_dq                (_connected_to_mem_0_dq_),                //   inout,   width = 32,              .mem_dq
		.mem_0_dqs_t             (_connected_to_mem_0_dqs_t_),             //   inout,    width = 4,              .mem_dqs_t
		.mem_0_dqs_c             (_connected_to_mem_0_dqs_c_),             //   inout,    width = 4,              .mem_dqs_c
		.mem_0_dmi               (_connected_to_mem_0_dmi_),               //   inout,    width = 4,              .mem_dmi
		.mem_0_ck_t              (_connected_to_mem_0_ck_t_),              //  output,    width = 1,      mem_ck_0.mem_ck_t
		.mem_0_ck_c              (_connected_to_mem_0_ck_c_),              //  output,    width = 1,              .mem_ck_c
		.mem_0_reset_n           (_connected_to_mem_0_reset_n_),           //  output,    width = 1,   mem_reset_n.mem_reset_n
		.oct_rzqin_0             (_connected_to_oct_rzqin_0_),             //   input,    width = 1,         oct_0.oct_rzqin
		.ref_clk                 (_connected_to_ref_clk_)                  //   input,    width = 1,       ref_clk.clk
	);

