// emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_emif_io96b_cal_420_65qugki.v

// Generated using ACDS version 26.1 110

`timescale 1 ps / 1 ps
module emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_emif_io96b_cal_420_65qugki #(
		parameter NUM_CALBUS_PERIPHS = 1,
		parameter NUM_CALBUS_PLLS    = 0,
		parameter PORT_S_AXIL_MODE   = "HARD_PATH",
		parameter DEBUG_TOOLS_EN     = 0,
		parameter PORT_M_AXIL_ENABLE = 0
	) (
		output wire [1341:0]  periph_calbus_0,             //       calbus_periph_0.calbus,             Interface to periphery 0 - command
		input  wire [1314:0]  periph_calbus_readdata_0,    //                      .calbus_readdata,    Interface to periphery 0 - read data
		input  wire [32767:0] periph_calbus_param_table_0, //                      .calbus_param_table, Interface to periphery 0 - param table
		output wire [1341:0]  periph_calbus_1,             //       calbus_periph_1.calbus,             Interface to periphery 1 - command
		input  wire [1314:0]  periph_calbus_readdata_1,    //                      .calbus_readdata,    Interface to periphery 1 - read data
		input  wire [32767:0] periph_calbus_param_table_1, //                      .calbus_param_table, Interface to periphery 1 - param table
		output wire [57:0]    pll_calbus_0,                //          calbus_pll_0.calbus,             Interface to PLL 0 - command
		input  wire [31:0]    pll_calbus_readdata_0,       //                      .calbus_readdata,    Interface to PLL 0 - read data
		output wire [57:0]    pll_calbus_1,                //          calbus_pll_1.calbus,             Interface to PLL 1 - command
		input  wire [31:0]    pll_calbus_readdata_1,       //                      .calbus_readdata,    Interface to PLL 1 - read data
		output wire [57:0]    pll_calbus_2,                //          calbus_pll_2.calbus,             Interface to PLL 2 - command
		input  wire [31:0]    pll_calbus_readdata_2,       //                      .calbus_readdata,    Interface to PLL 2 - read data
		input  wire           s0_axi4lite_clk,             //       s0_axi4lite_clk.clk,                Axi-lite clock
		input  wire           s0_axi4lite_rst_n,           //     s0_axi4lite_rst_n.reset_n,            Axi-lite reset_n
		input  wire [26:0]    s0_axi4lite_awaddr,          //           s0_axi4lite.awaddr,             Axi-lite awaddr
		input  wire           s0_axi4lite_awvalid,         //                      .awvalid,            Axi-lite awvalid
		output wire           s0_axi4lite_awready,         //                      .awready,            Axi-lite awready
		input  wire [26:0]    s0_axi4lite_araddr,          //                      .araddr,             Axi-lite araddr
		input  wire           s0_axi4lite_arvalid,         //                      .arvalid,            Axi-lite arvalid
		output wire           s0_axi4lite_arready,         //                      .arready,            Axi-lite arready
		input  wire [31:0]    s0_axi4lite_wdata,           //                      .wdata,              Axi-lite wdata
		input  wire           s0_axi4lite_wvalid,          //                      .wvalid,             Axi-lite wvalid
		output wire           s0_axi4lite_wready,          //                      .wready,             Axi-lite wready
		output wire [1:0]     s0_axi4lite_rresp,           //                      .rresp,              Axi-lite rresp
		output wire [31:0]    s0_axi4lite_rdata,           //                      .rdata,              Axi-lite rdata
		output wire           s0_axi4lite_rvalid,          //                      .rvalid,             Axi-lite rvalid
		input  wire           s0_axi4lite_rready,          //                      .rready,             Axi-lite rready
		output wire [1:0]     s0_axi4lite_bresp,           //                      .bresp,              Axi-lite bresp
		output wire           s0_axi4lite_bvalid,          //                      .bvalid,             Axi-lite bvalid
		input  wire           s0_axi4lite_bready,          //                      .bready,             Axi-lite bready
		input  wire [2:0]     s0_axi4lite_awprot,          //                      .awprot,             Axi-lite awprot
		input  wire [2:0]     s0_axi4lite_arprot,          //                      .arprot,             Axi-lite arprot
		input  wire [3:0]     s0_axi4lite_wstrb,           //                      .wstrb,              Axi-lite wstrb
		output wire [26:0]    m0_axi4lite_awaddr,          //           m0_axi4lite.awaddr
		output wire           m0_axi4lite_awvalid,         //                      .awvalid
		input  wire           m0_axi4lite_awready,         //                      .awready
		output wire [26:0]    m0_axi4lite_araddr,          //                      .araddr
		output wire           m0_axi4lite_arvalid,         //                      .arvalid
		input  wire           m0_axi4lite_arready,         //                      .arready
		output wire [31:0]    m0_axi4lite_wdata,           //                      .wdata
		output wire           m0_axi4lite_wvalid,          //                      .wvalid
		input  wire           m0_axi4lite_wready,          //                      .wready
		input  wire [1:0]     m0_axi4lite_rresp,           //                      .rresp
		input  wire [31:0]    m0_axi4lite_rdata,           //                      .rdata
		input  wire           m0_axi4lite_rvalid,          //                      .rvalid
		output wire           m0_axi4lite_rready,          //                      .rready
		input  wire [1:0]     m0_axi4lite_bresp,           //                      .bresp
		input  wire           m0_axi4lite_bvalid,          //                      .bvalid
		output wire           m0_axi4lite_bready,          //                      .bready
		output wire [2:0]     m0_axi4lite_awprot,          //                      .awprot
		output wire [2:0]     m0_axi4lite_arprot,          //                      .arprot
		output wire [3:0]     m0_axi4lite_wstrb,           //                      .wstrb
		output wire           s0_noc_axi4lite_clk,         //   s0_noc_axi4lite_clk.clk
		output wire           s0_noc_axi4lite_rst_n,       // s0_noc_axi4lite_rst_n.reset_n
		input  wire [26:0]    s0_noc_axi4lite_awaddr,      //       s0_noc_axi4lite.awaddr
		input  wire           s0_noc_axi4lite_awvalid,     //                      .awvalid
		output wire           s0_noc_axi4lite_awready,     //                      .awready
		input  wire [26:0]    s0_noc_axi4lite_araddr,      //                      .araddr
		input  wire           s0_noc_axi4lite_arvalid,     //                      .arvalid
		output wire           s0_noc_axi4lite_arready,     //                      .arready
		input  wire [31:0]    s0_noc_axi4lite_wdata,       //                      .wdata
		input  wire           s0_noc_axi4lite_wvalid,      //                      .wvalid
		output wire           s0_noc_axi4lite_wready,      //                      .wready
		output wire [1:0]     s0_noc_axi4lite_rresp,       //                      .rresp
		output wire [31:0]    s0_noc_axi4lite_rdata,       //                      .rdata
		output wire           s0_noc_axi4lite_rvalid,      //                      .rvalid
		input  wire           s0_noc_axi4lite_rready,      //                      .rready
		output wire [1:0]     s0_noc_axi4lite_bresp,       //                      .bresp
		output wire           s0_noc_axi4lite_bvalid,      //                      .bvalid
		input  wire           s0_noc_axi4lite_bready,      //                      .bready
		input  wire [2:0]     s0_noc_axi4lite_awprot,      //                      .awprot
		input  wire [2:0]     s0_noc_axi4lite_arprot,      //                      .arprot
		input  wire [3:0]     s0_noc_axi4lite_wstrb,       //                      .wstrb
		input  wire           tniul_rst_n,                 //   s0_tniulite_reset_n.reset_n
		input  wire [7:0]     ls_to_cal,                   //                    ls.ls_to_cal
		output wire [7:0]     ls_from_cal,                 //                      .ls_from_cal
		input  wire           fbr_c2f_rst_n                //                      .fbr_c2f_rst_n
	);

	generate
		// If any of the display statements (or deliberately broken
		// instantiations) within this generate block triggers then this module
		// has been instantiated this module with a set of parameters different
		// from those it was generated for.  This will usually result in a
		// non-functioning system.
		if (NUM_CALBUS_PERIPHS != 1)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					num_calbus_periphs_check ( .error(1'b1) );
		end
		if (NUM_CALBUS_PLLS != 0)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					num_calbus_plls_check ( .error(1'b1) );
		end
		if (PORT_S_AXIL_MODE != "HARD_PATH")
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					port_s_axil_mode_check ( .error(1'b1) );
		end
		if (DEBUG_TOOLS_EN != 0)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					debug_tools_en_check ( .error(1'b1) );
		end
		if (PORT_M_AXIL_ENABLE != 0)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					port_m_axil_enable_check ( .error(1'b1) );
		end
	endgenerate

	emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki #(
		.NUM_CALBUS_PERIPHS (1),
		.NUM_CALBUS_PLLS    (0),
		.PORT_S_AXIL_MODE   ("HARD_PATH"),
		.DEBUG_TOOLS_EN     (0),
		.PORT_M_AXIL_ENABLE (0)
	) cal_0 (
		.periph_calbus_0             (periph_calbus_0),             //  output,   width = 1342,       calbus_periph_0.calbus
		.periph_calbus_readdata_0    (periph_calbus_readdata_0),    //   input,   width = 1315,                      .calbus_readdata
		.periph_calbus_param_table_0 (periph_calbus_param_table_0), //   input,  width = 32768,                      .calbus_param_table
		.periph_calbus_1             (periph_calbus_1),             //  output,   width = 1342,       calbus_periph_1.calbus
		.periph_calbus_readdata_1    (periph_calbus_readdata_1),    //   input,   width = 1315,                      .calbus_readdata
		.periph_calbus_param_table_1 (periph_calbus_param_table_1), //   input,  width = 32768,                      .calbus_param_table
		.pll_calbus_0                (pll_calbus_0),                //  output,     width = 58,          calbus_pll_0.calbus
		.pll_calbus_readdata_0       (pll_calbus_readdata_0),       //   input,     width = 32,                      .calbus_readdata
		.pll_calbus_1                (pll_calbus_1),                //  output,     width = 58,          calbus_pll_1.calbus
		.pll_calbus_readdata_1       (pll_calbus_readdata_1),       //   input,     width = 32,                      .calbus_readdata
		.pll_calbus_2                (pll_calbus_2),                //  output,     width = 58,          calbus_pll_2.calbus
		.pll_calbus_readdata_2       (pll_calbus_readdata_2),       //   input,     width = 32,                      .calbus_readdata
		.s0_axi4lite_clk             (s0_axi4lite_clk),             //   input,      width = 1,       s0_axi4lite_clk.clk
		.s0_axi4lite_rst_n           (s0_axi4lite_rst_n),           //   input,      width = 1,     s0_axi4lite_rst_n.reset_n
		.s0_axi4lite_awaddr          (s0_axi4lite_awaddr),          //   input,     width = 27,           s0_axi4lite.awaddr
		.s0_axi4lite_awvalid         (s0_axi4lite_awvalid),         //   input,      width = 1,                      .awvalid
		.s0_axi4lite_awready         (s0_axi4lite_awready),         //  output,      width = 1,                      .awready
		.s0_axi4lite_araddr          (s0_axi4lite_araddr),          //   input,     width = 27,                      .araddr
		.s0_axi4lite_arvalid         (s0_axi4lite_arvalid),         //   input,      width = 1,                      .arvalid
		.s0_axi4lite_arready         (s0_axi4lite_arready),         //  output,      width = 1,                      .arready
		.s0_axi4lite_wdata           (s0_axi4lite_wdata),           //   input,     width = 32,                      .wdata
		.s0_axi4lite_wvalid          (s0_axi4lite_wvalid),          //   input,      width = 1,                      .wvalid
		.s0_axi4lite_wready          (s0_axi4lite_wready),          //  output,      width = 1,                      .wready
		.s0_axi4lite_rresp           (s0_axi4lite_rresp),           //  output,      width = 2,                      .rresp
		.s0_axi4lite_rdata           (s0_axi4lite_rdata),           //  output,     width = 32,                      .rdata
		.s0_axi4lite_rvalid          (s0_axi4lite_rvalid),          //  output,      width = 1,                      .rvalid
		.s0_axi4lite_rready          (s0_axi4lite_rready),          //   input,      width = 1,                      .rready
		.s0_axi4lite_bresp           (s0_axi4lite_bresp),           //  output,      width = 2,                      .bresp
		.s0_axi4lite_bvalid          (s0_axi4lite_bvalid),          //  output,      width = 1,                      .bvalid
		.s0_axi4lite_bready          (s0_axi4lite_bready),          //   input,      width = 1,                      .bready
		.s0_axi4lite_awprot          (s0_axi4lite_awprot),          //   input,      width = 3,                      .awprot
		.s0_axi4lite_arprot          (s0_axi4lite_arprot),          //   input,      width = 3,                      .arprot
		.s0_axi4lite_wstrb           (s0_axi4lite_wstrb),           //   input,      width = 4,                      .wstrb
		.m0_axi4lite_awaddr          (m0_axi4lite_awaddr),          //  output,     width = 27,           m0_axi4lite.awaddr
		.m0_axi4lite_awvalid         (m0_axi4lite_awvalid),         //  output,      width = 1,                      .awvalid
		.m0_axi4lite_awready         (m0_axi4lite_awready),         //   input,      width = 1,                      .awready
		.m0_axi4lite_araddr          (m0_axi4lite_araddr),          //  output,     width = 27,                      .araddr
		.m0_axi4lite_arvalid         (m0_axi4lite_arvalid),         //  output,      width = 1,                      .arvalid
		.m0_axi4lite_arready         (m0_axi4lite_arready),         //   input,      width = 1,                      .arready
		.m0_axi4lite_wdata           (m0_axi4lite_wdata),           //  output,     width = 32,                      .wdata
		.m0_axi4lite_wvalid          (m0_axi4lite_wvalid),          //  output,      width = 1,                      .wvalid
		.m0_axi4lite_wready          (m0_axi4lite_wready),          //   input,      width = 1,                      .wready
		.m0_axi4lite_rresp           (m0_axi4lite_rresp),           //   input,      width = 2,                      .rresp
		.m0_axi4lite_rdata           (m0_axi4lite_rdata),           //   input,     width = 32,                      .rdata
		.m0_axi4lite_rvalid          (m0_axi4lite_rvalid),          //   input,      width = 1,                      .rvalid
		.m0_axi4lite_rready          (m0_axi4lite_rready),          //  output,      width = 1,                      .rready
		.m0_axi4lite_bresp           (m0_axi4lite_bresp),           //   input,      width = 2,                      .bresp
		.m0_axi4lite_bvalid          (m0_axi4lite_bvalid),          //   input,      width = 1,                      .bvalid
		.m0_axi4lite_bready          (m0_axi4lite_bready),          //  output,      width = 1,                      .bready
		.m0_axi4lite_awprot          (m0_axi4lite_awprot),          //  output,      width = 3,                      .awprot
		.m0_axi4lite_arprot          (m0_axi4lite_arprot),          //  output,      width = 3,                      .arprot
		.m0_axi4lite_wstrb           (m0_axi4lite_wstrb),           //  output,      width = 4,                      .wstrb
		.s0_noc_axi4lite_clk         (s0_noc_axi4lite_clk),         //  output,      width = 1,   s0_noc_axi4lite_clk.clk
		.s0_noc_axi4lite_rst_n       (s0_noc_axi4lite_rst_n),       //  output,      width = 1, s0_noc_axi4lite_rst_n.reset_n
		.s0_noc_axi4lite_awaddr      (s0_noc_axi4lite_awaddr),      //   input,     width = 27,       s0_noc_axi4lite.awaddr
		.s0_noc_axi4lite_awvalid     (s0_noc_axi4lite_awvalid),     //   input,      width = 1,                      .awvalid
		.s0_noc_axi4lite_awready     (s0_noc_axi4lite_awready),     //  output,      width = 1,                      .awready
		.s0_noc_axi4lite_araddr      (s0_noc_axi4lite_araddr),      //   input,     width = 27,                      .araddr
		.s0_noc_axi4lite_arvalid     (s0_noc_axi4lite_arvalid),     //   input,      width = 1,                      .arvalid
		.s0_noc_axi4lite_arready     (s0_noc_axi4lite_arready),     //  output,      width = 1,                      .arready
		.s0_noc_axi4lite_wdata       (s0_noc_axi4lite_wdata),       //   input,     width = 32,                      .wdata
		.s0_noc_axi4lite_wvalid      (s0_noc_axi4lite_wvalid),      //   input,      width = 1,                      .wvalid
		.s0_noc_axi4lite_wready      (s0_noc_axi4lite_wready),      //  output,      width = 1,                      .wready
		.s0_noc_axi4lite_rresp       (s0_noc_axi4lite_rresp),       //  output,      width = 2,                      .rresp
		.s0_noc_axi4lite_rdata       (s0_noc_axi4lite_rdata),       //  output,     width = 32,                      .rdata
		.s0_noc_axi4lite_rvalid      (s0_noc_axi4lite_rvalid),      //  output,      width = 1,                      .rvalid
		.s0_noc_axi4lite_rready      (s0_noc_axi4lite_rready),      //   input,      width = 1,                      .rready
		.s0_noc_axi4lite_bresp       (s0_noc_axi4lite_bresp),       //  output,      width = 2,                      .bresp
		.s0_noc_axi4lite_bvalid      (s0_noc_axi4lite_bvalid),      //  output,      width = 1,                      .bvalid
		.s0_noc_axi4lite_bready      (s0_noc_axi4lite_bready),      //   input,      width = 1,                      .bready
		.s0_noc_axi4lite_awprot      (s0_noc_axi4lite_awprot),      //   input,      width = 3,                      .awprot
		.s0_noc_axi4lite_arprot      (s0_noc_axi4lite_arprot),      //   input,      width = 3,                      .arprot
		.s0_noc_axi4lite_wstrb       (s0_noc_axi4lite_wstrb),       //   input,      width = 4,                      .wstrb
		.tniul_rst_n                 (tniul_rst_n),                 //   input,      width = 1,   s0_tniulite_reset_n.reset_n
		.ls_to_cal                   (ls_to_cal),                   //   input,      width = 8,                    ls.ls_to_cal
		.ls_from_cal                 (ls_from_cal),                 //  output,      width = 8,                      .ls_from_cal
		.fbr_c2f_rst_n               (fbr_c2f_rst_n)                //   input,      width = 1,                      .fbr_c2f_rst_n
	);

endmodule
