# Ch415 epoch descriptor table (124 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 124 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 1772 12288 480 sh3_zsrt139f160_tex_lpddr.mem 0x200000 262144 0x42d367ae feeder_sh3_zsrt139f160.mem 44 4 0 sh3_zsrt139f160_pal.mem 0x60778774
1 6822 11264 480 sh3_zsrt139f161_tex_lpddr.mem 0x200000 262144 0x55070afa feeder_sh3_zsrt139f161.mem 1547 171 0 sh3_zsrt139f161_pal.mem 0x32ed74c4
2 8151 11264 480 sh3_zsrt139f161_tex_lpddr.mem 0x200000 262144 0x55070afa feeder_sh3_zsrt139f162.mem 1772 196 1 sh3_zsrt139f161_pal.mem 0x32ed74c4
3 12757 10240 480 sh3_zsrt139f163_tex_lpddr.mem 0x200000 262144 0x26a88b77 feeder_sh3_zsrt139f163.mem 350 38 0 sh3_zsrt139f163_pal.mem 0x3cd88c98
4 15277 12288 480 sh3_zsrt139f164_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139f164.mem 1277 141 0 sh3_zsrt139f164_pal.mem 0x4812d6f2
5 15277 12288 480 sh3_zsrt139f164_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139f165.mem 107 11 1 sh3_zsrt139f164_pal.mem 0x4812d6f2
6 15931 12288 480 sh3_zsrt139f164_tex_lpddr.mem 0x200000 262144 0x835dceb6 feeder_sh3_zsrt139f166.mem 620 68 1 sh3_zsrt139f164_pal.mem 0x4812d6f2
7 20246 11264 480 sh3_zsrt139f167_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139f167.mem 224 24 0 sh3_zsrt139f167_pal.mem 0x5cbf8bb4
8 20792 11264 480 sh3_zsrt139f167_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139f168.mem 593 65 1 sh3_zsrt139f167_pal.mem 0x5cbf8bb4
9 21386 11264 480 sh3_zsrt139f167_tex_lpddr.mem 0x200000 262144 0x95a83cbc feeder_sh3_zsrt139f169.mem 332 36 1 sh3_zsrt139f167_pal.mem 0x5cbf8bb4
10 30461 10240 480 sh3_zsrt139f1610_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1610.mem 53 5 0 sh3_zsrt139f1610_pal.mem 0x47405cb0
11 31915 10240 480 sh3_zsrt139f1610_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1611.mem 359 39 1 sh3_zsrt139f1610_pal.mem 0x47405cb0
12 33303 10240 480 sh3_zsrt139f1610_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1612.mem 602 66 1 sh3_zsrt139f1610_pal.mem 0x47405cb0
13 34605 10240 480 sh3_zsrt139f1610_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1613.mem 944 104 1 sh3_zsrt139f1610_pal.mem 0x47405cb0
14 35907 10240 480 sh3_zsrt139f1610_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1614.mem 557 61 1 sh3_zsrt139f1610_pal.mem 0x47405cb0
15 37209 10240 480 sh3_zsrt139f1610_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1615.mem 737 81 1 sh3_zsrt139f1610_pal.mem 0x47405cb0
16 38511 10240 480 sh3_zsrt139f1610_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1616.mem 1115 123 1 sh3_zsrt139f1610_pal.mem 0x47405cb0
17 71148 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1617.mem 728 80 0 sh3_zsrt139f1617_pal.mem 0x43ece1ae
18 71787 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1618.mem 341 37 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
19 72426 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1619.mem 296 32 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
20 73065 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1620.mem 530 58 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
21 73704 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1621.mem 683 75 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
22 74343 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1622.mem 422 46 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
23 74982 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1623.mem 665 73 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
24 75621 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1624.mem 1151 127 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
25 76260 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1625.mem 566 62 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
26 76899 10240 480 sh3_zsrt139f1617_tex_lpddr.mem 0x200000 262144 0xa727234d feeder_sh3_zsrt139f1626.mem 638 70 1 sh3_zsrt139f1617_pal.mem 0x43ece1ae
27 78319 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1627.mem 458 50 0 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
28 82720 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1628.mem 476 52 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
29 83323 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1629.mem 845 93 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
30 83944 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1630.mem 629 69 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
31 84565 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1631.mem 728 80 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
32 85186 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1632.mem 476 52 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
33 85807 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1633.mem 854 94 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
34 86428 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1634.mem 602 66 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
35 87049 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1635.mem 395 43 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
36 88918 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1636.mem 26 2 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
37 89548 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1637.mem 2042 226 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
38 89548 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1638.mem 899 99 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
39 90187 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1639.mem 1745 193 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
40 90187 9216 480 sh3_zsrt139f1627_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1640.mem 485 53 1 sh3_zsrt139f1627_pal.mem 0x5dfce0a2
41 91678 9216 480 sh3_zsrt139f1641_tex_lpddr.mem 0x200000 262144 0xfbdeaa32 feeder_sh3_zsrt139f1641.mem 188 20 0 sh3_zsrt139f1641_pal.mem 0x181b2ac2
42 114431 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1642.mem 1376 152 0 sh3_zsrt139f1642_pal.mem 0x47097d4c
43 115016 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1643.mem 2042 226 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
44 115016 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1644.mem 170 18 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
45 115655 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1645.mem 2042 226 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
46 115655 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1646.mem 224 24 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
47 116351 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1647.mem 1421 157 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
48 117050 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1648.mem 1457 161 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
49 117599 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1649.mem 1988 220 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
50 118238 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1650.mem 1547 171 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
51 118877 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1651.mem 1187 131 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
52 119471 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1652.mem 503 55 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
53 120110 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1653.mem 1331 147 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
54 120749 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1654.mem 1502 166 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
55 120749 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1655.mem 575 63 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
56 121388 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1656.mem 1070 118 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
57 122027 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1657.mem 863 95 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
58 122600 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1658.mem 791 87 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
59 123239 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1659.mem 152 16 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
60 123869 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1660.mem 260 28 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
61 124508 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1661.mem 314 34 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
62 125147 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1662.mem 62 6 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
63 125786 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1663.mem 359 39 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
64 126434 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1664.mem 359 39 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
65 126968 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1665.mem 557 61 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
66 127607 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1666.mem 467 51 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
67 128246 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1667.mem 449 49 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
68 128885 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1668.mem 62 6 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
69 129389 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1669.mem 1205 133 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
70 130028 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1670.mem 1025 113 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
71 130667 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1671.mem 1673 185 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
72 130667 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1672.mem 233 25 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
73 131306 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1673.mem 485 53 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
74 131306 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1674.mem 557 61 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
75 131306 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1675.mem 521 57 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
76 131306 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1676.mem 683 75 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
77 131945 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1677.mem 1376 152 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
78 132584 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1678.mem 944 104 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
79 133262 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1679.mem 620 68 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
80 133262 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1680.mem 53 5 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
81 135869 8192 480 sh3_zsrt139f1642_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrt139f1681.mem 26 2 1 sh3_zsrt139f1642_pal.mem 0x47097d4c
82 144890 12288 480 sh3_zsrt139f1682_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrt139f1682.mem 179 19 0 sh3_zsrt139f1682_pal.mem 0x3e849a98
83 145712 12288 480 sh3_zsrt139f1682_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrt139f1683.mem 116 12 1 sh3_zsrt139f1682_pal.mem 0x3e849a98
84 146205 11264 480 sh3_zsrt139f1684_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1684.mem 1052 116 0 sh3_zsrt139f1684_pal.mem 0xfd978fd9
85 146630 11264 480 sh3_zsrt139f1684_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1685.mem 278 30 1 sh3_zsrt139f1684_pal.mem 0xfd978fd9
86 147068 11264 480 sh3_zsrt139f1684_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1686.mem 332 36 1 sh3_zsrt139f1684_pal.mem 0xfd978fd9
87 147480 11264 480 sh3_zsrt139f1687_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1687.mem 710 78 0 sh3_zsrt139f1687_pal.mem 0xd5ed05ff
88 147888 11264 480 sh3_zsrt139f1687_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1688.mem 638 70 1 sh3_zsrt139f1687_pal.mem 0xd5ed05ff
89 148264 11264 480 sh3_zsrt139f1687_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1689.mem 1016 112 1 sh3_zsrt139f1687_pal.mem 0xd5ed05ff
90 148919 11264 480 sh3_zsrt139f1690_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1690.mem 1043 115 0 sh3_zsrt139f1690_pal.mem 0xcdf8a4d8
91 149509 11264 480 sh3_zsrt139f1690_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1691.mem 854 94 1 sh3_zsrt139f1690_pal.mem 0xcdf8a4d8
92 150125 11264 480 sh3_zsrt139f1690_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1692.mem 701 77 1 sh3_zsrt139f1690_pal.mem 0xcdf8a4d8
93 150741 11264 480 sh3_zsrt139f1690_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1693.mem 701 77 1 sh3_zsrt139f1690_pal.mem 0xcdf8a4d8
94 151344 11264 480 sh3_zsrt139f1690_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1694.mem 377 41 1 sh3_zsrt139f1690_pal.mem 0xcdf8a4d8
95 152021 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1695.mem 314 34 0 sh3_zsrt139f1695_pal.mem 0xc6784386
96 152420 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1696.mem 269 29 1 sh3_zsrt139f1695_pal.mem 0xc6784386
97 152806 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1697.mem 377 41 1 sh3_zsrt139f1695_pal.mem 0xc6784386
98 153218 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1698.mem 179 19 1 sh3_zsrt139f1695_pal.mem 0xc6784386
99 153643 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f1699.mem 44 4 1 sh3_zsrt139f1695_pal.mem 0xc6784386
100 154029 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f16100.mem 359 39 1 sh3_zsrt139f1695_pal.mem 0xc6784386
101 154428 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f16101.mem 206 22 1 sh3_zsrt139f1695_pal.mem 0xc6784386
102 154853 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f16102.mem 206 22 1 sh3_zsrt139f1695_pal.mem 0xc6784386
103 155265 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f16103.mem 188 20 1 sh3_zsrt139f1695_pal.mem 0xc6784386
104 155664 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f16104.mem 98 10 1 sh3_zsrt139f1695_pal.mem 0xc6784386
105 156063 11264 480 sh3_zsrt139f1695_tex_lpddr.mem 0x200000 262144 0xeadeb012 feeder_sh3_zsrt139f16105.mem 89 9 1 sh3_zsrt139f1695_pal.mem 0xc6784386
106 156566 10240 480 sh3_zsrt139f16106_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16106.mem 1268 140 0 sh3_zsrt139f16106_pal.mem 0x00fd9028
107 157273 10240 480 sh3_zsrt139f16106_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16107.mem 1106 122 1 sh3_zsrt139f16106_pal.mem 0x00fd9028
108 157967 10240 480 sh3_zsrt139f16106_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16108.mem 755 83 1 sh3_zsrt139f16106_pal.mem 0x00fd9028
109 158674 10240 480 sh3_zsrt139f16106_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16109.mem 809 89 1 sh3_zsrt139f16106_pal.mem 0x00fd9028
110 159420 10240 480 sh3_zsrt139f16106_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16110.mem 503 55 1 sh3_zsrt139f16106_pal.mem 0x00fd9028
111 160114 10240 480 sh3_zsrt139f16106_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16111.mem 116 12 1 sh3_zsrt139f16106_pal.mem 0x00fd9028
112 160331 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16112.mem 368 40 0 sh3_zsrt139f16112_pal.mem 0xd8d19684
113 160769 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16113.mem 287 31 1 sh3_zsrt139f16112_pal.mem 0xd8d19684
114 161168 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16114.mem 440 48 1 sh3_zsrt139f16112_pal.mem 0xd8d19684
115 161567 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16115.mem 296 32 1 sh3_zsrt139f16112_pal.mem 0xd8d19684
116 162300 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16116.mem 395 43 1 sh3_zsrt139f16112_pal.mem 0xd8d19684
117 162725 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16117.mem 377 41 1 sh3_zsrt139f16112_pal.mem 0xd8d19684
118 163163 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16118.mem 251 27 1 sh3_zsrt139f16112_pal.mem 0xd8d19684
119 163575 10240 480 sh3_zsrt139f16112_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16119.mem 314 34 1 sh3_zsrt139f16112_pal.mem 0xd8d19684
120 164204 10240 480 sh3_zsrt139f16120_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16120.mem 647 71 0 sh3_zsrt139f16120_pal.mem 0xaa4e7e05
121 164950 10240 480 sh3_zsrt139f16120_tex_lpddr.mem 0x200000 262144 0xb710940e feeder_sh3_zsrt139f16121.mem 377 41 1 sh3_zsrt139f16120_pal.mem 0xaa4e7e05
122 175995 12288 480 sh3_zsrt139f16122_tex_lpddr.mem 0x200000 262144 0xf2553358 feeder_sh3_zsrt139f16122.mem 395 43 0 sh3_zsrt139f16122_pal.mem 0x56ebf1d1
123 176446 12288 480 sh3_zsrt139f16122_tex_lpddr.mem 0x200000 262144 0xf2553358 feeder_sh3_zsrt139f16123.mem 251 27 1 sh3_zsrt139f16122_pal.mem 0x56ebf1d1
