# Ch407 epoch descriptor table (147 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 147 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 198075 10240 480 sh3_zsrt139d50_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d50.mem 485 53 0 sh3_zsrt139d50_pal.mem 0x158afe76
1 198092 10240 480 sh3_zsrt139d51_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d51.mem 665 73 1 sh3_zsrt139d51_pal.mem 0x158afe76
2 198092 10240 480 sh3_zsrt139d52_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d52.mem 215 23 1 sh3_zsrt139d52_pal.mem 0x158afe76
3 198092 10240 480 sh3_zsrt139d53_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d53.mem 458 50 1 sh3_zsrt139d53_pal.mem 0x158afe76
4 198092 10240 480 sh3_zsrt139d54_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d54.mem 431 47 1 sh3_zsrt139d54_pal.mem 0x158afe76
5 198092 10240 480 sh3_zsrt139d55_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d55.mem 395 43 1 sh3_zsrt139d55_pal.mem 0x158afe76
6 198092 10240 480 sh3_zsrt139d56_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d56.mem 206 22 1 sh3_zsrt139d56_pal.mem 0x158afe76
7 198092 10240 480 sh3_zsrt139d57_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d57.mem 170 18 1 sh3_zsrt139d57_pal.mem 0x158afe76
8 198092 10240 480 sh3_zsrt139d58_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d58.mem 242 26 1 sh3_zsrt139d58_pal.mem 0x158afe76
9 198092 10240 480 sh3_zsrt139d59_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d59.mem 359 39 1 sh3_zsrt139d59_pal.mem 0x158afe76
10 198092 10240 480 sh3_zsrt139d510_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d510.mem 323 35 1 sh3_zsrt139d510_pal.mem 0x158afe76
11 198092 10240 480 sh3_zsrt139d511_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d511.mem 215 23 1 sh3_zsrt139d511_pal.mem 0x158afe76
12 198092 10240 480 sh3_zsrt139d512_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d512.mem 314 34 1 sh3_zsrt139d512_pal.mem 0x158afe76
13 198092 10240 480 sh3_zsrt139d513_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d513.mem 278 30 1 sh3_zsrt139d513_pal.mem 0x158afe76
14 198092 10240 480 sh3_zsrt139d514_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d514.mem 116 12 1 sh3_zsrt139d514_pal.mem 0x158afe76
15 198092 10240 480 sh3_zsrt139d515_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d515.mem 197 21 1 sh3_zsrt139d515_pal.mem 0x158afe76
16 198092 10240 480 sh3_zsrt139d516_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d516.mem 458 50 1 sh3_zsrt139d516_pal.mem 0x158afe76
17 198092 10240 480 sh3_zsrt139d517_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d517.mem 269 29 1 sh3_zsrt139d517_pal.mem 0x158afe76
18 198092 10240 480 sh3_zsrt139d518_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d518.mem 206 22 1 sh3_zsrt139d518_pal.mem 0x158afe76
19 198092 10240 480 sh3_zsrt139d519_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d519.mem 323 35 1 sh3_zsrt139d519_pal.mem 0x158afe76
20 198092 10240 480 sh3_zsrt139d520_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d520.mem 494 54 1 sh3_zsrt139d520_pal.mem 0x158afe76
21 198092 10240 480 sh3_zsrt139d521_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d521.mem 566 62 1 sh3_zsrt139d521_pal.mem 0x158afe76
22 198092 10240 480 sh3_zsrt139d522_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d522.mem 287 31 1 sh3_zsrt139d522_pal.mem 0x158afe76
23 198092 10240 480 sh3_zsrt139d523_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d523.mem 260 28 1 sh3_zsrt139d523_pal.mem 0x158afe76
24 198092 10240 480 sh3_zsrt139d524_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d524.mem 89 9 1 sh3_zsrt139d524_pal.mem 0x158afe76
25 198092 10240 480 sh3_zsrt139d525_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d525.mem 359 39 1 sh3_zsrt139d525_pal.mem 0x158afe76
26 198092 10240 480 sh3_zsrt139d526_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d526.mem 539 59 1 sh3_zsrt139d526_pal.mem 0x158afe76
27 198092 10240 480 sh3_zsrt139d527_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d527.mem 323 35 1 sh3_zsrt139d527_pal.mem 0x158afe76
28 198092 10240 480 sh3_zsrt139d528_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d528.mem 179 19 1 sh3_zsrt139d528_pal.mem 0x158afe76
29 198092 10240 480 sh3_zsrt139d529_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d529.mem 494 54 1 sh3_zsrt139d529_pal.mem 0x158afe76
30 198092 10240 480 sh3_zsrt139d530_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d530.mem 431 47 1 sh3_zsrt139d530_pal.mem 0x158afe76
31 198092 10240 480 sh3_zsrt139d531_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d531.mem 107 11 1 sh3_zsrt139d531_pal.mem 0x158afe76
32 198092 10240 480 sh3_zsrt139d532_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d532.mem 278 30 1 sh3_zsrt139d532_pal.mem 0x158afe76
33 198092 10240 480 sh3_zsrt139d533_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d533.mem 413 45 1 sh3_zsrt139d533_pal.mem 0x158afe76
34 198092 10240 480 sh3_zsrt139d534_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d534.mem 98 10 1 sh3_zsrt139d534_pal.mem 0x158afe76
35 198092 10240 480 sh3_zsrt139d535_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d535.mem 278 30 1 sh3_zsrt139d535_pal.mem 0x158afe76
36 198092 10240 480 sh3_zsrt139d536_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d536.mem 62 6 1 sh3_zsrt139d536_pal.mem 0x158afe76
37 198092 10240 480 sh3_zsrt139d537_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d537.mem 98 10 1 sh3_zsrt139d537_pal.mem 0x158afe76
38 198092 10240 480 sh3_zsrt139d538_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d538.mem 251 27 1 sh3_zsrt139d538_pal.mem 0x158afe76
39 198092 10240 480 sh3_zsrt139d539_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d539.mem 215 23 1 sh3_zsrt139d539_pal.mem 0x158afe76
40 198092 10240 480 sh3_zsrt139d540_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d540.mem 215 23 1 sh3_zsrt139d540_pal.mem 0x158afe76
41 198092 10240 480 sh3_zsrt139d541_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d541.mem 107 11 1 sh3_zsrt139d541_pal.mem 0x158afe76
42 198092 10240 480 sh3_zsrt139d542_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d542.mem 152 16 1 sh3_zsrt139d542_pal.mem 0x158afe76
43 198092 10240 480 sh3_zsrt139d543_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d543.mem 278 30 1 sh3_zsrt139d543_pal.mem 0x158afe76
44 198092 10240 480 sh3_zsrt139d544_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d544.mem 503 55 1 sh3_zsrt139d544_pal.mem 0x158afe76
45 198092 10240 480 sh3_zsrt139d545_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d545.mem 62 6 1 sh3_zsrt139d545_pal.mem 0x158afe76
46 198092 10240 480 sh3_zsrt139d546_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d546.mem 98 10 1 sh3_zsrt139d546_pal.mem 0x158afe76
47 198092 10240 480 sh3_zsrt139d547_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d547.mem 260 28 1 sh3_zsrt139d547_pal.mem 0x158afe76
48 198092 10240 480 sh3_zsrt139d548_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d548.mem 116 12 1 sh3_zsrt139d548_pal.mem 0x158afe76
49 198092 10240 480 sh3_zsrt139d549_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d549.mem 323 35 1 sh3_zsrt139d549_pal.mem 0x158afe76
50 198092 10240 480 sh3_zsrt139d550_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d550.mem 242 26 1 sh3_zsrt139d550_pal.mem 0x158afe76
51 198092 10240 480 sh3_zsrt139d551_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d551.mem 233 25 1 sh3_zsrt139d551_pal.mem 0x158afe76
52 198092 10240 480 sh3_zsrt139d552_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d552.mem 233 25 1 sh3_zsrt139d552_pal.mem 0x158afe76
53 198092 10240 480 sh3_zsrt139d553_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d553.mem 152 16 1 sh3_zsrt139d553_pal.mem 0x158afe76
54 198092 10240 480 sh3_zsrt139d554_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d554.mem 449 49 1 sh3_zsrt139d554_pal.mem 0x158afe76
55 198092 10240 480 sh3_zsrt139d555_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d555.mem 125 13 1 sh3_zsrt139d555_pal.mem 0x158afe76
56 198092 10240 480 sh3_zsrt139d556_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d556.mem 62 6 1 sh3_zsrt139d556_pal.mem 0x158afe76
57 198092 10240 480 sh3_zsrt139d557_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d557.mem 53 5 1 sh3_zsrt139d557_pal.mem 0x158afe76
58 198092 10240 480 sh3_zsrt139d558_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d558.mem 125 13 1 sh3_zsrt139d558_pal.mem 0x158afe76
59 198092 10240 480 sh3_zsrt139d559_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d559.mem 125 13 1 sh3_zsrt139d559_pal.mem 0x158afe76
60 198092 10240 480 sh3_zsrt139d560_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d560.mem 377 41 1 sh3_zsrt139d560_pal.mem 0x158afe76
61 198092 10240 480 sh3_zsrt139d561_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d561.mem 512 56 1 sh3_zsrt139d561_pal.mem 0x158afe76
62 198092 10240 480 sh3_zsrt139d562_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d562.mem 539 59 1 sh3_zsrt139d562_pal.mem 0x158afe76
63 198092 10240 480 sh3_zsrt139d563_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d563.mem 53 5 1 sh3_zsrt139d563_pal.mem 0x158afe76
64 198092 10240 480 sh3_zsrt139d564_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d564.mem 53 5 1 sh3_zsrt139d564_pal.mem 0x158afe76
65 198092 10240 480 sh3_zsrt139d565_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d565.mem 71 7 1 sh3_zsrt139d565_pal.mem 0x158afe76
66 198092 10240 480 sh3_zsrt139d566_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d566.mem 161 17 1 sh3_zsrt139d566_pal.mem 0x158afe76
67 198092 10240 480 sh3_zsrt139d567_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d567.mem 206 22 1 sh3_zsrt139d567_pal.mem 0x158afe76
68 198092 10240 480 sh3_zsrt139d568_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d568.mem 89 9 1 sh3_zsrt139d568_pal.mem 0x158afe76
69 198092 10240 480 sh3_zsrt139d569_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d569.mem 89 9 1 sh3_zsrt139d569_pal.mem 0x158afe76
70 198092 10240 480 sh3_zsrt139d570_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d570.mem 143 15 1 sh3_zsrt139d570_pal.mem 0x158afe76
71 198092 10240 480 sh3_zsrt139d571_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d571.mem 368 40 1 sh3_zsrt139d571_pal.mem 0x158afe76
72 198092 10240 480 sh3_zsrt139d572_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d572.mem 80 8 1 sh3_zsrt139d572_pal.mem 0x158afe76
73 198092 10240 480 sh3_zsrt139d573_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d573.mem 152 16 1 sh3_zsrt139d573_pal.mem 0x158afe76
74 198092 10240 480 sh3_zsrt139d574_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d574.mem 314 34 1 sh3_zsrt139d574_pal.mem 0x158afe76
75 198092 10240 480 sh3_zsrt139d575_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d575.mem 116 12 1 sh3_zsrt139d575_pal.mem 0x158afe76
76 198092 10240 480 sh3_zsrt139d576_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d576.mem 197 21 1 sh3_zsrt139d576_pal.mem 0x158afe76
77 198092 10240 480 sh3_zsrt139d577_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d577.mem 143 15 1 sh3_zsrt139d577_pal.mem 0x158afe76
78 198092 10240 480 sh3_zsrt139d578_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d578.mem 503 55 1 sh3_zsrt139d578_pal.mem 0x158afe76
79 198092 10240 480 sh3_zsrt139d579_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d579.mem 449 49 1 sh3_zsrt139d579_pal.mem 0x158afe76
80 198092 10240 480 sh3_zsrt139d580_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d580.mem 395 43 1 sh3_zsrt139d580_pal.mem 0x158afe76
81 198092 10240 480 sh3_zsrt139d581_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d581.mem 413 45 1 sh3_zsrt139d581_pal.mem 0x158afe76
82 198092 10240 480 sh3_zsrt139d582_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d582.mem 449 49 1 sh3_zsrt139d582_pal.mem 0x158afe76
83 198092 10240 480 sh3_zsrt139d583_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d583.mem 584 64 1 sh3_zsrt139d583_pal.mem 0x158afe76
84 198092 10240 480 sh3_zsrt139d584_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d584.mem 125 13 1 sh3_zsrt139d584_pal.mem 0x158afe76
85 198092 10240 480 sh3_zsrt139d585_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d585.mem 80 8 1 sh3_zsrt139d585_pal.mem 0x158afe76
86 198092 10240 480 sh3_zsrt139d586_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d586.mem 152 16 1 sh3_zsrt139d586_pal.mem 0x158afe76
87 198092 10240 480 sh3_zsrt139d587_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d587.mem 107 11 1 sh3_zsrt139d587_pal.mem 0x158afe76
88 198092 10240 480 sh3_zsrt139d588_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d588.mem 98 10 1 sh3_zsrt139d588_pal.mem 0x158afe76
89 198092 10240 480 sh3_zsrt139d589_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d589.mem 152 16 1 sh3_zsrt139d589_pal.mem 0x158afe76
90 198092 10240 480 sh3_zsrt139d590_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d590.mem 314 34 1 sh3_zsrt139d590_pal.mem 0x158afe76
91 198092 10240 480 sh3_zsrt139d591_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d591.mem 53 5 1 sh3_zsrt139d591_pal.mem 0x158afe76
92 198092 10240 480 sh3_zsrt139d592_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d592.mem 62 6 1 sh3_zsrt139d592_pal.mem 0x158afe76
93 198092 10240 480 sh3_zsrt139d593_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d593.mem 152 16 1 sh3_zsrt139d593_pal.mem 0x158afe76
94 198092 10240 480 sh3_zsrt139d594_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d594.mem 197 21 1 sh3_zsrt139d594_pal.mem 0x158afe76
95 198092 10240 480 sh3_zsrt139d595_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d595.mem 287 31 1 sh3_zsrt139d595_pal.mem 0x158afe76
96 198092 10240 480 sh3_zsrt139d596_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d596.mem 566 62 1 sh3_zsrt139d596_pal.mem 0x158afe76
97 198092 10240 480 sh3_zsrt139d597_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d597.mem 980 108 1 sh3_zsrt139d597_pal.mem 0x158afe76
98 198092 10240 480 sh3_zsrt139d598_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d598.mem 107 11 1 sh3_zsrt139d598_pal.mem 0x158afe76
99 198092 10240 480 sh3_zsrt139d599_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d599.mem 602 66 1 sh3_zsrt139d599_pal.mem 0x158afe76
100 198092 10240 480 sh3_zsrt139d5100_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5100.mem 377 41 1 sh3_zsrt139d5100_pal.mem 0x158afe76
101 198092 10240 480 sh3_zsrt139d5101_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5101.mem 89 9 1 sh3_zsrt139d5101_pal.mem 0x158afe76
102 198092 10240 480 sh3_zsrt139d5102_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5102.mem 152 16 1 sh3_zsrt139d5102_pal.mem 0x158afe76
103 198092 10240 480 sh3_zsrt139d5103_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5103.mem 305 33 1 sh3_zsrt139d5103_pal.mem 0x158afe76
104 198092 10240 480 sh3_zsrt139d5104_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5104.mem 98 10 1 sh3_zsrt139d5104_pal.mem 0x158afe76
105 198092 10240 480 sh3_zsrt139d5105_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5105.mem 71 7 1 sh3_zsrt139d5105_pal.mem 0x158afe76
106 198092 10240 480 sh3_zsrt139d5106_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5106.mem 71 7 1 sh3_zsrt139d5106_pal.mem 0x158afe76
107 198092 10240 480 sh3_zsrt139d5107_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5107.mem 80 8 1 sh3_zsrt139d5107_pal.mem 0x158afe76
108 198092 10240 480 sh3_zsrt139d5108_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5108.mem 179 19 1 sh3_zsrt139d5108_pal.mem 0x158afe76
109 198092 10240 480 sh3_zsrt139d5109_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5109.mem 251 27 1 sh3_zsrt139d5109_pal.mem 0x158afe76
110 198092 10240 480 sh3_zsrt139d5110_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5110.mem 278 30 1 sh3_zsrt139d5110_pal.mem 0x158afe76
111 198092 10240 480 sh3_zsrt139d5111_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5111.mem 125 13 1 sh3_zsrt139d5111_pal.mem 0x158afe76
112 198092 10240 480 sh3_zsrt139d5112_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5112.mem 251 27 1 sh3_zsrt139d5112_pal.mem 0x158afe76
113 198092 10240 480 sh3_zsrt139d5113_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5113.mem 449 49 1 sh3_zsrt139d5113_pal.mem 0x158afe76
114 198092 10240 480 sh3_zsrt139d5114_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5114.mem 125 13 1 sh3_zsrt139d5114_pal.mem 0x158afe76
115 198092 10240 480 sh3_zsrt139d5115_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5115.mem 71 7 1 sh3_zsrt139d5115_pal.mem 0x158afe76
116 198092 10240 480 sh3_zsrt139d5116_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5116.mem 53 5 1 sh3_zsrt139d5116_pal.mem 0x158afe76
117 198092 10240 480 sh3_zsrt139d5117_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5117.mem 53 5 1 sh3_zsrt139d5117_pal.mem 0x158afe76
118 198092 10240 480 sh3_zsrt139d5118_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5118.mem 44 4 1 sh3_zsrt139d5118_pal.mem 0x158afe76
119 198092 10240 480 sh3_zsrt139d5119_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5119.mem 44 4 1 sh3_zsrt139d5119_pal.mem 0x158afe76
120 198092 10240 480 sh3_zsrt139d5120_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5120.mem 98 10 1 sh3_zsrt139d5120_pal.mem 0x158afe76
121 198092 10240 480 sh3_zsrt139d5121_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5121.mem 80 8 1 sh3_zsrt139d5121_pal.mem 0x158afe76
122 198092 10240 480 sh3_zsrt139d5122_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5122.mem 62 6 1 sh3_zsrt139d5122_pal.mem 0x158afe76
123 198092 10240 480 sh3_zsrt139d5123_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5123.mem 80 8 1 sh3_zsrt139d5123_pal.mem 0x158afe76
124 198092 10240 480 sh3_zsrt139d5124_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5124.mem 107 11 1 sh3_zsrt139d5124_pal.mem 0x158afe76
125 198092 10240 480 sh3_zsrt139d5125_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5125.mem 206 22 1 sh3_zsrt139d5125_pal.mem 0x158afe76
126 198092 10240 480 sh3_zsrt139d5126_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5126.mem 719 79 1 sh3_zsrt139d5126_pal.mem 0x158afe76
127 198092 10240 480 sh3_zsrt139d5127_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5127.mem 494 54 1 sh3_zsrt139d5127_pal.mem 0x158afe76
128 198092 10240 480 sh3_zsrt139d5128_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5128.mem 89 9 1 sh3_zsrt139d5128_pal.mem 0x158afe76
129 198092 10240 480 sh3_zsrt139d5129_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5129.mem 179 19 1 sh3_zsrt139d5129_pal.mem 0x158afe76
130 198092 10240 480 sh3_zsrt139d5130_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5130.mem 242 26 1 sh3_zsrt139d5130_pal.mem 0x158afe76
131 198092 10240 480 sh3_zsrt139d5131_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5131.mem 89 9 1 sh3_zsrt139d5131_pal.mem 0x158afe76
132 198092 10240 480 sh3_zsrt139d5132_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5132.mem 80 8 1 sh3_zsrt139d5132_pal.mem 0x158afe76
133 198092 10240 480 sh3_zsrt139d5133_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5133.mem 170 18 1 sh3_zsrt139d5133_pal.mem 0x158afe76
134 198092 10240 480 sh3_zsrt139d5134_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5134.mem 143 15 1 sh3_zsrt139d5134_pal.mem 0x158afe76
135 198092 10240 480 sh3_zsrt139d5135_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5135.mem 80 8 1 sh3_zsrt139d5135_pal.mem 0x158afe76
136 198092 10240 480 sh3_zsrt139d5136_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5136.mem 62 6 1 sh3_zsrt139d5136_pal.mem 0x158afe76
137 198092 10240 480 sh3_zsrt139d5137_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5137.mem 125 13 1 sh3_zsrt139d5137_pal.mem 0x158afe76
138 198092 10240 480 sh3_zsrt139d5138_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5138.mem 197 21 1 sh3_zsrt139d5138_pal.mem 0x158afe76
139 198092 10240 480 sh3_zsrt139d5139_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5139.mem 188 20 1 sh3_zsrt139d5139_pal.mem 0x158afe76
140 198092 10240 480 sh3_zsrt139d5140_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5140.mem 62 6 1 sh3_zsrt139d5140_pal.mem 0x158afe76
141 198092 10240 480 sh3_zsrt139d5141_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5141.mem 44 4 1 sh3_zsrt139d5141_pal.mem 0x158afe76
142 198092 10240 480 sh3_zsrt139d5142_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5142.mem 44 4 1 sh3_zsrt139d5142_pal.mem 0x158afe76
143 198092 10240 480 sh3_zsrt139d5143_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5143.mem 35 3 1 sh3_zsrt139d5143_pal.mem 0x158afe76
144 198092 10240 480 sh3_zsrt139d5144_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5144.mem 44 4 1 sh3_zsrt139d5144_pal.mem 0x158afe76
145 198092 10240 480 sh3_zsrt139d5145_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5145.mem 62 6 1 sh3_zsrt139d5145_pal.mem 0x158afe76
146 198092 10240 480 sh3_zsrt139d5146_tex_lpddr.mem 0x200000 262144 0x13cfe390 feeder_sh3_zsrt139d5146.mem 98 10 1 sh3_zsrt139d5146_pal.mem 0x158afe76
