# Ch399 epoch descriptor table (16 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 16 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 5328 11264 480 sh3_zsrt139a50_tex_lpddr.mem 0x200000 262144 0x55070afa feeder_sh3_zsrt139a50.mem 493 54 0 sh3_zsrt139a50_pal.mem 0x32ed74c4
1 11671 10240 480 sh3_zsrt139a51_tex_lpddr.mem 0x200000 262144 0x26a88b77 feeder_sh3_zsrt139a51.mem 619 68 0 sh3_zsrt139a51_pal.mem 0x3cd88c98
2 31075 13824 480 sh3_zsrt139a52_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a52.mem 1474 163 0 sh3_zsrt139a52_pal.mem 0x566e7c38
3 32131 13824 480 sh3_zsrt139a53_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a53.mem 1321 146 1 sh3_zsrt139a53_pal.mem 0x566e7c38
4 33085 13824 480 sh3_zsrt139a54_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a54.mem 1843 204 1 sh3_zsrt139a54_pal.mem 0x566e7c38
5 34387 13824 480 sh3_zsrt139a55_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a55.mem 1843 204 1 sh3_zsrt139a55_pal.mem 0x566e7c38
6 35689 13824 480 sh3_zsrt139a56_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a56.mem 1843 204 1 sh3_zsrt139a56_pal.mem 0x566e7c38
7 36991 13824 480 sh3_zsrt139a57_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a57.mem 1843 204 1 sh3_zsrt139a57_pal.mem 0x566e7c38
8 38293 13824 480 sh3_zsrt139a58_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a58.mem 1843 204 1 sh3_zsrt139a58_pal.mem 0x566e7c38
9 39520 13824 480 sh3_zsrt139a59_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a59.mem 1618 179 1 sh3_zsrt139a59_pal.mem 0x566e7c38
10 40747 13824 480 sh3_zsrt139a510_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a510.mem 1843 204 1 sh3_zsrt139a510_pal.mem 0x566e7c38
11 42049 13824 480 sh3_zsrt139a511_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a511.mem 1843 204 1 sh3_zsrt139a511_pal.mem 0x566e7c38
12 43351 13824 480 sh3_zsrt139a512_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a512.mem 1843 204 1 sh3_zsrt139a512_pal.mem 0x566e7c38
13 44653 13824 480 sh3_zsrt139a513_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a513.mem 1843 204 1 sh3_zsrt139a513_pal.mem 0x566e7c38
14 45955 13824 480 sh3_zsrt139a514_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a514.mem 1843 204 1 sh3_zsrt139a514_pal.mem 0x566e7c38
15 47089 13824 480 sh3_zsrt139a515_tex_lpddr.mem 0x200000 262144 0x5b7ffb3d feeder_sh3_zsrt139a515.mem 115 12 1 sh3_zsrt139a515_pal.mem 0x566e7c38
