# Ch385 epoch descriptor table (17 epochs, dump order). CLUT=runtime HPS staging;
# per epoch: upload tex -> LPDDR 0x200000, fill+verify CRC, stream list, GO, fresh drain.
# reuse=1 (Ch359): the texture cache is ALREADY resident from a prior epoch — the host must SKIP the
# upload and fill, and instead VERIFY the resident CRC register still equals crc (fail-closed residency).
META n_epochs 17 fbpxw 640 fbh 480 fbwords 307200 lpddr_tex 0x200000 tex_words 65536 n_beats 8192
# k idx tbp cbp_reloc tex_file lpddr size crc list_file words records reuse pal_file pal_sum32
0 10123 2048 500 sh3_zsrte450_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte450.mem 1843 204 0 sh3_zsrte450_pal.mem 0x3bfe8722
1 10762 2048 500 sh3_zsrte451_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte451.mem 1843 204 1 sh3_zsrte451_pal.mem 0x3bfe8722
2 11401 2048 500 sh3_zsrte452_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte452.mem 817 90 1 sh3_zsrte452_pal.mem 0x3bfe8722
3 11698 2048 500 sh3_zsrte453_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte453.mem 1285 142 0 sh3_zsrte453_pal.mem 0x2c5b7e28
4 12646 2048 500 sh3_zsrte454_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte454.mem 1591 176 1 sh3_zsrte454_pal.mem 0x2c5b7e28
5 13201 2048 500 sh3_zsrte455_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte455.mem 1069 118 1 sh3_zsrte455_pal.mem 0x2c5b7e28
6 13582 2048 500 sh3_zsrte456_tex_lpddr.mem 0x200000 262144 0x2d9a2fda feeder_sh3_zsrte456.mem 205 22 1 sh3_zsrte456_pal.mem 0x2c5b7e28
7 93634 3072 500 sh3_zsrte457_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte457.mem 619 68 0 sh3_zsrte457_pal.mem 0x47097d4c
8 93847 3072 500 sh3_zsrte458_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte458.mem 1591 176 1 sh3_zsrte458_pal.mem 0x47097d4c
9 94402 3072 500 sh3_zsrte459_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte459.mem 1843 204 1 sh3_zsrte459_pal.mem 0x47097d4c
10 95254 3072 500 sh3_zsrte4510_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte4510.mem 1240 137 1 sh3_zsrte4510_pal.mem 0x47097d4c
11 97432 3072 500 sh3_zsrte4511_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte4511.mem 1465 162 1 sh3_zsrte4511_pal.mem 0x47097d4c
12 97945 3072 500 sh3_zsrte4512_tex_lpddr.mem 0x200000 262144 0xcf4cae27 feeder_sh3_zsrte4512.mem 1519 168 1 sh3_zsrte4512_pal.mem 0x47097d4c
13 121898 2048 500 sh3_zsrte4513_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrte4513.mem 1357 150 0 sh3_zsrte4513_pal.mem 0x20ffffff
14 123287 2048 500 sh3_zsrte4514_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrte4514.mem 1825 202 1 sh3_zsrte4514_pal.mem 0x20ffffff
15 123920 2048 500 sh3_zsrte4515_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrte4515.mem 1789 198 1 sh3_zsrte4515_pal.mem 0x20ffffff
16 124541 2048 500 sh3_zsrte4516_tex_lpddr.mem 0x200000 262144 0x87415c50 feeder_sh3_zsrte4516.mem 664 73 1 sh3_zsrte4516_pal.mem 0x20ffffff
