EMIF_Qsys |

2026.03.02.19:16:03 | Datasheet

Overview

Memory Map

emif_lpddr4b
s0_axi4
s0_axi4lite

## clock_310m

altera_clock_bridge v19.2.0

iopll | outclk0 | clock_310m
in_clk

## Parameters
generateLegacySim | false

## Software Assignments (none)

## emif_lpddr4b

emif_io96b_lpddr4 v4.0.0

iopll | outclk0 | emif_lpddr4b
s0_axi4_clock_in
reset_in | out_reset
core_init_n

## Parameters
generateLegacySim | false

## Software Assignments (none)

## iopll

altera_iopll v20.0.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## reset_in

altera_reset_bridge v19.2.0

iopll | outclk0 | reset_in
clk
|  | out_reset | emif_lpddr4b
|  | core_init_n

## Parameters
generateLegacySim | false

## Software Assignments (none)

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