# Ch423 — control-free data stages (prefit)

## Trigger

Ch422 eliminated the design-clock bilinear critical path and left only six
310 MHz EMIF setup endpoints: WNS `-0.012 ns`, TNS `-0.047 ns`.  The actual
post-fit netlist showed that all six ended at data-register clock enables, not
at the RAMs or payload datapaths themselves:

- five `ca_wdata_q[*]|ena` endpoints were driven by the
  `ca_tail -> ca_full -> feed_ok` control cone;
- `req_stage_packet[79]|ena` was driven through the async-reset request-stage
  process, pulling the high-fanout synchronized EMIF calibration reset into
  the payload register's enable implementation.

This chapter handles both members of that same root class in one fit cycle.

## Structural cuts

### Request packet stage

`req_stage_packet` now has its own non-reset `always_ff` block and captures
only when the local registered `req_read_pending` pulse is high.  Occupancy
and observability remain controlled by the separately reset
`req_stage_valid`.  This preserves the request FIFO protocol while preventing
the asynchronous reset cone from being folded into the wide payload register
enable.

### Color-align RAM write tuple

`ca_waddr_q` and `ca_wdata_q` now capture the prospective write tuple every
cycle without reset or `feed_ok` enables.  The separately reset `ca_wr_q`
continues to be asserted only for an accepted fragment.  On the next edge the
RAM consumes the prior captured tuple exactly when the prior `feed_ok` raised
`ca_wr_q`, preserving address, payload, and commit ordering while removing the
FIFO-full comparison from 82 data-register enables.

No clock constraint, multicycle exception, frequency reduction, or functional
pixel change was introduced.

## Prefit verification

- asynchronous request FIFO regression: 3,284 exact transfers, PASS;
- Z/color emitter regression: 1,500 fragments, zero errors, PASS;
- LPDDR scanout-concurrency regression: 16,384 exact pixels, PASS;
- full 283-marker / 282-epoch production-control replay: PASS;
- 1,177,489 fragments fed, 984,845 passed Z, zero drops/errors;
- final Z mismatch `0 / 307,200`, color mismatch `0 / 235,963`;
- framebuffer SHA-256 remains exactly
  `a88f1f6c926dd0db2b72ae2873c399e7dc5666f8003190184c34d360b13a5f44`.

## Owner fit gate

Ready for one owner-controlled Quartus 26.1 GUI compile.  Inspect the actual
post-fit timing and synthesis reports.  Acceptance requires:

- no `ca_tail -> ca_wdata_q[*]|ena` or
  `ca_tail -> ca_waddr_q[*]|ena` setup family;
- no synchronized EMIF calibration-reset / `lock_sync` path to
  `req_stage_packet[*]|ena`;
- the Ch422 bilinear family remains absent and the design clock stays clean;
- setup, hold, recovery, removal, and minimum pulse are all non-negative;
- color-align RAM inference and overall resource use remain intact.

Do not deploy the Ch422 RBF.  If the complete Ch423 report is clean, its RBF is
the next board-deployment candidate.

## Owner fit result — 2026-07-18 17:24

The owner-controlled Quartus 26.1 GUI fit is signoff-clean:

- EMIF setup WNS `+0.025 ns`, TNS `0.000 ns`;
- 25 MHz design setup WNS `+4.124 ns`, TNS `0.000 ns`;
- reference-clock setup WNS `+8.056 ns`, TNS `0.000 ns`;
- hold has zero violations (reported minima `0.000 ns`);
- recovery minimum `+1.071 ns`, removal minimum `+0.167 ns`;
- minimum-pulse-width minimum `+0.200 ns`;
- Timing Analyzer completed successfully with zero errors.

The retired `ca_tail -> ca_wdata_q[*]|ena`, synchronized calibration-reset to
`req_stage_packet[*]|ena`, and Ch422 bilinear families are absent from the
setup top paths.  The color-align memory remains an inferred simple dual-port
M20K (`8,832` bits).  Final resources are 38,241 / 46,800 ALMs (82%),
5,261,744 block-memory bits (72%), and 336 / 358 RAM blocks (94%).

The accepted deploy artifact is `output_files/retroDE_ps2.core.rbf`, 4,120,576
bytes, SHA-256:

`17d1c1b49aac4d893ed56285cf0703bf375db2ee9f472ea36862cca376ae63fe`

## Board acceptance

The RBF was checksum-verified on the DE25-Nano and loaded successfully through
`core_loader.sh`; `fpga0` reported `operating`.  Live bridge preflight passed:

- `CORE_ID = 0x50533200`, ABI `0x00000100`, status `0x0000001f`;
- frame counter advanced by 145 over two seconds;
- raster-overflow count and delta were both zero.

The exact 283-epoch `sh3_zsrt139f18` production fixture then completed with
all texture CRC, CLUT sum, staged-list, fresh-drain, and record-count gates
passing.  Every epoch reported zero fragment drops and the scheduler ended
with `DONE rc=0`.

The board dumped all 307,200 framebuffer words.  Its SHA-256 is

`a88f1f6c926dd0db2b72ae2873c399e7dc5666f8003190184c34d360b13a5f44`,

identical to the full production simulation.  `cmp` confirms byte-for-byte
equality.  Ch423 is therefore timing-, simulation-, and hardware-accepted and
is the new deployment baseline.
