# Ch359 audit log — zs640c6: shared-texture RESIDENCY, 2x204-tri lists, native 640x480 persistent Z

Codex-locked chapter: six SH3 draws sharing ONE PSMT8 texture (tbp=8192/cbp=13888), grouped into TWO ordered
204-triangle feeder lists (1843 words each), authentic GEQUAL/ZMSK=0/PSMZ16S, native 640x480. NEW capability:
EXPLICIT texture-cache residency — one upload+fill (epoch 0); epoch 1 carries reuse=1 in the descriptor and runs
on the resident cache. 408 tris vs Ch358's 122 (3.3x density).

## Fixture/host/TB stack
- Generator --group-size (per-member strip expansion, no phantom bridging tris); shared-texture fail-closed gates
  (tex idxw + CLUT BYTE-identical across draws; list-local state equality; ZTE=1/ZTST=GEQUAL/ZMSK=0/PSMZ16S decode;
  native bounds; <=2048 words); ONE relocated CLUT; reuse in descs/params/epochs.txt. EMIT: 2x204/1843 EXACT
  (Codex's numbers to the digit), crc 0xcf4cae27, ref 21071 covered / 6129 multi px.
- Census lesson: strip draws' triangles = nprim-2 (my verts//3 probe was wrong; proven vs zsched 46/58/18).
- Host: optional trailing reuse column (back-compat verified); reuse epoch = no tex file, no upload/fill,
  fail-closed resident CRC/beats register verify. Dry-run rc=0 (zs640c6 AND legacy tables).
- TBs zs640c6_cap / zint640c6: 2-epoch arrays + EP_REUSE, reuse-epoch residency assert (fill_crc register),
  fills==1 hard assert. LESSON: per-scene TB wait budgets scale with tris/epoch (204-tri epochs blew the
  zs640-calibrated 800k-cycle budgets -> records=172/204 cut-off, cascading counter errors + phantom 65% fidelity).

## THE FINDING — cold-Z burst vs request FIFO (and the Ch359 RTL change)
- zint640c6 @ REQ_DEPTH=256 (Ch358 silicon config): **424 fragment drops, ALL epoch 0** (empty-Z phase: every
  z_rmw miss = dirty evict = 2x AXI), zero in epoch 1 (Z-reject heavy = clean misses). Scoreboard mismatches
  (Z 320 / COLOR 316) == drop effects. High-water probe (Codex-corrected: write-domain wbin - gray2bin(rgray_s2),
  parameterized modulus) saturated 256/256.
- Codex-authorized sim-only sweep: depth 512 -> zero drops, ep0 peak **478** (34 slots margin), scoreboard EXACT;
  depth 1024 -> identical (bounded deterministic burst, not rate-bound).
- CODEX DECISION: **REQ_DEPTH=1024** (2.1x headroom for the next density rung; no Z-RMW/scene/SDC/clock change).
  Changed: de25 top u_zc_emit + the 3 production-equivalent zint TBs; unit/replay depths (16/32) untouched.

## Verification at depth 1024 (2026-07-10)
- Parse audit (QSF file list, exact macro set): clean (only pll/EMIF_Qsys/qsys_top IP).
- zc_emit unit PASS; zrop PASS (zsched 93.4/93.7); baseline zint PASS (Z 0/53760, drops=0, golden-identical);
  zint640 PASS (Z 0/307200, golden-identical); **zint640c6 PASS (ZERO drops, Z 0/307200 + COLOR 0/21032 exact,
  204/204 records, ONE fill + REUSE verified)**; zs640c6_cap PASS (MULTI=90.2% >= 90 floor, ALL=85.3%
  scene-dependent reciprocal floor, clut_bad=0 — flagged: floor margin is thin for future regenerations).
- Full regression: **282/282 PASS, 0 FAIL** (280 baseline + the two C6 gates now in the run list).

## Board Proof And Provenance Correction
- The first depth-1024 GUI fit met timing, and its board host run passed every transport/runtime gate: 204/204 records
  in both epochs, one fill plus verified reuse, and zero drops. The board framebuffer nevertheless differed from zint
  at all 21032 covered pixels while retaining the exact C6 bounds=(84,101)..(340,301). This isolated the failure to
  color provenance, not geometry, persistent Z, LPDDR transport, or FIFO depth.
- Root cause, verified in that fit's synthesis report: the QSF still selected Ch358 `bios_sh3_zs640.mem` and
  `payload_sh3_zs640.mem`, so the board booted the old CLUT rather than C6's CBP=13888 palette. The C6 fixture and
  host files were correct; the RBF's boot-image inputs were not.
- Corrected fit inputs: `sh3_lpddr_fb_z640c6` now selects `bios_sh3_zs640c6.mem` and
  `payload_sh3_zs640c6.mem` through `scripts/select_de25_profile.sh`. The REQ_DEPTH=1024 top change remains part of
  the same compile. No SDC, clock, or Z-RMW change is needed.

## Handoff
Owner: run one full 26.1 GUI compile with the corrected C6 profile, then check STA before loading the RBF. Only after
timing is clean: run `scp_zs640c6_to_board.sh` (five files including the reuse-modified `ps2_sh3_sched.c`, recompile
on board), then `sudo ./ps2_sh3_sched --zbuf sh3_zs640c6_epochs.txt --dump-fb sh3_zs640c6_board_fb.mem`. Expect
`bounds=(84,101)..(340,301)`, retrieve the dump, and run `make -C sim sh3_zs640c6_board_compare`.

## Closure (2026-07-10)
- Quartus 26.1 GUI RBF `ad4e8c9627520dcaba9babf2019ca5b28892799e0500f8f3300f4f2a29b5218c` compiled the corrected
  `bios_sh3_zs640c6.mem` and `payload_sh3_zs640c6.mem` inputs. STA met: setup +0.095 ns, hold 0.000 ns, recovery
  +1.042 ns, removal +0.185 ns, minimum pulse width +0.200 ns.
- On silicon: both 204-record epochs drained; epoch 0 uploaded/filled the texture and epoch 1 verified resident reuse;
  zero fragment drops; output bounds `(84,101)..(340,301)`; 21032 nonzero pixels.
- `make -C sim sh3_zs640c6_board_compare` passed. The board and zint framebuffers had identical SHA-256
  `948d9c45df84ccf180faebe7b24e3e4445bcce390c8bfab91fb3b50885fcaa4`, and replay-color was exact at
  307200/307200 pixels. Ch359 is closed.
