# Ch400 — chronological base geometry plus bounded alpha tail

## Goal

Move fidelity forward by replaying the missing in-bounds opaque draws before a
small authentic alpha-blended tail, rather than darkening the incomplete Ch399
base with the full alpha family.

## Fixture

- Tag: `sh3_zsrt139a6`
- 35 authentic draws in chronological order
- 20 epochs: 17 base epochs followed by 3 alpha epochs
- Independent reference coverage: 83,596 framebuffer pixels
- Simulation target: `make -C sim tb_top_psmct32_sh3_zint640rt139a6`
- Board loader: `tools/scp_zsrt139a6_to_board.sh`

## Blend ordering correction

The first full replay found two wrong color pixels with exact Z. Repeated ABE
fragments could begin their destination read after the previous blended result
entered the color writer, but before that partial beat received an AXI BRESP.
Waiting on the writer's raw `idle` signal is not sufficient because the elastic
packer may retain a partial beat while its AXI FIFO is empty.

`gs_lpddr_zc_emit` now treats each ABE result as an ordered dependency:

1. accept one ABE input and hold subsequent color inputs;
2. enqueue its blended output and pulse the color writer flush;
3. wait for the ordered drain acknowledgement to transition low then high;
4. admit the next color input only after the preceding write is memory-visible.

Opaque flow remains unrestricted outside an active ABE dependency.

## Simulation acceptance

Final full replay:

- fragments fed: 279,134
- fragments passing Z: 234,373
- scene markers: 20
- request drops: 0
- color FIFO overflows: 0
- AXI BRESP errors: 0
- Z mismatches: 0 / 307,200
- color mismatches: 0 / 83,596
- framebuffer MEM SHA-256:
  `38095a6c9136eb6618876c4cf2bf9a72c494a6f8161c247f2e1a36dcd0474bb8`

## Hardware gate

The RTL correction postdates the 2026-07-16 06:17 Quartus artifact. A fresh
owner-run Quartus 26.1 GUI compile is required before board deployment. After
that compile, accept Ch400 only if timing is clean, the RBF is fresh, the board
run completes all 20 epochs with zero drops/errors, and the board framebuffer is
byte-exact to `sh3_zsrt139a6_sim_fb.mem`.

## Silicon acceptance (2026-07-16)

The owner-run Quartus 26.1 GUI compile completed successfully after the final
RTL correction. The fit used 37,148/46,800 ALMs and 284/358 RAM blocks. Setup
slack was `+0.107 ns`, hold slack was `0.000 ns`, and all reported TNS values
were zero.

The fresh deploy RBF was written at 08:34:52, is 3,919,872 bytes, and has
SHA-256
`4619653217c8946b7ba4cd847a17f5e5b020c449ac4837784f72f9a7abed0b7d`.
The hash matched on the DE25 before loading, and `fpga0` reported `operating`.

The board completed all 20 epochs with every texture CRC, palette checksum,
staged-word count, triangle-record count, preclear, drain, and zero-drop gate
passing. The host returned `rc=0` and dumped all 307,200 framebuffer words.

Board and simulation are byte-exact across the complete framebuffer:

- board MEM SHA-256:
  `38095a6c9136eb6618876c4cf2bf9a72c494a6f8161c247f2e1a36dcd0474bb8`
- simulation MEM SHA-256: same
- board PNG SHA-256:
  `1785875df7c4c17fbf94ce1543fa3777be5601c874f5319ce4e2a20c828cecd0`
- simulation PNG SHA-256: same

Ch400 is accepted on silicon.
