peripheral_subsys |

2026.05.11.21:03:51 | Datasheet

Overview

All Components
button_pio altera_avalon_pio 19.2.3
dipsw_pio altera_avalon_pio 19.2.3
led_pio altera_avalon_pio 19.2.3
pb_cpu_0 altera_avalon_mm_bridge 20.1.0
sysid altera_avalon_sysid_qsys 19.1.7
Memory Map

| pb_cpu_0
m0
button_pio |
s1 | 0x0001_0060 - 0x0001_006f
dipsw_pio |
s1 | 0x0001_0070 - 0x0001_007f
led_pio |
s1 | 0x0001_0080 - 0x0001_008f
pb_cpu_0 |
s0 |
sysid |
control_slave | 0x0001_0000 - 0x0001_0007

## button_pio

altera_avalon_pio v19.2.3

pb_cpu_0 | m0 | button_pio
s1
periph_clk | out_clk
clk
periph_rst_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 1
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | FALLING
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## dipsw_pio

altera_avalon_pio v19.2.3

pb_cpu_0 | m0 | dipsw_pio
s1
periph_clk | out_clk
clk
periph_rst_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 1
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | FALLING
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## led_pio

altera_avalon_pio v19.2.3

pb_cpu_0 | m0 | led_pio
s1
periph_clk | out_clk
clk
periph_rst_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 3
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 7

## pb_cpu_0

altera_avalon_mm_bridge v20.1.0

periph_clk | out_clk | pb_cpu_0
clk
periph_rst_in | out_reset
reset
|  | m0 | sysid
|  | control_slave
|  | m0 | led_pio
|  | s1
|  | m0 | dipsw_pio
|  | s1
|  | m0 | button_pio
|  | s1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## periph_clk

altera_clock_bridge v19.2.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## periph_rst_in

altera_reset_bridge v19.2.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## sysid

altera_avalon_sysid_qsys v19.1.7

pb_cpu_0 | m0 | sysid
control_slave
periph_clk | out_clk
clk
periph_rst_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
ID | -1395275010
TIMESTAMP | 0

generation took 0.01 seconds | rendering took 0.07 seconds