	EMIF_Qsys u0 (
		.clock_310m_out_clk_clk                   (_connected_to_clock_310m_out_clk_clk_),                   //  output,    width = 1,               clock_310m_out_clk.clk
		.emif_lpddr4b_s0_axi4_ctrl_ready_reset_n  (_connected_to_emif_lpddr4b_s0_axi4_ctrl_ready_reset_n_),  //  output,    width = 1,  emif_lpddr4b_s0_axi4_ctrl_ready.reset_n
		.emif_lpddr4b_s0_axi4_awaddr              (_connected_to_emif_lpddr4b_s0_axi4_awaddr_),              //   input,   width = 30,             emif_lpddr4b_s0_axi4.awaddr
		.emif_lpddr4b_s0_axi4_awburst             (_connected_to_emif_lpddr4b_s0_axi4_awburst_),             //   input,    width = 2,                                 .awburst
		.emif_lpddr4b_s0_axi4_awid                (_connected_to_emif_lpddr4b_s0_axi4_awid_),                //   input,    width = 7,                                 .awid
		.emif_lpddr4b_s0_axi4_awlen               (_connected_to_emif_lpddr4b_s0_axi4_awlen_),               //   input,    width = 8,                                 .awlen
		.emif_lpddr4b_s0_axi4_awlock              (_connected_to_emif_lpddr4b_s0_axi4_awlock_),              //   input,    width = 1,                                 .awlock
		.emif_lpddr4b_s0_axi4_awqos               (_connected_to_emif_lpddr4b_s0_axi4_awqos_),               //   input,    width = 4,                                 .awqos
		.emif_lpddr4b_s0_axi4_awsize              (_connected_to_emif_lpddr4b_s0_axi4_awsize_),              //   input,    width = 3,                                 .awsize
		.emif_lpddr4b_s0_axi4_awvalid             (_connected_to_emif_lpddr4b_s0_axi4_awvalid_),             //   input,    width = 1,                                 .awvalid
		.emif_lpddr4b_s0_axi4_awuser              (_connected_to_emif_lpddr4b_s0_axi4_awuser_),              //   input,   width = 14,                                 .awuser
		.emif_lpddr4b_s0_axi4_awprot              (_connected_to_emif_lpddr4b_s0_axi4_awprot_),              //   input,    width = 3,                                 .awprot
		.emif_lpddr4b_s0_axi4_awready             (_connected_to_emif_lpddr4b_s0_axi4_awready_),             //  output,    width = 1,                                 .awready
		.emif_lpddr4b_s0_axi4_araddr              (_connected_to_emif_lpddr4b_s0_axi4_araddr_),              //   input,   width = 30,                                 .araddr
		.emif_lpddr4b_s0_axi4_arburst             (_connected_to_emif_lpddr4b_s0_axi4_arburst_),             //   input,    width = 2,                                 .arburst
		.emif_lpddr4b_s0_axi4_arid                (_connected_to_emif_lpddr4b_s0_axi4_arid_),                //   input,    width = 7,                                 .arid
		.emif_lpddr4b_s0_axi4_arlen               (_connected_to_emif_lpddr4b_s0_axi4_arlen_),               //   input,    width = 8,                                 .arlen
		.emif_lpddr4b_s0_axi4_arlock              (_connected_to_emif_lpddr4b_s0_axi4_arlock_),              //   input,    width = 1,                                 .arlock
		.emif_lpddr4b_s0_axi4_arqos               (_connected_to_emif_lpddr4b_s0_axi4_arqos_),               //   input,    width = 4,                                 .arqos
		.emif_lpddr4b_s0_axi4_arsize              (_connected_to_emif_lpddr4b_s0_axi4_arsize_),              //   input,    width = 3,                                 .arsize
		.emif_lpddr4b_s0_axi4_arvalid             (_connected_to_emif_lpddr4b_s0_axi4_arvalid_),             //   input,    width = 1,                                 .arvalid
		.emif_lpddr4b_s0_axi4_aruser              (_connected_to_emif_lpddr4b_s0_axi4_aruser_),              //   input,   width = 14,                                 .aruser
		.emif_lpddr4b_s0_axi4_arprot              (_connected_to_emif_lpddr4b_s0_axi4_arprot_),              //   input,    width = 3,                                 .arprot
		.emif_lpddr4b_s0_axi4_arready             (_connected_to_emif_lpddr4b_s0_axi4_arready_),             //  output,    width = 1,                                 .arready
		.emif_lpddr4b_s0_axi4_wdata               (_connected_to_emif_lpddr4b_s0_axi4_wdata_),               //   input,  width = 256,                                 .wdata
		.emif_lpddr4b_s0_axi4_wstrb               (_connected_to_emif_lpddr4b_s0_axi4_wstrb_),               //   input,   width = 32,                                 .wstrb
		.emif_lpddr4b_s0_axi4_wlast               (_connected_to_emif_lpddr4b_s0_axi4_wlast_),               //   input,    width = 1,                                 .wlast
		.emif_lpddr4b_s0_axi4_wvalid              (_connected_to_emif_lpddr4b_s0_axi4_wvalid_),              //   input,    width = 1,                                 .wvalid
		.emif_lpddr4b_s0_axi4_wready              (_connected_to_emif_lpddr4b_s0_axi4_wready_),              //  output,    width = 1,                                 .wready
		.emif_lpddr4b_s0_axi4_bready              (_connected_to_emif_lpddr4b_s0_axi4_bready_),              //   input,    width = 1,                                 .bready
		.emif_lpddr4b_s0_axi4_bid                 (_connected_to_emif_lpddr4b_s0_axi4_bid_),                 //  output,    width = 7,                                 .bid
		.emif_lpddr4b_s0_axi4_bresp               (_connected_to_emif_lpddr4b_s0_axi4_bresp_),               //  output,    width = 2,                                 .bresp
		.emif_lpddr4b_s0_axi4_bvalid              (_connected_to_emif_lpddr4b_s0_axi4_bvalid_),              //  output,    width = 1,                                 .bvalid
		.emif_lpddr4b_s0_axi4_rready              (_connected_to_emif_lpddr4b_s0_axi4_rready_),              //   input,    width = 1,                                 .rready
		.emif_lpddr4b_s0_axi4_rdata               (_connected_to_emif_lpddr4b_s0_axi4_rdata_),               //  output,  width = 256,                                 .rdata
		.emif_lpddr4b_s0_axi4_rid                 (_connected_to_emif_lpddr4b_s0_axi4_rid_),                 //  output,    width = 7,                                 .rid
		.emif_lpddr4b_s0_axi4_rlast               (_connected_to_emif_lpddr4b_s0_axi4_rlast_),               //  output,    width = 1,                                 .rlast
		.emif_lpddr4b_s0_axi4_rresp               (_connected_to_emif_lpddr4b_s0_axi4_rresp_),               //  output,    width = 2,                                 .rresp
		.emif_lpddr4b_s0_axi4_rvalid              (_connected_to_emif_lpddr4b_s0_axi4_rvalid_),              //  output,    width = 1,                                 .rvalid
		.emif_lpddr4b_s0_axi4lite_clock_clk       (_connected_to_emif_lpddr4b_s0_axi4lite_clock_clk_),       //   input,    width = 1,   emif_lpddr4b_s0_axi4lite_clock.clk
		.emif_lpddr4b_s0_axi4lite_reset_n_reset_n (_connected_to_emif_lpddr4b_s0_axi4lite_reset_n_reset_n_), //   input,    width = 1, emif_lpddr4b_s0_axi4lite_reset_n.reset_n
		.emif_lpddr4b_s0_axi4lite_awaddr          (_connected_to_emif_lpddr4b_s0_axi4lite_awaddr_),          //   input,   width = 27,         emif_lpddr4b_s0_axi4lite.awaddr
		.emif_lpddr4b_s0_axi4lite_awprot          (_connected_to_emif_lpddr4b_s0_axi4lite_awprot_),          //   input,    width = 3,                                 .awprot
		.emif_lpddr4b_s0_axi4lite_awvalid         (_connected_to_emif_lpddr4b_s0_axi4lite_awvalid_),         //   input,    width = 1,                                 .awvalid
		.emif_lpddr4b_s0_axi4lite_awready         (_connected_to_emif_lpddr4b_s0_axi4lite_awready_),         //  output,    width = 1,                                 .awready
		.emif_lpddr4b_s0_axi4lite_araddr          (_connected_to_emif_lpddr4b_s0_axi4lite_araddr_),          //   input,   width = 27,                                 .araddr
		.emif_lpddr4b_s0_axi4lite_arprot          (_connected_to_emif_lpddr4b_s0_axi4lite_arprot_),          //   input,    width = 3,                                 .arprot
		.emif_lpddr4b_s0_axi4lite_arvalid         (_connected_to_emif_lpddr4b_s0_axi4lite_arvalid_),         //   input,    width = 1,                                 .arvalid
		.emif_lpddr4b_s0_axi4lite_arready         (_connected_to_emif_lpddr4b_s0_axi4lite_arready_),         //  output,    width = 1,                                 .arready
		.emif_lpddr4b_s0_axi4lite_wdata           (_connected_to_emif_lpddr4b_s0_axi4lite_wdata_),           //   input,   width = 32,                                 .wdata
		.emif_lpddr4b_s0_axi4lite_wstrb           (_connected_to_emif_lpddr4b_s0_axi4lite_wstrb_),           //   input,    width = 4,                                 .wstrb
		.emif_lpddr4b_s0_axi4lite_wvalid          (_connected_to_emif_lpddr4b_s0_axi4lite_wvalid_),          //   input,    width = 1,                                 .wvalid
		.emif_lpddr4b_s0_axi4lite_wready          (_connected_to_emif_lpddr4b_s0_axi4lite_wready_),          //  output,    width = 1,                                 .wready
		.emif_lpddr4b_s0_axi4lite_bready          (_connected_to_emif_lpddr4b_s0_axi4lite_bready_),          //   input,    width = 1,                                 .bready
		.emif_lpddr4b_s0_axi4lite_bresp           (_connected_to_emif_lpddr4b_s0_axi4lite_bresp_),           //  output,    width = 2,                                 .bresp
		.emif_lpddr4b_s0_axi4lite_bvalid          (_connected_to_emif_lpddr4b_s0_axi4lite_bvalid_),          //  output,    width = 1,                                 .bvalid
		.emif_lpddr4b_s0_axi4lite_rready          (_connected_to_emif_lpddr4b_s0_axi4lite_rready_),          //   input,    width = 1,                                 .rready
		.emif_lpddr4b_s0_axi4lite_rdata           (_connected_to_emif_lpddr4b_s0_axi4lite_rdata_),           //  output,   width = 32,                                 .rdata
		.emif_lpddr4b_s0_axi4lite_rresp           (_connected_to_emif_lpddr4b_s0_axi4lite_rresp_),           //  output,    width = 2,                                 .rresp
		.emif_lpddr4b_s0_axi4lite_rvalid          (_connected_to_emif_lpddr4b_s0_axi4lite_rvalid_),          //  output,    width = 1,                                 .rvalid
		.emif_lpddr4b_mem_mem_cs                  (_connected_to_emif_lpddr4b_mem_mem_cs_),                  //  output,    width = 1,                 emif_lpddr4b_mem.mem_cs
		.emif_lpddr4b_mem_mem_ca                  (_connected_to_emif_lpddr4b_mem_mem_ca_),                  //  output,    width = 6,                                 .mem_ca
		.emif_lpddr4b_mem_mem_cke                 (_connected_to_emif_lpddr4b_mem_mem_cke_),                 //  output,    width = 1,                                 .mem_cke
		.emif_lpddr4b_mem_mem_dq                  (_connected_to_emif_lpddr4b_mem_mem_dq_),                  //   inout,   width = 32,                                 .mem_dq
		.emif_lpddr4b_mem_mem_dqs_t               (_connected_to_emif_lpddr4b_mem_mem_dqs_t_),               //   inout,    width = 4,                                 .mem_dqs_t
		.emif_lpddr4b_mem_mem_dqs_c               (_connected_to_emif_lpddr4b_mem_mem_dqs_c_),               //   inout,    width = 4,                                 .mem_dqs_c
		.emif_lpddr4b_mem_mem_dmi                 (_connected_to_emif_lpddr4b_mem_mem_dmi_),                 //   inout,    width = 4,                                 .mem_dmi
		.emif_lpddr4b_mem_ck_mem_ck_t             (_connected_to_emif_lpddr4b_mem_ck_mem_ck_t_),             //  output,    width = 1,              emif_lpddr4b_mem_ck.mem_ck_t
		.emif_lpddr4b_mem_ck_mem_ck_c             (_connected_to_emif_lpddr4b_mem_ck_mem_ck_c_),             //  output,    width = 1,                                 .mem_ck_c
		.emif_lpddr4b_mem_reset_n_mem_reset_n     (_connected_to_emif_lpddr4b_mem_reset_n_mem_reset_n_),     //  output,    width = 1,         emif_lpddr4b_mem_reset_n.mem_reset_n
		.emif_lpddr4b_oct_oct_rzqin               (_connected_to_emif_lpddr4b_oct_oct_rzqin_),               //   input,    width = 1,                 emif_lpddr4b_oct.oct_rzqin
		.emif_lpddr4b_ref_clk_clk                 (_connected_to_emif_lpddr4b_ref_clk_clk_),                 //   input,    width = 1,             emif_lpddr4b_ref_clk.clk
		.iopll_refclk_clk                         (_connected_to_iopll_refclk_clk_),                         //   input,    width = 1,                     iopll_refclk.clk
		.iopll_locked_export                      (_connected_to_iopll_locked_export_),                      //  output,    width = 1,                     iopll_locked.export
		.iopll_reset_reset                        (_connected_to_iopll_reset_reset_),                        //   input,    width = 1,                      iopll_reset.reset
		.iopll_outclk_axi4_lite_clk               (_connected_to_iopll_outclk_axi4_lite_clk_),               //  output,    width = 1,           iopll_outclk_axi4_lite.clk
		.reset_reset_n                            (_connected_to_reset_reset_n_)                             //   input,    width = 1,                            reset.reset_n
	);

