// hps_subsys.v

// Generated using ACDS version 26.1 110

`timescale 1 ps / 1 ps
module hps_subsys (
		output wire         h2f_reset_reset,                       //                 h2f_reset.reset
		input  wire         hps2fpga_clk_clk,                      //              hps2fpga_clk.clk
		input  wire         hps2fpga_rst_reset,                    //              hps2fpga_rst.reset
		output wire [3:0]   hps2fpga_awid,                         //                  hps2fpga.awid
		output wire [37:0]  hps2fpga_awaddr,                       //                          .awaddr
		output wire [7:0]   hps2fpga_awlen,                        //                          .awlen
		output wire [2:0]   hps2fpga_awsize,                       //                          .awsize
		output wire [1:0]   hps2fpga_awburst,                      //                          .awburst
		output wire         hps2fpga_awlock,                       //                          .awlock
		output wire [3:0]   hps2fpga_awcache,                      //                          .awcache
		output wire [2:0]   hps2fpga_awprot,                       //                          .awprot
		output wire         hps2fpga_awvalid,                      //                          .awvalid
		input  wire         hps2fpga_awready,                      //                          .awready
		output wire [127:0] hps2fpga_wdata,                        //                          .wdata
		output wire [15:0]  hps2fpga_wstrb,                        //                          .wstrb
		output wire         hps2fpga_wlast,                        //                          .wlast
		output wire         hps2fpga_wvalid,                       //                          .wvalid
		input  wire         hps2fpga_wready,                       //                          .wready
		input  wire [3:0]   hps2fpga_bid,                          //                          .bid
		input  wire [1:0]   hps2fpga_bresp,                        //                          .bresp
		input  wire         hps2fpga_bvalid,                       //                          .bvalid
		output wire         hps2fpga_bready,                       //                          .bready
		output wire [3:0]   hps2fpga_arid,                         //                          .arid
		output wire [37:0]  hps2fpga_araddr,                       //                          .araddr
		output wire [7:0]   hps2fpga_arlen,                        //                          .arlen
		output wire [2:0]   hps2fpga_arsize,                       //                          .arsize
		output wire [1:0]   hps2fpga_arburst,                      //                          .arburst
		output wire         hps2fpga_arlock,                       //                          .arlock
		output wire [3:0]   hps2fpga_arcache,                      //                          .arcache
		output wire [2:0]   hps2fpga_arprot,                       //                          .arprot
		output wire         hps2fpga_arvalid,                      //                          .arvalid
		input  wire         hps2fpga_arready,                      //                          .arready
		input  wire [3:0]   hps2fpga_rid,                          //                          .rid
		input  wire [127:0] hps2fpga_rdata,                        //                          .rdata
		input  wire [1:0]   hps2fpga_rresp,                        //                          .rresp
		input  wire         hps2fpga_rlast,                        //                          .rlast
		input  wire         hps2fpga_rvalid,                       //                          .rvalid
		output wire         hps2fpga_rready,                       //                          .rready
		input  wire         lwhps2fpga_clk_clk,                    //            lwhps2fpga_clk.clk
		input  wire         lwhps2fpga_rst_reset,                  //            lwhps2fpga_rst.reset
		output wire [3:0]   lwhps2fpga_awid,                       //                lwhps2fpga.awid
		output wire [28:0]  lwhps2fpga_awaddr,                     //                          .awaddr
		output wire [7:0]   lwhps2fpga_awlen,                      //                          .awlen
		output wire [2:0]   lwhps2fpga_awsize,                     //                          .awsize
		output wire [1:0]   lwhps2fpga_awburst,                    //                          .awburst
		output wire         lwhps2fpga_awlock,                     //                          .awlock
		output wire [3:0]   lwhps2fpga_awcache,                    //                          .awcache
		output wire [2:0]   lwhps2fpga_awprot,                     //                          .awprot
		output wire         lwhps2fpga_awvalid,                    //                          .awvalid
		input  wire         lwhps2fpga_awready,                    //                          .awready
		output wire [31:0]  lwhps2fpga_wdata,                      //                          .wdata
		output wire [3:0]   lwhps2fpga_wstrb,                      //                          .wstrb
		output wire         lwhps2fpga_wlast,                      //                          .wlast
		output wire         lwhps2fpga_wvalid,                     //                          .wvalid
		input  wire         lwhps2fpga_wready,                     //                          .wready
		input  wire [3:0]   lwhps2fpga_bid,                        //                          .bid
		input  wire [1:0]   lwhps2fpga_bresp,                      //                          .bresp
		input  wire         lwhps2fpga_bvalid,                     //                          .bvalid
		output wire         lwhps2fpga_bready,                     //                          .bready
		output wire [3:0]   lwhps2fpga_arid,                       //                          .arid
		output wire [28:0]  lwhps2fpga_araddr,                     //                          .araddr
		output wire [7:0]   lwhps2fpga_arlen,                      //                          .arlen
		output wire [2:0]   lwhps2fpga_arsize,                     //                          .arsize
		output wire [1:0]   lwhps2fpga_arburst,                    //                          .arburst
		output wire         lwhps2fpga_arlock,                     //                          .arlock
		output wire [3:0]   lwhps2fpga_arcache,                    //                          .arcache
		output wire [2:0]   lwhps2fpga_arprot,                     //                          .arprot
		output wire         lwhps2fpga_arvalid,                    //                          .arvalid
		input  wire         lwhps2fpga_arready,                    //                          .arready
		input  wire [3:0]   lwhps2fpga_rid,                        //                          .rid
		input  wire [31:0]  lwhps2fpga_rdata,                      //                          .rdata
		input  wire [1:0]   lwhps2fpga_rresp,                      //                          .rresp
		input  wire         lwhps2fpga_rlast,                      //                          .rlast
		input  wire         lwhps2fpga_rvalid,                     //                          .rvalid
		output wire         lwhps2fpga_rready,                     //                          .rready
		output wire         h2f_warm_reset_handshake_reset_req,    //  h2f_warm_reset_handshake.reset_req
		input  wire         h2f_warm_reset_handshake_reset_ack,    //                          .reset_ack
		input  wire         hps_io_hps_osc_clk,                    //                    hps_io.hps_osc_clk
		inout  wire         hps_io_sdmmc_data0,                    //                          .sdmmc_data0
		inout  wire         hps_io_sdmmc_data1,                    //                          .sdmmc_data1
		output wire         hps_io_sdmmc_cclk,                     //                          .sdmmc_cclk
		inout  wire         hps_io_sdmmc_data2,                    //                          .sdmmc_data2
		inout  wire         hps_io_sdmmc_data3,                    //                          .sdmmc_data3
		inout  wire         hps_io_sdmmc_cmd,                      //                          .sdmmc_cmd
		input  wire         hps_io_usb0_clk,                       //                          .usb0_clk
		output wire         hps_io_usb0_stp,                       //                          .usb0_stp
		input  wire         hps_io_usb0_dir,                       //                          .usb0_dir
		inout  wire         hps_io_usb0_data0,                     //                          .usb0_data0
		inout  wire         hps_io_usb0_data1,                     //                          .usb0_data1
		input  wire         hps_io_usb0_nxt,                       //                          .usb0_nxt
		inout  wire         hps_io_usb0_data2,                     //                          .usb0_data2
		inout  wire         hps_io_usb0_data3,                     //                          .usb0_data3
		inout  wire         hps_io_usb0_data4,                     //                          .usb0_data4
		inout  wire         hps_io_usb0_data5,                     //                          .usb0_data5
		inout  wire         hps_io_usb0_data6,                     //                          .usb0_data6
		inout  wire         hps_io_usb0_data7,                     //                          .usb0_data7
		output wire         hps_io_emac0_tx_clk,                   //                          .emac0_tx_clk
		output wire         hps_io_emac0_tx_ctl,                   //                          .emac0_tx_ctl
		input  wire         hps_io_emac0_rx_clk,                   //                          .emac0_rx_clk
		input  wire         hps_io_emac0_rx_ctl,                   //                          .emac0_rx_ctl
		output wire         hps_io_emac0_txd0,                     //                          .emac0_txd0
		output wire         hps_io_emac0_txd1,                     //                          .emac0_txd1
		input  wire         hps_io_emac0_rxd0,                     //                          .emac0_rxd0
		input  wire         hps_io_emac0_rxd1,                     //                          .emac0_rxd1
		output wire         hps_io_emac0_txd2,                     //                          .emac0_txd2
		output wire         hps_io_emac0_txd3,                     //                          .emac0_txd3
		input  wire         hps_io_emac0_rxd2,                     //                          .emac0_rxd2
		input  wire         hps_io_emac0_rxd3,                     //                          .emac0_rxd3
		inout  wire         hps_io_mdio0_mdio,                     //                          .mdio0_mdio
		output wire         hps_io_mdio0_mdc,                      //                          .mdio0_mdc
		output wire         hps_io_uart1_tx,                       //                          .uart1_tx
		input  wire         hps_io_uart1_rx,                       //                          .uart1_rx
		inout  wire         hps_io_i2c1_sda,                       //                          .i2c1_sda
		inout  wire         hps_io_i2c1_scl,                       //                          .i2c1_scl
		inout  wire         hps_io_gpio28,                         //                          .gpio28
		inout  wire         hps_io_gpio34,                         //                          .gpio34
		inout  wire         hps_io_gpio40,                         //                          .gpio40
		inout  wire         hps_io_gpio41,                         //                          .gpio41
		input  wire [31:0]  f2h_irq1_in_irq,                       //               f2h_irq1_in.irq
		input  wire [31:0]  f2h_irq0_in_irq,                       //               f2h_irq0_in.irq
		input  wire         f2sdram_clk_clk,                       //               f2sdram_clk.clk
		input  wire         f2sdram_rst_reset,                     //               f2sdram_rst.reset
		input  wire [31:0]  f2sdram_araddr,                        //                   f2sdram.araddr
		input  wire [1:0]   f2sdram_arburst,                       //                          .arburst
		input  wire [3:0]   f2sdram_arcache,                       //                          .arcache
		input  wire [4:0]   f2sdram_arid,                          //                          .arid
		input  wire [7:0]   f2sdram_arlen,                         //                          .arlen
		input  wire         f2sdram_arlock,                        //                          .arlock
		input  wire [2:0]   f2sdram_arprot,                        //                          .arprot
		input  wire [3:0]   f2sdram_arqos,                         //                          .arqos
		output wire         f2sdram_arready,                       //                          .arready
		input  wire [2:0]   f2sdram_arsize,                        //                          .arsize
		input  wire         f2sdram_arvalid,                       //                          .arvalid
		input  wire [31:0]  f2sdram_awaddr,                        //                          .awaddr
		input  wire [1:0]   f2sdram_awburst,                       //                          .awburst
		input  wire [3:0]   f2sdram_awcache,                       //                          .awcache
		input  wire [4:0]   f2sdram_awid,                          //                          .awid
		input  wire [7:0]   f2sdram_awlen,                         //                          .awlen
		input  wire         f2sdram_awlock,                        //                          .awlock
		input  wire [2:0]   f2sdram_awprot,                        //                          .awprot
		input  wire [3:0]   f2sdram_awqos,                         //                          .awqos
		output wire         f2sdram_awready,                       //                          .awready
		input  wire [2:0]   f2sdram_awsize,                        //                          .awsize
		input  wire         f2sdram_awvalid,                       //                          .awvalid
		output wire [4:0]   f2sdram_bid,                           //                          .bid
		input  wire         f2sdram_bready,                        //                          .bready
		output wire [1:0]   f2sdram_bresp,                         //                          .bresp
		output wire         f2sdram_bvalid,                        //                          .bvalid
		output wire [255:0] f2sdram_rdata,                         //                          .rdata
		output wire [4:0]   f2sdram_rid,                           //                          .rid
		output wire         f2sdram_rlast,                         //                          .rlast
		input  wire         f2sdram_rready,                        //                          .rready
		output wire [1:0]   f2sdram_rresp,                         //                          .rresp
		output wire         f2sdram_rvalid,                        //                          .rvalid
		input  wire [255:0] f2sdram_wdata,                         //                          .wdata
		input  wire         f2sdram_wlast,                         //                          .wlast
		output wire         f2sdram_wready,                        //                          .wready
		input  wire [31:0]  f2sdram_wstrb,                         //                          .wstrb
		input  wire         f2sdram_wvalid,                        //                          .wvalid
		input  wire [7:0]   f2sdram_aruser,                        //                          .aruser
		input  wire [7:0]   f2sdram_awuser,                        //                          .awuser
		input  wire [7:0]   f2sdram_wuser,                         //                          .wuser
		output wire [7:0]   f2sdram_buser,                         //                          .buser
		input  wire [3:0]   f2sdram_arregion,                      //                          .arregion
		output wire [7:0]   f2sdram_ruser,                         //                          .ruser
		input  wire [3:0]   f2sdram_awregion,                      //                          .awregion
		output wire [0:0]   emif_hps_emif_mem_0_mem_cs,            //       emif_hps_emif_mem_0.mem_cs
		output wire [5:0]   emif_hps_emif_mem_0_mem_ca,            //                          .mem_ca
		output wire [0:0]   emif_hps_emif_mem_0_mem_cke,           //                          .mem_cke
		inout  wire [31:0]  emif_hps_emif_mem_0_mem_dq,            //                          .mem_dq
		inout  wire [3:0]   emif_hps_emif_mem_0_mem_dqs_t,         //                          .mem_dqs_t
		inout  wire [3:0]   emif_hps_emif_mem_0_mem_dqs_c,         //                          .mem_dqs_c
		inout  wire [3:0]   emif_hps_emif_mem_0_mem_dmi,           //                          .mem_dmi
		output wire [0:0]   emif_hps_emif_mem_ck_0_mem_ck_t,       //    emif_hps_emif_mem_ck_0.mem_ck_t
		output wire [0:0]   emif_hps_emif_mem_ck_0_mem_ck_c,       //                          .mem_ck_c
		output wire         emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n
		input  wire         emif_hps_emif_oct_0_oct_rzqin,         //       emif_hps_emif_oct_0.oct_rzqin
		input  wire         emif_hps_emif_ref_clk_clk              //     emif_hps_emif_ref_clk.clk
	);

	wire          emif_hps_io96b0_to_hps_ch0_axil_rvalid;    // emif_hps:s0_noc_axi4lite_rvalid -> agilex_hps:io96b0_to_hps_ch0_axil_rvalid
	wire    [2:0] agilex_hps_io96b0_to_hps_axi4_ch0_awprot;  // agilex_hps:io96b0_to_hps_axi4_ch0_awprot -> emif_hps:s0_axi4_awprot
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_arvalid; // agilex_hps:io96b0_to_hps_axi4_ch0_arvalid -> emif_hps:s0_axi4_arvalid
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_bready;  // agilex_hps:io96b0_to_hps_axi4_ch0_bready -> emif_hps:s0_axi4_bready
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_arlock;  // agilex_hps:io96b0_to_hps_axi4_ch0_arlock -> emif_hps:s0_axi4_arlock
	wire    [2:0] agilex_hps_io96b0_to_hps_ch0_axil_arprot;  // agilex_hps:io96b0_to_hps_ch0_axil_arprot -> emif_hps:s0_noc_axi4lite_arprot
	wire   [39:0] agilex_hps_io96b0_to_hps_axi4_ch0_awaddr;  // agilex_hps:io96b0_to_hps_axi4_ch0_awaddr -> emif_hps:s0_axi4_awaddr
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_awvalid; // agilex_hps:io96b0_to_hps_axi4_ch0_awvalid -> emif_hps:s0_axi4_awvalid
	wire          agilex_hps_io96b0_to_hps_ch0_axil_wvalid;  // agilex_hps:io96b0_to_hps_ch0_axil_wvalid -> emif_hps:s0_noc_axi4lite_wvalid
	wire   [26:0] agilex_hps_io96b0_to_hps_ch0_axil_araddr;  // agilex_hps:io96b0_to_hps_ch0_axil_araddr -> emif_hps:s0_noc_axi4lite_araddr
	wire    [6:0] agilex_hps_io96b0_to_hps_axi4_ch0_awid;    // agilex_hps:io96b0_to_hps_axi4_ch0_awid -> emif_hps:s0_axi4_awid
	wire    [1:0] emif_hps_io96b0_to_hps_ch0_axil_rresp;     // emif_hps:s0_noc_axi4lite_rresp -> agilex_hps:io96b0_to_hps_ch0_axil_rresp
	wire    [7:0] agilex_hps_io96b0_to_hps_axi4_ch0_arlen;   // agilex_hps:io96b0_to_hps_axi4_ch0_arlen -> emif_hps:s0_axi4_arlen
	wire    [3:0] agilex_hps_io96b0_to_hps_axi4_ch0_arqos;   // agilex_hps:io96b0_to_hps_axi4_ch0_arqos -> emif_hps:s0_axi4_arqos
	wire    [1:0] emif_hps_io96b0_to_hps_axi4_ch0_bresp;     // emif_hps:s0_axi4_bresp -> agilex_hps:io96b0_to_hps_axi4_ch0_bresp
	wire          emif_hps_io96b0_to_hps_axi4_ch0_clk;       // emif_hps:noc_aclk_0 -> agilex_hps:io96b0_to_hps_axi4_ch0_clk
	wire          emif_hps_io96b0_to_hps_ch0_axil_reset_n;   // emif_hps:s0_noc_axi4lite_reset_n -> agilex_hps:io96b0_to_hps_ch0_axil_reset_n
	wire          emif_hps_io96b0_to_hps_ch0_axil_clk;       // emif_hps:s0_noc_axi4lite_clock -> agilex_hps:io96b0_to_hps_ch0_axil_clk
	wire  [255:0] emif_hps_io96b0_to_hps_axi4_ch0_rdata;     // emif_hps:s0_axi4_rdata -> agilex_hps:io96b0_to_hps_axi4_ch0_rdata
	wire   [13:0] agilex_hps_io96b0_to_hps_axi4_ch0_awuser;  // agilex_hps:io96b0_to_hps_axi4_ch0_awuser -> emif_hps:s0_axi4_awuser
	wire          emif_hps_io96b0_to_hps_axi4_ch0_bvalid;    // emif_hps:s0_axi4_bvalid -> agilex_hps:io96b0_to_hps_axi4_ch0_bvalid
	wire          emif_hps_io96b0_to_hps_ch0_axil_bvalid;    // emif_hps:s0_noc_axi4lite_bvalid -> agilex_hps:io96b0_to_hps_ch0_axil_bvalid
	wire    [6:0] emif_hps_io96b0_to_hps_axi4_ch0_bid;       // emif_hps:s0_axi4_bid -> agilex_hps:io96b0_to_hps_axi4_ch0_bid
	wire   [31:0] emif_hps_io96b0_to_hps_ch0_axil_rdata;     // emif_hps:s0_noc_axi4lite_rdata -> agilex_hps:io96b0_to_hps_ch0_axil_rdata
	wire    [2:0] agilex_hps_io96b0_to_hps_axi4_ch0_arsize;  // agilex_hps:io96b0_to_hps_axi4_ch0_arsize -> emif_hps:s0_axi4_arsize
	wire          emif_hps_io96b0_to_hps_axi4_ch0_rlast;     // emif_hps:s0_axi4_rlast -> agilex_hps:io96b0_to_hps_axi4_ch0_rlast
	wire    [6:0] emif_hps_io96b0_to_hps_axi4_ch0_rid;       // emif_hps:s0_axi4_rid -> agilex_hps:io96b0_to_hps_axi4_ch0_rid
	wire    [2:0] agilex_hps_io96b0_to_hps_ch0_axil_awprot;  // agilex_hps:io96b0_to_hps_ch0_axil_awprot -> emif_hps:s0_noc_axi4lite_awprot
	wire    [2:0] agilex_hps_io96b0_to_hps_axi4_ch0_arprot;  // agilex_hps:io96b0_to_hps_axi4_ch0_arprot -> emif_hps:s0_axi4_arprot
	wire          agilex_hps_io96b0_to_hps_ch0_axil_bready;  // agilex_hps:io96b0_to_hps_ch0_axil_bready -> emif_hps:s0_noc_axi4lite_bready
	wire    [3:0] agilex_hps_io96b0_to_hps_ch0_axil_wstrb;   // agilex_hps:io96b0_to_hps_ch0_axil_wstrb -> emif_hps:s0_noc_axi4lite_wstrb
	wire          emif_hps_io96b0_to_hps_axi4_ch0_rvalid;    // emif_hps:s0_axi4_rvalid -> agilex_hps:io96b0_to_hps_axi4_ch0_rvalid
	wire          emif_hps_io96b0_to_hps_ch0_axil_awready;   // emif_hps:s0_noc_axi4lite_awready -> agilex_hps:io96b0_to_hps_ch0_axil_awready
	wire  [255:0] agilex_hps_io96b0_to_hps_axi4_ch0_wdata;   // agilex_hps:io96b0_to_hps_axi4_ch0_wdata -> emif_hps:s0_axi4_wdata
	wire          emif_hps_io96b0_to_hps_ch0_axil_arready;   // emif_hps:s0_noc_axi4lite_arready -> agilex_hps:io96b0_to_hps_ch0_axil_arready
	wire    [1:0] agilex_hps_io96b0_to_hps_axi4_ch0_awburst; // agilex_hps:io96b0_to_hps_axi4_ch0_awburst -> emif_hps:s0_axi4_awburst
	wire   [39:0] agilex_hps_io96b0_to_hps_axi4_ch0_araddr;  // agilex_hps:io96b0_to_hps_axi4_ch0_araddr -> emif_hps:s0_axi4_araddr
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_wvalid;  // agilex_hps:io96b0_to_hps_axi4_ch0_wvalid -> emif_hps:s0_axi4_wvalid
	wire   [31:0] agilex_hps_io96b0_to_hps_axi4_ch0_wuser;   // agilex_hps:io96b0_to_hps_axi4_ch0_wuser -> emif_hps:s0_axi4_wuser
	wire   [31:0] agilex_hps_io96b0_to_hps_axi4_ch0_wstrb;   // agilex_hps:io96b0_to_hps_axi4_ch0_wstrb -> emif_hps:s0_axi4_wstrb
	wire          agilex_hps_io96b0_to_hps_ch0_axil_arvalid; // agilex_hps:io96b0_to_hps_ch0_axil_arvalid -> emif_hps:s0_noc_axi4lite_arvalid
	wire   [26:0] agilex_hps_io96b0_to_hps_ch0_axil_awaddr;  // agilex_hps:io96b0_to_hps_ch0_axil_awaddr -> emif_hps:s0_noc_axi4lite_awaddr
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_awlock;  // agilex_hps:io96b0_to_hps_axi4_ch0_awlock -> emif_hps:s0_axi4_awlock
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_wlast;   // agilex_hps:io96b0_to_hps_axi4_ch0_wlast -> emif_hps:s0_axi4_wlast
	wire          emif_hps_io96b0_to_hps_axi4_ch0_reset_n;   // emif_hps:noc_rst_n_0 -> agilex_hps:io96b0_to_hps_axi4_ch0_reset_n
	wire    [7:0] agilex_hps_io96b0_to_hps_axi4_ch0_awlen;   // agilex_hps:io96b0_to_hps_axi4_ch0_awlen -> emif_hps:s0_axi4_awlen
	wire    [3:0] agilex_hps_io96b0_to_hps_axi4_ch0_awqos;   // agilex_hps:io96b0_to_hps_axi4_ch0_awqos -> emif_hps:s0_axi4_awqos
	wire    [1:0] emif_hps_io96b0_to_hps_ch0_axil_bresp;     // emif_hps:s0_noc_axi4lite_bresp -> agilex_hps:io96b0_to_hps_ch0_axil_bresp
	wire   [13:0] agilex_hps_io96b0_to_hps_axi4_ch0_aruser;  // agilex_hps:io96b0_to_hps_axi4_ch0_aruser -> emif_hps:s0_axi4_aruser
	wire          agilex_hps_io96b0_to_hps_ch0_axil_rready;  // agilex_hps:io96b0_to_hps_ch0_axil_rready -> emif_hps:s0_noc_axi4lite_rready
	wire          emif_hps_io96b0_to_hps_axi4_ch0_arready;   // emif_hps:s0_axi4_arready -> agilex_hps:io96b0_to_hps_axi4_ch0_arready
	wire          agilex_hps_io96b0_to_hps_axi4_ch0_rready;  // agilex_hps:io96b0_to_hps_axi4_ch0_rready -> emif_hps:s0_axi4_rready
	wire    [1:0] emif_hps_io96b0_to_hps_axi4_ch0_rresp;     // emif_hps:s0_axi4_rresp -> agilex_hps:io96b0_to_hps_axi4_ch0_rresp
	wire    [6:0] agilex_hps_io96b0_to_hps_axi4_ch0_arid;    // agilex_hps:io96b0_to_hps_axi4_ch0_arid -> emif_hps:s0_axi4_arid
	wire          emif_hps_io96b0_to_hps_ch0_axil_wready;    // emif_hps:s0_noc_axi4lite_wready -> agilex_hps:io96b0_to_hps_ch0_axil_wready
	wire   [31:0] emif_hps_io96b0_to_hps_axi4_ch0_ruser;     // emif_hps:s0_axi4_ruser -> agilex_hps:io96b0_to_hps_axi4_ch0_ruser
	wire          emif_hps_io96b0_to_hps_axi4_ch0_awready;   // emif_hps:s0_axi4_awready -> agilex_hps:io96b0_to_hps_axi4_ch0_awready
	wire    [1:0] agilex_hps_io96b0_to_hps_axi4_ch0_arburst; // agilex_hps:io96b0_to_hps_axi4_ch0_arburst -> emif_hps:s0_axi4_arburst
	wire          emif_hps_io96b0_to_hps_axi4_ch0_wready;    // emif_hps:s0_axi4_wready -> agilex_hps:io96b0_to_hps_axi4_ch0_wready
	wire    [2:0] agilex_hps_io96b0_to_hps_axi4_ch0_awsize;  // agilex_hps:io96b0_to_hps_axi4_ch0_awsize -> emif_hps:s0_axi4_awsize
	wire          agilex_hps_io96b0_to_hps_ch0_axil_awvalid; // agilex_hps:io96b0_to_hps_ch0_axil_awvalid -> emif_hps:s0_noc_axi4lite_awvalid
	wire   [31:0] agilex_hps_io96b0_to_hps_ch0_axil_wdata;   // agilex_hps:io96b0_to_hps_ch0_axil_wdata -> emif_hps:s0_noc_axi4lite_wdata

	agilex_hps agilex_hps (
		.h2f_reset_reset                    (h2f_reset_reset),                           //  output,    width = 1,                h2f_reset.reset
		.hps2fpga_axi_clock_clk             (hps2fpga_clk_clk),                          //   input,    width = 1,       hps2fpga_axi_clock.clk
		.hps2fpga_axi_reset_reset           (hps2fpga_rst_reset),                        //   input,    width = 1,       hps2fpga_axi_reset.reset
		.hps2fpga_awid                      (hps2fpga_awid),                             //  output,    width = 4,                 hps2fpga.awid
		.hps2fpga_awaddr                    (hps2fpga_awaddr),                           //  output,   width = 38,                         .awaddr
		.hps2fpga_awlen                     (hps2fpga_awlen),                            //  output,    width = 8,                         .awlen
		.hps2fpga_awsize                    (hps2fpga_awsize),                           //  output,    width = 3,                         .awsize
		.hps2fpga_awburst                   (hps2fpga_awburst),                          //  output,    width = 2,                         .awburst
		.hps2fpga_awlock                    (hps2fpga_awlock),                           //  output,    width = 1,                         .awlock
		.hps2fpga_awcache                   (hps2fpga_awcache),                          //  output,    width = 4,                         .awcache
		.hps2fpga_awprot                    (hps2fpga_awprot),                           //  output,    width = 3,                         .awprot
		.hps2fpga_awvalid                   (hps2fpga_awvalid),                          //  output,    width = 1,                         .awvalid
		.hps2fpga_awready                   (hps2fpga_awready),                          //   input,    width = 1,                         .awready
		.hps2fpga_wdata                     (hps2fpga_wdata),                            //  output,  width = 128,                         .wdata
		.hps2fpga_wstrb                     (hps2fpga_wstrb),                            //  output,   width = 16,                         .wstrb
		.hps2fpga_wlast                     (hps2fpga_wlast),                            //  output,    width = 1,                         .wlast
		.hps2fpga_wvalid                    (hps2fpga_wvalid),                           //  output,    width = 1,                         .wvalid
		.hps2fpga_wready                    (hps2fpga_wready),                           //   input,    width = 1,                         .wready
		.hps2fpga_bid                       (hps2fpga_bid),                              //   input,    width = 4,                         .bid
		.hps2fpga_bresp                     (hps2fpga_bresp),                            //   input,    width = 2,                         .bresp
		.hps2fpga_bvalid                    (hps2fpga_bvalid),                           //   input,    width = 1,                         .bvalid
		.hps2fpga_bready                    (hps2fpga_bready),                           //  output,    width = 1,                         .bready
		.hps2fpga_arid                      (hps2fpga_arid),                             //  output,    width = 4,                         .arid
		.hps2fpga_araddr                    (hps2fpga_araddr),                           //  output,   width = 38,                         .araddr
		.hps2fpga_arlen                     (hps2fpga_arlen),                            //  output,    width = 8,                         .arlen
		.hps2fpga_arsize                    (hps2fpga_arsize),                           //  output,    width = 3,                         .arsize
		.hps2fpga_arburst                   (hps2fpga_arburst),                          //  output,    width = 2,                         .arburst
		.hps2fpga_arlock                    (hps2fpga_arlock),                           //  output,    width = 1,                         .arlock
		.hps2fpga_arcache                   (hps2fpga_arcache),                          //  output,    width = 4,                         .arcache
		.hps2fpga_arprot                    (hps2fpga_arprot),                           //  output,    width = 3,                         .arprot
		.hps2fpga_arvalid                   (hps2fpga_arvalid),                          //  output,    width = 1,                         .arvalid
		.hps2fpga_arready                   (hps2fpga_arready),                          //   input,    width = 1,                         .arready
		.hps2fpga_rid                       (hps2fpga_rid),                              //   input,    width = 4,                         .rid
		.hps2fpga_rdata                     (hps2fpga_rdata),                            //   input,  width = 128,                         .rdata
		.hps2fpga_rresp                     (hps2fpga_rresp),                            //   input,    width = 2,                         .rresp
		.hps2fpga_rlast                     (hps2fpga_rlast),                            //   input,    width = 1,                         .rlast
		.hps2fpga_rvalid                    (hps2fpga_rvalid),                           //   input,    width = 1,                         .rvalid
		.hps2fpga_rready                    (hps2fpga_rready),                           //  output,    width = 1,                         .rready
		.lwhps2fpga_axi_clock_clk           (lwhps2fpga_clk_clk),                        //   input,    width = 1,     lwhps2fpga_axi_clock.clk
		.lwhps2fpga_axi_reset_reset         (lwhps2fpga_rst_reset),                      //   input,    width = 1,     lwhps2fpga_axi_reset.reset
		.lwhps2fpga_awid                    (lwhps2fpga_awid),                           //  output,    width = 4,               lwhps2fpga.awid
		.lwhps2fpga_awaddr                  (lwhps2fpga_awaddr),                         //  output,   width = 29,                         .awaddr
		.lwhps2fpga_awlen                   (lwhps2fpga_awlen),                          //  output,    width = 8,                         .awlen
		.lwhps2fpga_awsize                  (lwhps2fpga_awsize),                         //  output,    width = 3,                         .awsize
		.lwhps2fpga_awburst                 (lwhps2fpga_awburst),                        //  output,    width = 2,                         .awburst
		.lwhps2fpga_awlock                  (lwhps2fpga_awlock),                         //  output,    width = 1,                         .awlock
		.lwhps2fpga_awcache                 (lwhps2fpga_awcache),                        //  output,    width = 4,                         .awcache
		.lwhps2fpga_awprot                  (lwhps2fpga_awprot),                         //  output,    width = 3,                         .awprot
		.lwhps2fpga_awvalid                 (lwhps2fpga_awvalid),                        //  output,    width = 1,                         .awvalid
		.lwhps2fpga_awready                 (lwhps2fpga_awready),                        //   input,    width = 1,                         .awready
		.lwhps2fpga_wdata                   (lwhps2fpga_wdata),                          //  output,   width = 32,                         .wdata
		.lwhps2fpga_wstrb                   (lwhps2fpga_wstrb),                          //  output,    width = 4,                         .wstrb
		.lwhps2fpga_wlast                   (lwhps2fpga_wlast),                          //  output,    width = 1,                         .wlast
		.lwhps2fpga_wvalid                  (lwhps2fpga_wvalid),                         //  output,    width = 1,                         .wvalid
		.lwhps2fpga_wready                  (lwhps2fpga_wready),                         //   input,    width = 1,                         .wready
		.lwhps2fpga_bid                     (lwhps2fpga_bid),                            //   input,    width = 4,                         .bid
		.lwhps2fpga_bresp                   (lwhps2fpga_bresp),                          //   input,    width = 2,                         .bresp
		.lwhps2fpga_bvalid                  (lwhps2fpga_bvalid),                         //   input,    width = 1,                         .bvalid
		.lwhps2fpga_bready                  (lwhps2fpga_bready),                         //  output,    width = 1,                         .bready
		.lwhps2fpga_arid                    (lwhps2fpga_arid),                           //  output,    width = 4,                         .arid
		.lwhps2fpga_araddr                  (lwhps2fpga_araddr),                         //  output,   width = 29,                         .araddr
		.lwhps2fpga_arlen                   (lwhps2fpga_arlen),                          //  output,    width = 8,                         .arlen
		.lwhps2fpga_arsize                  (lwhps2fpga_arsize),                         //  output,    width = 3,                         .arsize
		.lwhps2fpga_arburst                 (lwhps2fpga_arburst),                        //  output,    width = 2,                         .arburst
		.lwhps2fpga_arlock                  (lwhps2fpga_arlock),                         //  output,    width = 1,                         .arlock
		.lwhps2fpga_arcache                 (lwhps2fpga_arcache),                        //  output,    width = 4,                         .arcache
		.lwhps2fpga_arprot                  (lwhps2fpga_arprot),                         //  output,    width = 3,                         .arprot
		.lwhps2fpga_arvalid                 (lwhps2fpga_arvalid),                        //  output,    width = 1,                         .arvalid
		.lwhps2fpga_arready                 (lwhps2fpga_arready),                        //   input,    width = 1,                         .arready
		.lwhps2fpga_rid                     (lwhps2fpga_rid),                            //   input,    width = 4,                         .rid
		.lwhps2fpga_rdata                   (lwhps2fpga_rdata),                          //   input,   width = 32,                         .rdata
		.lwhps2fpga_rresp                   (lwhps2fpga_rresp),                          //   input,    width = 2,                         .rresp
		.lwhps2fpga_rlast                   (lwhps2fpga_rlast),                          //   input,    width = 1,                         .rlast
		.lwhps2fpga_rvalid                  (lwhps2fpga_rvalid),                         //   input,    width = 1,                         .rvalid
		.lwhps2fpga_rready                  (lwhps2fpga_rready),                         //  output,    width = 1,                         .rready
		.emac0_app_rst_reset_n              (),                                          //  output,    width = 1,            emac0_app_rst.reset_n
		.h2f_warm_reset_handshake_reset_req (h2f_warm_reset_handshake_reset_req),        //  output,    width = 1, h2f_warm_reset_handshake.reset_req
		.h2f_warm_reset_handshake_reset_ack (h2f_warm_reset_handshake_reset_ack),        //   input,    width = 1,                         .reset_ack
		.hps_io_hps_osc_clk                 (hps_io_hps_osc_clk),                        //   input,    width = 1,                   hps_io.hps_osc_clk
		.hps_io_sdmmc_data0                 (hps_io_sdmmc_data0),                        //   inout,    width = 1,                         .sdmmc_data0
		.hps_io_sdmmc_data1                 (hps_io_sdmmc_data1),                        //   inout,    width = 1,                         .sdmmc_data1
		.hps_io_sdmmc_cclk                  (hps_io_sdmmc_cclk),                         //  output,    width = 1,                         .sdmmc_cclk
		.hps_io_sdmmc_data2                 (hps_io_sdmmc_data2),                        //   inout,    width = 1,                         .sdmmc_data2
		.hps_io_sdmmc_data3                 (hps_io_sdmmc_data3),                        //   inout,    width = 1,                         .sdmmc_data3
		.hps_io_sdmmc_cmd                   (hps_io_sdmmc_cmd),                          //   inout,    width = 1,                         .sdmmc_cmd
		.hps_io_usb0_clk                    (hps_io_usb0_clk),                           //   input,    width = 1,                         .usb0_clk
		.hps_io_usb0_stp                    (hps_io_usb0_stp),                           //  output,    width = 1,                         .usb0_stp
		.hps_io_usb0_dir                    (hps_io_usb0_dir),                           //   input,    width = 1,                         .usb0_dir
		.hps_io_usb0_data0                  (hps_io_usb0_data0),                         //   inout,    width = 1,                         .usb0_data0
		.hps_io_usb0_data1                  (hps_io_usb0_data1),                         //   inout,    width = 1,                         .usb0_data1
		.hps_io_usb0_nxt                    (hps_io_usb0_nxt),                           //   input,    width = 1,                         .usb0_nxt
		.hps_io_usb0_data2                  (hps_io_usb0_data2),                         //   inout,    width = 1,                         .usb0_data2
		.hps_io_usb0_data3                  (hps_io_usb0_data3),                         //   inout,    width = 1,                         .usb0_data3
		.hps_io_usb0_data4                  (hps_io_usb0_data4),                         //   inout,    width = 1,                         .usb0_data4
		.hps_io_usb0_data5                  (hps_io_usb0_data5),                         //   inout,    width = 1,                         .usb0_data5
		.hps_io_usb0_data6                  (hps_io_usb0_data6),                         //   inout,    width = 1,                         .usb0_data6
		.hps_io_usb0_data7                  (hps_io_usb0_data7),                         //   inout,    width = 1,                         .usb0_data7
		.hps_io_emac0_tx_clk                (hps_io_emac0_tx_clk),                       //  output,    width = 1,                         .emac0_tx_clk
		.hps_io_emac0_tx_ctl                (hps_io_emac0_tx_ctl),                       //  output,    width = 1,                         .emac0_tx_ctl
		.hps_io_emac0_rx_clk                (hps_io_emac0_rx_clk),                       //   input,    width = 1,                         .emac0_rx_clk
		.hps_io_emac0_rx_ctl                (hps_io_emac0_rx_ctl),                       //   input,    width = 1,                         .emac0_rx_ctl
		.hps_io_emac0_txd0                  (hps_io_emac0_txd0),                         //  output,    width = 1,                         .emac0_txd0
		.hps_io_emac0_txd1                  (hps_io_emac0_txd1),                         //  output,    width = 1,                         .emac0_txd1
		.hps_io_emac0_rxd0                  (hps_io_emac0_rxd0),                         //   input,    width = 1,                         .emac0_rxd0
		.hps_io_emac0_rxd1                  (hps_io_emac0_rxd1),                         //   input,    width = 1,                         .emac0_rxd1
		.hps_io_emac0_txd2                  (hps_io_emac0_txd2),                         //  output,    width = 1,                         .emac0_txd2
		.hps_io_emac0_txd3                  (hps_io_emac0_txd3),                         //  output,    width = 1,                         .emac0_txd3
		.hps_io_emac0_rxd2                  (hps_io_emac0_rxd2),                         //   input,    width = 1,                         .emac0_rxd2
		.hps_io_emac0_rxd3                  (hps_io_emac0_rxd3),                         //   input,    width = 1,                         .emac0_rxd3
		.hps_io_mdio0_mdio                  (hps_io_mdio0_mdio),                         //   inout,    width = 1,                         .mdio0_mdio
		.hps_io_mdio0_mdc                   (hps_io_mdio0_mdc),                          //  output,    width = 1,                         .mdio0_mdc
		.hps_io_uart1_tx                    (hps_io_uart1_tx),                           //  output,    width = 1,                         .uart1_tx
		.hps_io_uart1_rx                    (hps_io_uart1_rx),                           //   input,    width = 1,                         .uart1_rx
		.hps_io_i2c1_sda                    (hps_io_i2c1_sda),                           //   inout,    width = 1,                         .i2c1_sda
		.hps_io_i2c1_scl                    (hps_io_i2c1_scl),                           //   inout,    width = 1,                         .i2c1_scl
		.hps_io_gpio28                      (hps_io_gpio28),                             //   inout,    width = 1,                         .gpio28
		.hps_io_gpio34                      (hps_io_gpio34),                             //   inout,    width = 1,                         .gpio34
		.hps_io_gpio40                      (hps_io_gpio40),                             //   inout,    width = 1,                         .gpio40
		.hps_io_gpio41                      (hps_io_gpio41),                             //   inout,    width = 1,                         .gpio41
		.fpga2hps_interrupt_irq1_irq        (f2h_irq1_in_irq),                           //   input,   width = 32,  fpga2hps_interrupt_irq1.irq
		.fpga2hps_interrupt_irq0_irq        (f2h_irq0_in_irq),                           //   input,   width = 32,  fpga2hps_interrupt_irq0.irq
		.f2sdram_axi_clock_clk              (f2sdram_clk_clk),                           //   input,    width = 1,        f2sdram_axi_clock.clk
		.f2sdram_axi_reset_reset            (f2sdram_rst_reset),                         //   input,    width = 1,        f2sdram_axi_reset.reset
		.f2sdram_araddr                     (f2sdram_araddr),                            //   input,   width = 32,                  f2sdram.araddr
		.f2sdram_arburst                    (f2sdram_arburst),                           //   input,    width = 2,                         .arburst
		.f2sdram_arcache                    (f2sdram_arcache),                           //   input,    width = 4,                         .arcache
		.f2sdram_arid                       (f2sdram_arid),                              //   input,    width = 5,                         .arid
		.f2sdram_arlen                      (f2sdram_arlen),                             //   input,    width = 8,                         .arlen
		.f2sdram_arlock                     (f2sdram_arlock),                            //   input,    width = 1,                         .arlock
		.f2sdram_arprot                     (f2sdram_arprot),                            //   input,    width = 3,                         .arprot
		.f2sdram_arqos                      (f2sdram_arqos),                             //   input,    width = 4,                         .arqos
		.f2sdram_arready                    (f2sdram_arready),                           //  output,    width = 1,                         .arready
		.f2sdram_arsize                     (f2sdram_arsize),                            //   input,    width = 3,                         .arsize
		.f2sdram_arvalid                    (f2sdram_arvalid),                           //   input,    width = 1,                         .arvalid
		.f2sdram_awaddr                     (f2sdram_awaddr),                            //   input,   width = 32,                         .awaddr
		.f2sdram_awburst                    (f2sdram_awburst),                           //   input,    width = 2,                         .awburst
		.f2sdram_awcache                    (f2sdram_awcache),                           //   input,    width = 4,                         .awcache
		.f2sdram_awid                       (f2sdram_awid),                              //   input,    width = 5,                         .awid
		.f2sdram_awlen                      (f2sdram_awlen),                             //   input,    width = 8,                         .awlen
		.f2sdram_awlock                     (f2sdram_awlock),                            //   input,    width = 1,                         .awlock
		.f2sdram_awprot                     (f2sdram_awprot),                            //   input,    width = 3,                         .awprot
		.f2sdram_awqos                      (f2sdram_awqos),                             //   input,    width = 4,                         .awqos
		.f2sdram_awready                    (f2sdram_awready),                           //  output,    width = 1,                         .awready
		.f2sdram_awsize                     (f2sdram_awsize),                            //   input,    width = 3,                         .awsize
		.f2sdram_awvalid                    (f2sdram_awvalid),                           //   input,    width = 1,                         .awvalid
		.f2sdram_bid                        (f2sdram_bid),                               //  output,    width = 5,                         .bid
		.f2sdram_bready                     (f2sdram_bready),                            //   input,    width = 1,                         .bready
		.f2sdram_bresp                      (f2sdram_bresp),                             //  output,    width = 2,                         .bresp
		.f2sdram_bvalid                     (f2sdram_bvalid),                            //  output,    width = 1,                         .bvalid
		.f2sdram_rdata                      (f2sdram_rdata),                             //  output,  width = 256,                         .rdata
		.f2sdram_rid                        (f2sdram_rid),                               //  output,    width = 5,                         .rid
		.f2sdram_rlast                      (f2sdram_rlast),                             //  output,    width = 1,                         .rlast
		.f2sdram_rready                     (f2sdram_rready),                            //   input,    width = 1,                         .rready
		.f2sdram_rresp                      (f2sdram_rresp),                             //  output,    width = 2,                         .rresp
		.f2sdram_rvalid                     (f2sdram_rvalid),                            //  output,    width = 1,                         .rvalid
		.f2sdram_wdata                      (f2sdram_wdata),                             //   input,  width = 256,                         .wdata
		.f2sdram_wlast                      (f2sdram_wlast),                             //   input,    width = 1,                         .wlast
		.f2sdram_wready                     (f2sdram_wready),                            //  output,    width = 1,                         .wready
		.f2sdram_wstrb                      (f2sdram_wstrb),                             //   input,   width = 32,                         .wstrb
		.f2sdram_wvalid                     (f2sdram_wvalid),                            //   input,    width = 1,                         .wvalid
		.f2sdram_aruser                     (f2sdram_aruser),                            //   input,    width = 8,                         .aruser
		.f2sdram_awuser                     (f2sdram_awuser),                            //   input,    width = 8,                         .awuser
		.f2sdram_wuser                      (f2sdram_wuser),                             //   input,    width = 8,                         .wuser
		.f2sdram_buser                      (f2sdram_buser),                             //  output,    width = 8,                         .buser
		.f2sdram_arregion                   (f2sdram_arregion),                          //   input,    width = 4,                         .arregion
		.f2sdram_ruser                      (f2sdram_ruser),                             //  output,    width = 8,                         .ruser
		.f2sdram_awregion                   (f2sdram_awregion),                          //   input,    width = 4,                         .awregion
		.io96b0_to_hps_ch0_axil_clk         (emif_hps_io96b0_to_hps_ch0_axil_clk),       //   input,    width = 1,            io96b0_to_hps.ch0_axil_clk
		.io96b0_to_hps_ch0_axil_reset_n     (emif_hps_io96b0_to_hps_ch0_axil_reset_n),   //   input,    width = 1,                         .ch0_axil_reset_n
		.io96b0_to_hps_ch0_axil_arready     (emif_hps_io96b0_to_hps_ch0_axil_arready),   //   input,    width = 1,                         .ch0_axil_arready
		.io96b0_to_hps_ch0_axil_awready     (emif_hps_io96b0_to_hps_ch0_axil_awready),   //   input,    width = 1,                         .ch0_axil_awready
		.io96b0_to_hps_ch0_axil_bresp       (emif_hps_io96b0_to_hps_ch0_axil_bresp),     //   input,    width = 2,                         .ch0_axil_bresp
		.io96b0_to_hps_ch0_axil_bvalid      (emif_hps_io96b0_to_hps_ch0_axil_bvalid),    //   input,    width = 1,                         .ch0_axil_bvalid
		.io96b0_to_hps_ch0_axil_rdata       (emif_hps_io96b0_to_hps_ch0_axil_rdata),     //   input,   width = 32,                         .ch0_axil_rdata
		.io96b0_to_hps_ch0_axil_rresp       (emif_hps_io96b0_to_hps_ch0_axil_rresp),     //   input,    width = 2,                         .ch0_axil_rresp
		.io96b0_to_hps_ch0_axil_rvalid      (emif_hps_io96b0_to_hps_ch0_axil_rvalid),    //   input,    width = 1,                         .ch0_axil_rvalid
		.io96b0_to_hps_ch0_axil_wready      (emif_hps_io96b0_to_hps_ch0_axil_wready),    //   input,    width = 1,                         .ch0_axil_wready
		.io96b0_to_hps_ch0_axil_araddr      (agilex_hps_io96b0_to_hps_ch0_axil_araddr),  //  output,   width = 27,                         .ch0_axil_araddr
		.io96b0_to_hps_ch0_axil_arvalid     (agilex_hps_io96b0_to_hps_ch0_axil_arvalid), //  output,    width = 1,                         .ch0_axil_arvalid
		.io96b0_to_hps_ch0_axil_awaddr      (agilex_hps_io96b0_to_hps_ch0_axil_awaddr),  //  output,   width = 27,                         .ch0_axil_awaddr
		.io96b0_to_hps_ch0_axil_awvalid     (agilex_hps_io96b0_to_hps_ch0_axil_awvalid), //  output,    width = 1,                         .ch0_axil_awvalid
		.io96b0_to_hps_ch0_axil_bready      (agilex_hps_io96b0_to_hps_ch0_axil_bready),  //  output,    width = 1,                         .ch0_axil_bready
		.io96b0_to_hps_ch0_axil_rready      (agilex_hps_io96b0_to_hps_ch0_axil_rready),  //  output,    width = 1,                         .ch0_axil_rready
		.io96b0_to_hps_ch0_axil_wdata       (agilex_hps_io96b0_to_hps_ch0_axil_wdata),   //  output,   width = 32,                         .ch0_axil_wdata
		.io96b0_to_hps_ch0_axil_wstrb       (agilex_hps_io96b0_to_hps_ch0_axil_wstrb),   //  output,    width = 4,                         .ch0_axil_wstrb
		.io96b0_to_hps_ch0_axil_wvalid      (agilex_hps_io96b0_to_hps_ch0_axil_wvalid),  //  output,    width = 1,                         .ch0_axil_wvalid
		.io96b0_to_hps_ch0_axil_arprot      (agilex_hps_io96b0_to_hps_ch0_axil_arprot),  //  output,    width = 3,                         .ch0_axil_arprot
		.io96b0_to_hps_ch0_axil_awprot      (agilex_hps_io96b0_to_hps_ch0_axil_awprot),  //  output,    width = 3,                         .ch0_axil_awprot
		.io96b0_to_hps_axi4_ch0_clk         (emif_hps_io96b0_to_hps_axi4_ch0_clk),       //   input,    width = 1,                         .axi4_ch0_clk
		.io96b0_to_hps_axi4_ch0_reset_n     (emif_hps_io96b0_to_hps_axi4_ch0_reset_n),   //   input,    width = 1,                         .axi4_ch0_reset_n
		.io96b0_to_hps_axi4_ch0_arready     (emif_hps_io96b0_to_hps_axi4_ch0_arready),   //   input,    width = 1,                         .axi4_ch0_arready
		.io96b0_to_hps_axi4_ch0_awready     (emif_hps_io96b0_to_hps_axi4_ch0_awready),   //   input,    width = 1,                         .axi4_ch0_awready
		.io96b0_to_hps_axi4_ch0_bid         (emif_hps_io96b0_to_hps_axi4_ch0_bid),       //   input,    width = 7,                         .axi4_ch0_bid
		.io96b0_to_hps_axi4_ch0_bresp       (emif_hps_io96b0_to_hps_axi4_ch0_bresp),     //   input,    width = 2,                         .axi4_ch0_bresp
		.io96b0_to_hps_axi4_ch0_bvalid      (emif_hps_io96b0_to_hps_axi4_ch0_bvalid),    //   input,    width = 1,                         .axi4_ch0_bvalid
		.io96b0_to_hps_axi4_ch0_rdata       (emif_hps_io96b0_to_hps_axi4_ch0_rdata),     //   input,  width = 256,                         .axi4_ch0_rdata
		.io96b0_to_hps_axi4_ch0_rid         (emif_hps_io96b0_to_hps_axi4_ch0_rid),       //   input,    width = 7,                         .axi4_ch0_rid
		.io96b0_to_hps_axi4_ch0_rlast       (emif_hps_io96b0_to_hps_axi4_ch0_rlast),     //   input,    width = 1,                         .axi4_ch0_rlast
		.io96b0_to_hps_axi4_ch0_rresp       (emif_hps_io96b0_to_hps_axi4_ch0_rresp),     //   input,    width = 2,                         .axi4_ch0_rresp
		.io96b0_to_hps_axi4_ch0_ruser       (emif_hps_io96b0_to_hps_axi4_ch0_ruser),     //   input,   width = 32,                         .axi4_ch0_ruser
		.io96b0_to_hps_axi4_ch0_rvalid      (emif_hps_io96b0_to_hps_axi4_ch0_rvalid),    //   input,    width = 1,                         .axi4_ch0_rvalid
		.io96b0_to_hps_axi4_ch0_wready      (emif_hps_io96b0_to_hps_axi4_ch0_wready),    //   input,    width = 1,                         .axi4_ch0_wready
		.io96b0_to_hps_axi4_ch0_araddr      (agilex_hps_io96b0_to_hps_axi4_ch0_araddr),  //  output,   width = 40,                         .axi4_ch0_araddr
		.io96b0_to_hps_axi4_ch0_arburst     (agilex_hps_io96b0_to_hps_axi4_ch0_arburst), //  output,    width = 2,                         .axi4_ch0_arburst
		.io96b0_to_hps_axi4_ch0_arid        (agilex_hps_io96b0_to_hps_axi4_ch0_arid),    //  output,    width = 7,                         .axi4_ch0_arid
		.io96b0_to_hps_axi4_ch0_arlen       (agilex_hps_io96b0_to_hps_axi4_ch0_arlen),   //  output,    width = 8,                         .axi4_ch0_arlen
		.io96b0_to_hps_axi4_ch0_arlock      (agilex_hps_io96b0_to_hps_axi4_ch0_arlock),  //  output,    width = 1,                         .axi4_ch0_arlock
		.io96b0_to_hps_axi4_ch0_arqos       (agilex_hps_io96b0_to_hps_axi4_ch0_arqos),   //  output,    width = 4,                         .axi4_ch0_arqos
		.io96b0_to_hps_axi4_ch0_arsize      (agilex_hps_io96b0_to_hps_axi4_ch0_arsize),  //  output,    width = 3,                         .axi4_ch0_arsize
		.io96b0_to_hps_axi4_ch0_aruser      (agilex_hps_io96b0_to_hps_axi4_ch0_aruser),  //  output,   width = 14,                         .axi4_ch0_aruser
		.io96b0_to_hps_axi4_ch0_arvalid     (agilex_hps_io96b0_to_hps_axi4_ch0_arvalid), //  output,    width = 1,                         .axi4_ch0_arvalid
		.io96b0_to_hps_axi4_ch0_awaddr      (agilex_hps_io96b0_to_hps_axi4_ch0_awaddr),  //  output,   width = 40,                         .axi4_ch0_awaddr
		.io96b0_to_hps_axi4_ch0_awburst     (agilex_hps_io96b0_to_hps_axi4_ch0_awburst), //  output,    width = 2,                         .axi4_ch0_awburst
		.io96b0_to_hps_axi4_ch0_awid        (agilex_hps_io96b0_to_hps_axi4_ch0_awid),    //  output,    width = 7,                         .axi4_ch0_awid
		.io96b0_to_hps_axi4_ch0_awlen       (agilex_hps_io96b0_to_hps_axi4_ch0_awlen),   //  output,    width = 8,                         .axi4_ch0_awlen
		.io96b0_to_hps_axi4_ch0_awlock      (agilex_hps_io96b0_to_hps_axi4_ch0_awlock),  //  output,    width = 1,                         .axi4_ch0_awlock
		.io96b0_to_hps_axi4_ch0_awqos       (agilex_hps_io96b0_to_hps_axi4_ch0_awqos),   //  output,    width = 4,                         .axi4_ch0_awqos
		.io96b0_to_hps_axi4_ch0_awsize      (agilex_hps_io96b0_to_hps_axi4_ch0_awsize),  //  output,    width = 3,                         .axi4_ch0_awsize
		.io96b0_to_hps_axi4_ch0_awuser      (agilex_hps_io96b0_to_hps_axi4_ch0_awuser),  //  output,   width = 14,                         .axi4_ch0_awuser
		.io96b0_to_hps_axi4_ch0_awvalid     (agilex_hps_io96b0_to_hps_axi4_ch0_awvalid), //  output,    width = 1,                         .axi4_ch0_awvalid
		.io96b0_to_hps_axi4_ch0_bready      (agilex_hps_io96b0_to_hps_axi4_ch0_bready),  //  output,    width = 1,                         .axi4_ch0_bready
		.io96b0_to_hps_axi4_ch0_rready      (agilex_hps_io96b0_to_hps_axi4_ch0_rready),  //  output,    width = 1,                         .axi4_ch0_rready
		.io96b0_to_hps_axi4_ch0_wdata       (agilex_hps_io96b0_to_hps_axi4_ch0_wdata),   //  output,  width = 256,                         .axi4_ch0_wdata
		.io96b0_to_hps_axi4_ch0_wlast       (agilex_hps_io96b0_to_hps_axi4_ch0_wlast),   //  output,    width = 1,                         .axi4_ch0_wlast
		.io96b0_to_hps_axi4_ch0_wstrb       (agilex_hps_io96b0_to_hps_axi4_ch0_wstrb),   //  output,   width = 32,                         .axi4_ch0_wstrb
		.io96b0_to_hps_axi4_ch0_wuser       (agilex_hps_io96b0_to_hps_axi4_ch0_wuser),   //  output,   width = 32,                         .axi4_ch0_wuser
		.io96b0_to_hps_axi4_ch0_wvalid      (agilex_hps_io96b0_to_hps_axi4_ch0_wvalid),  //  output,    width = 1,                         .axi4_ch0_wvalid
		.io96b0_to_hps_axi4_ch0_arprot      (agilex_hps_io96b0_to_hps_axi4_ch0_arprot),  //  output,    width = 3,                         .axi4_ch0_arprot
		.io96b0_to_hps_axi4_ch0_awprot      (agilex_hps_io96b0_to_hps_axi4_ch0_awprot)   //  output,    width = 3,                         .axi4_ch0_awprot
	);

	emif_io96b_hps emif_hps (
		.s0_noc_axi4lite_clock   (emif_hps_io96b0_to_hps_ch0_axil_clk),       //  output,    width = 1, io96b0_to_hps.ch0_axil_clk
		.s0_noc_axi4lite_reset_n (emif_hps_io96b0_to_hps_ch0_axil_reset_n),   //  output,    width = 1,              .ch0_axil_reset_n
		.s0_noc_axi4lite_awaddr  (agilex_hps_io96b0_to_hps_ch0_axil_awaddr),  //   input,   width = 27,              .ch0_axil_awaddr
		.s0_noc_axi4lite_awvalid (agilex_hps_io96b0_to_hps_ch0_axil_awvalid), //   input,    width = 1,              .ch0_axil_awvalid
		.s0_noc_axi4lite_awready (emif_hps_io96b0_to_hps_ch0_axil_awready),   //  output,    width = 1,              .ch0_axil_awready
		.s0_noc_axi4lite_araddr  (agilex_hps_io96b0_to_hps_ch0_axil_araddr),  //   input,   width = 27,              .ch0_axil_araddr
		.s0_noc_axi4lite_arvalid (agilex_hps_io96b0_to_hps_ch0_axil_arvalid), //   input,    width = 1,              .ch0_axil_arvalid
		.s0_noc_axi4lite_arready (emif_hps_io96b0_to_hps_ch0_axil_arready),   //  output,    width = 1,              .ch0_axil_arready
		.s0_noc_axi4lite_wdata   (agilex_hps_io96b0_to_hps_ch0_axil_wdata),   //   input,   width = 32,              .ch0_axil_wdata
		.s0_noc_axi4lite_wvalid  (agilex_hps_io96b0_to_hps_ch0_axil_wvalid),  //   input,    width = 1,              .ch0_axil_wvalid
		.s0_noc_axi4lite_wready  (emif_hps_io96b0_to_hps_ch0_axil_wready),    //  output,    width = 1,              .ch0_axil_wready
		.s0_noc_axi4lite_rresp   (emif_hps_io96b0_to_hps_ch0_axil_rresp),     //  output,    width = 2,              .ch0_axil_rresp
		.s0_noc_axi4lite_rdata   (emif_hps_io96b0_to_hps_ch0_axil_rdata),     //  output,   width = 32,              .ch0_axil_rdata
		.s0_noc_axi4lite_rvalid  (emif_hps_io96b0_to_hps_ch0_axil_rvalid),    //  output,    width = 1,              .ch0_axil_rvalid
		.s0_noc_axi4lite_rready  (agilex_hps_io96b0_to_hps_ch0_axil_rready),  //   input,    width = 1,              .ch0_axil_rready
		.s0_noc_axi4lite_bresp   (emif_hps_io96b0_to_hps_ch0_axil_bresp),     //  output,    width = 2,              .ch0_axil_bresp
		.s0_noc_axi4lite_bvalid  (emif_hps_io96b0_to_hps_ch0_axil_bvalid),    //  output,    width = 1,              .ch0_axil_bvalid
		.s0_noc_axi4lite_bready  (agilex_hps_io96b0_to_hps_ch0_axil_bready),  //   input,    width = 1,              .ch0_axil_bready
		.s0_noc_axi4lite_awprot  (agilex_hps_io96b0_to_hps_ch0_axil_awprot),  //   input,    width = 3,              .ch0_axil_awprot
		.s0_noc_axi4lite_arprot  (agilex_hps_io96b0_to_hps_ch0_axil_arprot),  //   input,    width = 3,              .ch0_axil_arprot
		.s0_noc_axi4lite_wstrb   (agilex_hps_io96b0_to_hps_ch0_axil_wstrb),   //   input,    width = 4,              .ch0_axil_wstrb
		.s0_axi4_awaddr          (agilex_hps_io96b0_to_hps_axi4_ch0_awaddr),  //   input,   width = 40,              .axi4_ch0_awaddr
		.s0_axi4_awburst         (agilex_hps_io96b0_to_hps_axi4_ch0_awburst), //   input,    width = 2,              .axi4_ch0_awburst
		.s0_axi4_awid            (agilex_hps_io96b0_to_hps_axi4_ch0_awid),    //   input,    width = 7,              .axi4_ch0_awid
		.s0_axi4_awlen           (agilex_hps_io96b0_to_hps_axi4_ch0_awlen),   //   input,    width = 8,              .axi4_ch0_awlen
		.s0_axi4_awlock          (agilex_hps_io96b0_to_hps_axi4_ch0_awlock),  //   input,    width = 1,              .axi4_ch0_awlock
		.s0_axi4_awqos           (agilex_hps_io96b0_to_hps_axi4_ch0_awqos),   //   input,    width = 4,              .axi4_ch0_awqos
		.s0_axi4_awsize          (agilex_hps_io96b0_to_hps_axi4_ch0_awsize),  //   input,    width = 3,              .axi4_ch0_awsize
		.s0_axi4_awvalid         (agilex_hps_io96b0_to_hps_axi4_ch0_awvalid), //   input,    width = 1,              .axi4_ch0_awvalid
		.s0_axi4_awuser          (agilex_hps_io96b0_to_hps_axi4_ch0_awuser),  //   input,   width = 14,              .axi4_ch0_awuser
		.s0_axi4_awprot          (agilex_hps_io96b0_to_hps_axi4_ch0_awprot),  //   input,    width = 3,              .axi4_ch0_awprot
		.s0_axi4_awready         (emif_hps_io96b0_to_hps_axi4_ch0_awready),   //  output,    width = 1,              .axi4_ch0_awready
		.s0_axi4_araddr          (agilex_hps_io96b0_to_hps_axi4_ch0_araddr),  //   input,   width = 40,              .axi4_ch0_araddr
		.s0_axi4_arburst         (agilex_hps_io96b0_to_hps_axi4_ch0_arburst), //   input,    width = 2,              .axi4_ch0_arburst
		.s0_axi4_arid            (agilex_hps_io96b0_to_hps_axi4_ch0_arid),    //   input,    width = 7,              .axi4_ch0_arid
		.s0_axi4_arlen           (agilex_hps_io96b0_to_hps_axi4_ch0_arlen),   //   input,    width = 8,              .axi4_ch0_arlen
		.s0_axi4_arlock          (agilex_hps_io96b0_to_hps_axi4_ch0_arlock),  //   input,    width = 1,              .axi4_ch0_arlock
		.s0_axi4_arqos           (agilex_hps_io96b0_to_hps_axi4_ch0_arqos),   //   input,    width = 4,              .axi4_ch0_arqos
		.s0_axi4_arsize          (agilex_hps_io96b0_to_hps_axi4_ch0_arsize),  //   input,    width = 3,              .axi4_ch0_arsize
		.s0_axi4_arvalid         (agilex_hps_io96b0_to_hps_axi4_ch0_arvalid), //   input,    width = 1,              .axi4_ch0_arvalid
		.s0_axi4_aruser          (agilex_hps_io96b0_to_hps_axi4_ch0_aruser),  //   input,   width = 14,              .axi4_ch0_aruser
		.s0_axi4_arprot          (agilex_hps_io96b0_to_hps_axi4_ch0_arprot),  //   input,    width = 3,              .axi4_ch0_arprot
		.s0_axi4_arready         (emif_hps_io96b0_to_hps_axi4_ch0_arready),   //  output,    width = 1,              .axi4_ch0_arready
		.s0_axi4_wdata           (agilex_hps_io96b0_to_hps_axi4_ch0_wdata),   //   input,  width = 256,              .axi4_ch0_wdata
		.s0_axi4_wstrb           (agilex_hps_io96b0_to_hps_axi4_ch0_wstrb),   //   input,   width = 32,              .axi4_ch0_wstrb
		.s0_axi4_wlast           (agilex_hps_io96b0_to_hps_axi4_ch0_wlast),   //   input,    width = 1,              .axi4_ch0_wlast
		.s0_axi4_wvalid          (agilex_hps_io96b0_to_hps_axi4_ch0_wvalid),  //   input,    width = 1,              .axi4_ch0_wvalid
		.s0_axi4_wready          (emif_hps_io96b0_to_hps_axi4_ch0_wready),    //  output,    width = 1,              .axi4_ch0_wready
		.s0_axi4_bready          (agilex_hps_io96b0_to_hps_axi4_ch0_bready),  //   input,    width = 1,              .axi4_ch0_bready
		.s0_axi4_bid             (emif_hps_io96b0_to_hps_axi4_ch0_bid),       //  output,    width = 7,              .axi4_ch0_bid
		.s0_axi4_bresp           (emif_hps_io96b0_to_hps_axi4_ch0_bresp),     //  output,    width = 2,              .axi4_ch0_bresp
		.s0_axi4_bvalid          (emif_hps_io96b0_to_hps_axi4_ch0_bvalid),    //  output,    width = 1,              .axi4_ch0_bvalid
		.s0_axi4_rready          (agilex_hps_io96b0_to_hps_axi4_ch0_rready),  //   input,    width = 1,              .axi4_ch0_rready
		.s0_axi4_rdata           (emif_hps_io96b0_to_hps_axi4_ch0_rdata),     //  output,  width = 256,              .axi4_ch0_rdata
		.s0_axi4_rid             (emif_hps_io96b0_to_hps_axi4_ch0_rid),       //  output,    width = 7,              .axi4_ch0_rid
		.s0_axi4_rlast           (emif_hps_io96b0_to_hps_axi4_ch0_rlast),     //  output,    width = 1,              .axi4_ch0_rlast
		.s0_axi4_rresp           (emif_hps_io96b0_to_hps_axi4_ch0_rresp),     //  output,    width = 2,              .axi4_ch0_rresp
		.s0_axi4_rvalid          (emif_hps_io96b0_to_hps_axi4_ch0_rvalid),    //  output,    width = 1,              .axi4_ch0_rvalid
		.noc_aclk_0              (emif_hps_io96b0_to_hps_axi4_ch0_clk),       //  output,    width = 1,              .axi4_ch0_clk
		.noc_rst_n_0             (emif_hps_io96b0_to_hps_axi4_ch0_reset_n),   //  output,    width = 1,              .axi4_ch0_reset_n
		.s0_axi4_wuser           (agilex_hps_io96b0_to_hps_axi4_ch0_wuser),   //   input,   width = 32,              .axi4_ch0_wuser
		.s0_axi4_ruser           (emif_hps_io96b0_to_hps_axi4_ch0_ruser),     //  output,   width = 32,              .axi4_ch0_ruser
		.mem_0_cs                (emif_hps_emif_mem_0_mem_cs),                //  output,    width = 1,         mem_0.mem_cs
		.mem_0_ca                (emif_hps_emif_mem_0_mem_ca),                //  output,    width = 6,              .mem_ca
		.mem_0_cke               (emif_hps_emif_mem_0_mem_cke),               //  output,    width = 1,              .mem_cke
		.mem_0_dq                (emif_hps_emif_mem_0_mem_dq),                //   inout,   width = 32,              .mem_dq
		.mem_0_dqs_t             (emif_hps_emif_mem_0_mem_dqs_t),             //   inout,    width = 4,              .mem_dqs_t
		.mem_0_dqs_c             (emif_hps_emif_mem_0_mem_dqs_c),             //   inout,    width = 4,              .mem_dqs_c
		.mem_0_dmi               (emif_hps_emif_mem_0_mem_dmi),               //   inout,    width = 4,              .mem_dmi
		.mem_0_ck_t              (emif_hps_emif_mem_ck_0_mem_ck_t),           //  output,    width = 1,      mem_ck_0.mem_ck_t
		.mem_0_ck_c              (emif_hps_emif_mem_ck_0_mem_ck_c),           //  output,    width = 1,              .mem_ck_c
		.mem_0_reset_n           (emif_hps_emif_mem_reset_n_mem_reset_n),     //  output,    width = 1,   mem_reset_n.mem_reset_n
		.oct_rzqin_0             (emif_hps_emif_oct_0_oct_rzqin),             //   input,    width = 1,         oct_0.oct_rzqin
		.ref_clk                 (emif_hps_emif_ref_clk_clk)                  //   input,    width = 1,       ref_clk.clk
	);

endmodule
