// EMIF_Qsys_clock_bridge_0.v

// Generated using ACDS version 25.3.1 100

`timescale 1 ps / 1 ps
module EMIF_Qsys_clock_bridge_0 (
		input  wire  in_clk,  //  in_clk.clk, Clock Input
		output wire  out_clk  // out_clk.clk, Clock Output
	);

	assign out_clk = in_clk;

endmodule
