source [file join [file dirname [info script]] ./../../../ip/peripheral_subsys/button_pio/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/peripheral_subsys/led_pio/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/peripheral_subsys/dipsw_pio/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/peripheral_subsys/sysid/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/peripheral_subsys/periph_clk/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/peripheral_subsys/periph_rst_in/sim/common/riviera_files.tcl]
source [file join [file dirname [info script]] ./../../../ip/peripheral_subsys/pb_cpu_0/sim/common/riviera_files.tcl]

namespace eval peripheral_subsys {
  proc get_design_libraries {} {
    set libraries [dict create]
    set libraries [dict merge $libraries [button_pio::get_design_libraries]]
    set libraries [dict merge $libraries [led_pio::get_design_libraries]]
    set libraries [dict merge $libraries [dipsw_pio::get_design_libraries]]
    set libraries [dict merge $libraries [sysid::get_design_libraries]]
    set libraries [dict merge $libraries [periph_clk::get_design_libraries]]
    set libraries [dict merge $libraries [periph_rst_in::get_design_libraries]]
    set libraries [dict merge $libraries [pb_cpu_0::get_design_libraries]]
    dict set libraries altera_merlin_master_translator_193 1
    dict set libraries altera_merlin_slave_translator_191  1
    dict set libraries altera_merlin_master_agent_1940     1
    dict set libraries altera_merlin_slave_agent_1930      1
    dict set libraries altera_avalon_sc_fifo_1932          1
    dict set libraries altera_merlin_router_1921           1
    dict set libraries altera_merlin_traffic_limiter_1922  1
    dict set libraries altera_merlin_demultiplexer_1921    1
    dict set libraries altera_merlin_multiplexer_1922      1
    dict set libraries altera_mm_interconnect_1920         1
    dict set libraries altera_reset_controller_1924        1
    dict set libraries peripheral_subsys                   1
    return $libraries
  }
  
  proc get_memory_files {QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
    set memory_files [list]
    set memory_files [concat $memory_files [button_pio::get_memory_files "$QSYS_SIMDIR/../../ip/peripheral_subsys/button_pio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [led_pio::get_memory_files "$QSYS_SIMDIR/../../ip/peripheral_subsys/led_pio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [dipsw_pio::get_memory_files "$QSYS_SIMDIR/../../ip/peripheral_subsys/dipsw_pio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [sysid::get_memory_files "$QSYS_SIMDIR/../../ip/peripheral_subsys/sysid/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [periph_clk::get_memory_files "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_clk/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [periph_rst_in::get_memory_files "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
    set memory_files [concat $memory_files [pb_cpu_0::get_memory_files "$QSYS_SIMDIR/../../ip/peripheral_subsys/pb_cpu_0/sim/" "$QUARTUS_INSTALL_DIR"]]
    return $memory_files
  }
  
  proc get_common_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR} {
    set design_files [dict create]
    set design_files [dict merge $design_files [button_pio::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/button_pio/sim/"]]
    set design_files [dict merge $design_files [led_pio::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/led_pio/sim/"]]
    set design_files [dict merge $design_files [dipsw_pio::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/dipsw_pio/sim/"]]
    set design_files [dict merge $design_files [sysid::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/sysid/sim/"]]
    set design_files [dict merge $design_files [periph_clk::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_clk/sim/"]]
    set design_files [dict merge $design_files [periph_rst_in::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_rst_in/sim/"]]
    set design_files [dict merge $design_files [pb_cpu_0::get_common_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/pb_cpu_0/sim/"]]
    return $design_files
  }
  
  proc get_design_files {USER_DEFINED_COMPILE_OPTIONS USER_DEFINED_VERILOG_COMPILE_OPTIONS USER_DEFINED_VHDL_COMPILE_OPTIONS QSYS_SIMDIR QUARTUS_INSTALL_DIR} {
    set design_files [list]
    set design_files [concat $design_files [button_pio::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/button_pio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [led_pio::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/led_pio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [dipsw_pio::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/dipsw_pio/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [sysid::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/sysid/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [periph_clk::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_clk/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [periph_rst_in::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_rst_in/sim/" "$QUARTUS_INSTALL_DIR"]]
    set design_files [concat $design_files [pb_cpu_0::get_design_files $USER_DEFINED_COMPILE_OPTIONS $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_VHDL_COMPILE_OPTIONS "$QSYS_SIMDIR/../../ip/peripheral_subsys/pb_cpu_0/sim/" "$QUARTUS_INSTALL_DIR"]]
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_master_translator_193/sim/peripheral_subsys_altera_merlin_master_translator_193_lgcew2q.sv"]\"  -work altera_merlin_master_translator_193"                       
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_translator_191/sim/peripheral_subsys_altera_merlin_slave_translator_191_xg7rzxi.sv"]\"  -work altera_merlin_slave_translator_191"                          
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_master_agent_1940/sim/peripheral_subsys_altera_merlin_master_agent_1940_r3ep6da.sv"]\"  -work altera_merlin_master_agent_1940"                                   
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/peripheral_subsys_altera_merlin_slave_agent_1930_jxauz3i.sv"]\"  -work altera_merlin_slave_agent_1930"                                      
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_slave_agent_1930/sim/altera_merlin_burst_uncompressor.sv"]\"  -work altera_merlin_slave_agent_1930"                                                              
    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_avalon_sc_fifo_1932/sim/peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v"]\"  -work altera_avalon_sc_fifo_1932"                                              
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/peripheral_subsys_altera_merlin_router_1921_iesulwy.sv"]\"  -work altera_merlin_router_1921"                                                     
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_router_1921/sim/peripheral_subsys_altera_merlin_router_1921_wxl7gvy.sv"]\"  -work altera_merlin_router_1921"                                                     
    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_traffic_limiter_1922/sim/peripheral_subsys_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1922_25262sa.v"]\"  -work altera_merlin_traffic_limiter_1922"
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_traffic_limiter_1922/sim/altera_merlin_reorder_memory.sv"]\"  -work altera_merlin_traffic_limiter_1922"                                                          
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_traffic_limiter_1922/sim/altera_avalon_st_pipeline_base.v"]\"  -work altera_merlin_traffic_limiter_1922"                                                         
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_traffic_limiter_1922/sim/peripheral_subsys_altera_merlin_traffic_limiter_1922_y23fybq.sv"]\"  -work altera_merlin_traffic_limiter_1922"                          
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv"]\"  -work altera_merlin_demultiplexer_1921"                                
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/peripheral_subsys_altera_merlin_multiplexer_1922_ufdjdoq.sv"]\"  -work altera_merlin_multiplexer_1922"                                      
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_1922"                                                                      
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_demultiplexer_1921/sim/peripheral_subsys_altera_merlin_demultiplexer_1921_4xqokvi.sv"]\"  -work altera_merlin_demultiplexer_1921"                                
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq.sv"]\"  -work altera_merlin_multiplexer_1922"                                      
    lappend design_files "vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_merlin_multiplexer_1922/sim/altera_merlin_arbitrator.sv"]\"  -work altera_merlin_multiplexer_1922"                                                                      
    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_mm_interconnect_1920/sim/peripheral_subsys_altera_mm_interconnect_1920_553jo7i.v"]\"  -work altera_mm_interconnect_1920"                                           
    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_controller.v"]\"  -work altera_reset_controller_1924"                                                                       
    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/../altera_reset_controller_1924/sim/altera_reset_synchronizer.v"]\"  -work altera_reset_controller_1924"                                                                     
    lappend design_files "vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS  \"[normalize_path "$QSYS_SIMDIR/peripheral_subsys.v"]\"  -work peripheral_subsys"                                                                                                                            
    return $design_files
  }
  
  proc get_non_duplicate_elab_option {ELAB_OPTIONS NEW_ELAB_OPTION} {
    set IS_DUPLICATE [string first $NEW_ELAB_OPTION $ELAB_OPTIONS]
    if {$IS_DUPLICATE == -1} {
      return $NEW_ELAB_OPTION
    } else {
      return ""
    }
  }
  
  
  proc get_elab_options {SIMULATOR_TOOL_BITNESS} {
    set ELAB_OPTIONS ""
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [button_pio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [led_pio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [dipsw_pio::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [sysid::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [periph_clk::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [periph_rst_in::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    append ELAB_OPTIONS [get_non_duplicate_elab_option $ELAB_OPTIONS [pb_cpu_0::get_elab_options $SIMULATOR_TOOL_BITNESS]]
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ELAB_OPTIONS
  }
  
  
  proc get_sim_options {SIMULATOR_TOOL_BITNESS} {
    set SIM_OPTIONS ""
    append SIM_OPTIONS [button_pio::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [led_pio::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [dipsw_pio::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [sysid::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [periph_clk::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [periph_rst_in::get_sim_options $SIMULATOR_TOOL_BITNESS]
    append SIM_OPTIONS [pb_cpu_0::get_sim_options $SIMULATOR_TOOL_BITNESS]
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $SIM_OPTIONS
  }
  
  
  proc get_env_variables {SIMULATOR_TOOL_BITNESS} {
    set ENV_VARIABLES [dict create]
    set LD_LIBRARY_PATH [dict create]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [button_pio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [led_pio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [dipsw_pio::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [sysid::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [periph_clk::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [periph_rst_in::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    set LD_LIBRARY_PATH [dict merge $LD_LIBRARY_PATH [dict get [pb_cpu_0::get_env_variables $SIMULATOR_TOOL_BITNESS] "LD_LIBRARY_PATH"]]
    dict set ENV_VARIABLES "LD_LIBRARY_PATH" $LD_LIBRARY_PATH
    if ![ string match "bit_64" $SIMULATOR_TOOL_BITNESS ] {
    } else {
    }
    return $ENV_VARIABLES
  }
  
  
  proc normalize_path {FILEPATH} {
      if {[catch { package require fileutil } err]} { 
          return $FILEPATH 
      } 
      set path [fileutil::lexnormalize [file join [pwd] $FILEPATH]]  
      if {[file pathtype $FILEPATH] eq "relative"} { 
          set path [fileutil::relative [pwd] $path] 
      } 
      return $path 
  } 
  proc get_dpi_libraries {QSYS_SIMDIR} {
    set libraries [dict create]
    set libraries [dict merge $libraries [button_pio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/peripheral_subsys/button_pio/sim/"]]
    set libraries [dict merge $libraries [led_pio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/peripheral_subsys/led_pio/sim/"]]
    set libraries [dict merge $libraries [dipsw_pio::get_dpi_libraries "$QSYS_SIMDIR/../../ip/peripheral_subsys/dipsw_pio/sim/"]]
    set libraries [dict merge $libraries [sysid::get_dpi_libraries "$QSYS_SIMDIR/../../ip/peripheral_subsys/sysid/sim/"]]
    set libraries [dict merge $libraries [periph_clk::get_dpi_libraries "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_clk/sim/"]]
    set libraries [dict merge $libraries [periph_rst_in::get_dpi_libraries "$QSYS_SIMDIR/../../ip/peripheral_subsys/periph_rst_in/sim/"]]
    set libraries [dict merge $libraries [pb_cpu_0::get_dpi_libraries "$QSYS_SIMDIR/../../ip/peripheral_subsys/pb_cpu_0/sim/"]]
    
    return $libraries
  }
  
}
