// retroDE_ps2 — tb_top_psmct32_tile_bin4x4_demo (Ch312)
//
// Scale the tiled renderer to a 4x4 grid (16 tiles, 16x16 each = 64x64), reusing
// the Ch311 bin-buffer mechanism. Three prims stress the larger grid:
//   P0 blue (Z5000): top-left, bbox tiles t0,1,4,5         (4 tiles)
//   P1 red  (Z6000): mid, crosses x=16/32/48 & y=16/32 seams, bbox t5,6,7,9,10,11 (6)
//   P2 white(Z5800): bottom-right corner tile t15 ONLY     (1 tile)
//   EMPTY tiles t2,3,8,12,13,14 -> no prim -> stay clear.
// Prim idx P0=0,P1=1,P2=2. Tile t=row*4+col; bounds (col*16,row*16)+15.
//
// PROOFS:
//   BIN COUNTS  : bin_n[t] for ALL 16 tiles == # prims whose bbox overlaps tile t
//                 (so each prim is in every overlapping bin, none else; empty=0).
//   BIN ORDER   : the one multi-prim tile (t5) lists {P0,P1} in draw order.
//   EMPTY CLEAR : empty-tile pixels are clear green.
//   IMAGE       : whole 64x64 matches the screen-space re-test reference (depth+blend),
//                 with seam continuity across multiple x (16/32/48) & y (16/32) seams.
//   GRID        : 16 tiles cleared (256 each) + 16*256 flush; prim list = 3.

`timescale 1ns/1ps

module tb_top_psmct32_tile_bin4x4_demo;

    localparam int H_ACTIVE = 64, V_ACTIVE = 64;
    localparam int TP_CLEAR = 1;
    localparam real MARG = 0.10;
    localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go;
    logic [7:0]  r, g, b;
    logic        hsync, vsync, de;
    logic        core_halt, dma_done_seen, frame_seen, raster_overflow;
    logic        frame_toggle, dma_done_toggle;

    top_psmct32_raster_demo_bram #(
        .H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
        .VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
        .COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
        .TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .BIN_BUFFER_ENABLE(1'b1)
    ) dut (
        .clk(clk), .rst_n(rst_n), .core_go(core_go),
        .r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
        .core_halt(core_halt), .dma_done_seen(dma_done_seen),
        .frame_seen(frame_seen), .raster_overflow(raster_overflow),
        .frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
        .joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
    );

    function automatic int tri_cls(input real px, input real py,
                                   input real ax, input real ay,
                                   input real bx, input real by,
                                   input real cx, input real cy);
        real d, wa, wb, wc;
        begin
            d  = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
            wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
            wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
            wc = 1.0 - wa - wb;
            if (wa>MARG && wb>MARG && wc>MARG)            tri_cls = 1;
            else if (wa<-MARG || wb<-MARG || wc<-MARG)    tri_cls = 0;
            else                                          tri_cls = 2;
        end
    endfunction
    function automatic logic [7:0] sovr(input int cs, input int cd, input int aa);
        int t; begin t=((cs-cd)*aa)>>>7; t=t+cd; if(t<0)t=0; if(t>255)t=255; sovr=t[7:0]; end
    endfunction
    // expected: prim p's bbox overlaps tile t? (bboxes match bake.py Ch312 verts)
    function automatic bit binx(input int p, input int t);
        int xl,xh,yl,yh,tx0,tx1,ty0,ty1;
        begin
            case (p)
              0: begin xl=2;  xh=30; yl=2;  yh=30; end  // P0
              1: begin xl=20; xh=50; yl=18; yh=40; end  // P1
              default: begin xl=52; xh=60; yl=52; yh=60; end // P2
            endcase
            tx0=(t%4)*16; tx1=tx0+15; ty0=(t/4)*16; ty1=ty0+15;
            binx = !((xl>tx1)||(xh<tx0)||(yl>ty1)||(yh<ty0));
        end
    endfunction

    int clear_cw [0:15];
    int flush_emits; bit saw_prim_count_3;
    initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; saw_prim_count_3=0; end
    always_ff @(posedge clk) if (rst_n) begin
        if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
            int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
            if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
        end
        if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
        if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
    end

    logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
    logic       cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
    bit capture_armed;
    initial begin
        for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
        capture_armed=1'b0;
    end
    logic [31:0] hcnt_d, vcnt_d;
    always_ff @(posedge clk) begin
        if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
        else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
    end
    always_ff @(posedge clk) begin
        if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
            cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
        end
    end

    int errors, n_match, n_check, n_seam, n_empty_chk;
    int bnv [0:15];   // bin_n read-back (constant indices)
    int b5_0, b5_1;   // t5 bin slots (the only multi-prim tile)

    initial begin
        errors=0; n_match=0; n_check=0; n_seam=0; n_empty_chk=0;
        for(int t=0;t<16;t++) bnv[t]=0;
        rst_n=1'b0; core_go=1'b0;
        repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
        @(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
        wait (core_halt==1'b1); repeat(4) @(posedge clk);
        wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
        if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
        @(posedge dut.u_gs.raster_active);
        @(negedge dut.u_gs.raster_active);
        repeat(10) @(posedge clk);
        // grab all 16 bin_n + t5's two slots (constant indices; stable post-binning)
        bnv[0]=int'(dut.u_gs.bin_n[0]);   bnv[1]=int'(dut.u_gs.bin_n[1]);
        bnv[2]=int'(dut.u_gs.bin_n[2]);   bnv[3]=int'(dut.u_gs.bin_n[3]);
        bnv[4]=int'(dut.u_gs.bin_n[4]);   bnv[5]=int'(dut.u_gs.bin_n[5]);
        bnv[6]=int'(dut.u_gs.bin_n[6]);   bnv[7]=int'(dut.u_gs.bin_n[7]);
        bnv[8]=int'(dut.u_gs.bin_n[8]);   bnv[9]=int'(dut.u_gs.bin_n[9]);
        bnv[10]=int'(dut.u_gs.bin_n[10]); bnv[11]=int'(dut.u_gs.bin_n[11]);
        bnv[12]=int'(dut.u_gs.bin_n[12]); bnv[13]=int'(dut.u_gs.bin_n[13]);
        bnv[14]=int'(dut.u_gs.bin_n[14]); bnv[15]=int'(dut.u_gs.bin_n[15]);
        b5_0=int'(dut.u_gs.bin_prim[5][0]); b5_1=int'(dut.u_gs.bin_prim[5][1]);
        @(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
        @(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;

        // PROOF GRID
        for (int t=0;t<16;t++)
            if (clear_cw[t] != 256) begin $error("[b4] tile %0d cleared %0d (want 256)", t, clear_cw[t]); errors++; end
        if (flush_emits != 16*256) begin $error("[b4] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
        if (!saw_prim_count_3)     begin $error("[b4] prim_count_r never == 3"); errors++; end

        // PROOF BIN COUNTS — every tile's bin_n == # overlapping prims (incl. empty=0).
        for (int t=0;t<16;t++) begin
            int exp_n; exp_n=0;
            for (int p=0;p<3;p++) if (binx(p,t)) exp_n++;
            if (bnv[t] !== exp_n) begin $error("[b4] tile %0d bin_n=%0d, want %0d", t, bnv[t], exp_n); errors++; end
        end
        // PROOF BIN ORDER — t5 has both P0(0) and P1(1), in draw order.
        if (b5_0 !== 0 || b5_1 !== 1) begin $error("[b4] tile5 bin = {%0d,%0d}, want {0,1}", b5_0, b5_1); errors++; end
        $display("[b4] bin_n[0..15]=%0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d  t5={%0d,%0d}",
                 bnv[0],bnv[1],bnv[2],bnv[3],bnv[4],bnv[5],bnv[6],bnv[7],bnv[8],bnv[9],bnv[10],bnv[11],bnv[12],bnv[13],bnv[14],bnv[15],b5_0,b5_1);

        // PROOF IMAGE — re-test reference: P0 blue (src-over), P1 red (src-over),
        // P2 white (src-over translucent A=0x40 over green clear), depth GEQUAL.
        for (int py=0; py<V_ACTIVE; py++) begin
            for (int px=0; px<H_ACTIVE; px++) begin
                int c0,c1,c2,cr,cg,cb,zz; logic [7:0] er,eg,eb; bit scene_here, in_empty;
                c0 = tri_cls(real'(px),real'(py),  2, 2, 30, 2, 2,30);
                c1 = tri_cls(real'(px),real'(py), 20,18, 50,18, 35,40);
                c2 = tri_cls(real'(px),real'(py), 52,52, 60,52, 52,60);
                if (c0==2||c1==2||c2==2) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end
                else begin
                    scene_here = (c0==1)||(c1==1)||(c2==1);
                    cr=0;cg=128;cb=0;zz=ZCLR;
                    if (c0==1 && Z0>=zz) begin cr=sovr(0,cr,'h80);   cg=sovr(0,cg,'h80);   cb=sovr(255,cb,'h80); zz=Z0; end
                    if (c1==1 && Z1>=zz) begin cr=sovr(255,cr,'h80); cg=sovr(0,cg,'h80);   cb=sovr(0,cb,'h80);   zz=Z1; end
                    if (c2==1 && Z2>=zz) begin cr=sovr(255,cr,'h40); cg=sovr(255,cg,'h40); cb=sovr(255,cb,'h40); zz=Z2; end
                    er=cr[7:0]; eg=cg[7:0]; eb=cb[7:0];
                    // empty-tile sanity: a clearly-out-of-all pixel in an empty tile is green
                    if (!scene_here) in_empty=1;
                end
                if (er!==8'hxx && cap_de[py][px]) begin
                    n_check++;
                    if (in_empty && er==8'h00&&eg==8'h80&&eb==8'h00) n_empty_chk++;
                    if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
                        n_match++;
                        if (px==15||px==16||px==31||px==32||px==47||px==48||py==15||py==16||py==31||py==32) n_seam++;
                    end else begin
                        if (errors<14) $error("[b4] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
                        errors++;
                    end
                end
            end
        end

        if (n_check < 400)      begin $error("[b4] too few checkable pixels (%0d)", n_check); errors++; end
        if (n_match != n_check) begin $error("[b4] image match %0d/%0d (4x4 routing error)", n_match, n_check); errors++; end
        if (n_empty_chk < 100)  begin $error("[b4] too few empty-tile-clear pixels (%0d)", n_empty_chk); errors++; end
        if (n_seam < 40)        begin $error("[b4] too few SEAM matches (%0d) — 4x4 seams not exercised", n_seam); errors++; end
        if (!core_halt)         begin $error("core_halt low"); errors++; end
        if (raster_overflow)    begin $error("raster_overflow"); errors++; end

        $display("[tb_top_psmct32_tile_bin4x4_demo] tiles_cleared(all256)=%0b flush=%0d prim3=%0b match=%0d/%0d seam=%0d empty=%0d errors=%0d",
                 (flush_emits==16*256), flush_emits, saw_prim_count_3, n_match, n_check, n_seam, n_empty_chk, errors);
        if (errors==0) $display("[tb_top_psmct32_tile_bin4x4_demo] PASS");
        else           $display("[tb_top_psmct32_tile_bin4x4_demo] FAIL");
        $finish;
    end

    initial begin #600000000; $error("[tb_top_psmct32_tile_bin4x4_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_bin4x4_demo
