// retroDE_ps2 — tb_ee_core_lq
//
// Ch279 — Focused TB for R5900 EE LQ (Load Quadword), opcode
// 0x1E. The 128-bit load symmetric to Ch271's SQ. qbert.elf
// hits `lq $t1, 0($a1)` (instr 0x78A90000) at PC 0x00112C88.
//
// Our regfile is 32-bit so we only read/store the low 32 bits;
// the architectural upper 96 bits of $rt are discarded
// (documented approximation, same as SQ).
//
// Test sequence:
//   1. Set $v0 (base) = 0x80000400 (kseg0 → EE-RAM phys 0x400).
//   2. Pre-poke phys 0x400..0x40F with distinct 32-bit words.
//   3. Execute `lq $t1, 0($v0)` (encoded with rs=$v0, rt=$t1,
//      imm=0).
//   4. Verify $t1 == word0 (the low 32 bits of the 16-byte aligned
//      EA). Other lanes are intentionally distinct so a buggy
//      4-beat read that swapped lanes would FAIL.
//   5. Also verify the qbert-style `lq $t1, 0($a1)` encoding
//      assertion against 0x78A90000.
//   6. Cross-check: an LW at the same EA returns the same value
//      (proves LQ is decoded as a "single-beat low-word load"
//      consistent with the existing LW path).
//   7. PASS via syscall. Memory is NOT modified — verified by
//      direct hierarchical peek after halt.
//
// Strict mode ON. Pre-Ch279 this would trap on op=0x1E.

`timescale 1ns/1ps

module tb_ee_core_lq;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 64 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    localparam logic [31:0] TARGET_KSEG0   = 32'h8000_0400;
    localparam int          TARGET_PHYS    = 32'h400;
    localparam logic [31:0] PATTERN_WORD0  = 32'hAABB_CCDD;
    localparam logic [31:0] PATTERN_WORD1  = 32'h1111_2222;
    localparam logic [31:0] PATTERN_WORD2  = 32'h3333_4444;
    localparam logic [31:0] PATTERN_WORD3  = 32'h5555_6666;

    // Slot layout
    localparam int B_LUI_V0    = BOOTSTRAP_SLOT + 0;   // lui $v0, 0x8000
    localparam int B_ORI_V0    = BOOTSTRAP_SLOT + 1;   // ori $v0, $v0, 0x0400
    localparam int B_LQ        = BOOTSTRAP_SLOT + 2;   // lq  $t1, 0($v0)
    localparam int B_LUI_TMP_H = BOOTSTRAP_SLOT + 3;   // lui $tmp, 0xAABB
    localparam int B_ORI_TMP_L = BOOTSTRAP_SLOT + 4;   // ori $tmp, $tmp, 0xCCDD
    localparam int B_BNE_VALUE = BOOTSTRAP_SLOT + 5;   // bne $t1, $tmp, FAIL
    localparam int B_DS_VALUE  = BOOTSTRAP_SLOT + 6;
    // Cross-check via LW at the same EA.
    localparam int B_LW        = BOOTSTRAP_SLOT + 7;   // lw  $t2, 0($v0)
    localparam int B_BNE_CROSS = BOOTSTRAP_SLOT + 8;   // bne $t2, $t1, FAIL
    localparam int B_DS_CROSS  = BOOTSTRAP_SLOT + 9;
    localparam int B_PASS      = BOOTSTRAP_SLOT + 10;
    localparam int B_FAIL      = BOOTSTRAP_SLOT + 11;

    localparam logic [5:0] OP_J     = 6'h02;
    localparam logic [5:0] OP_BNE   = 6'h05;
    localparam logic [5:0] OP_ORI   = 6'h0D;
    localparam logic [5:0] OP_LUI   = 6'h0F;
    localparam logic [5:0] OP_LW    = 6'h23;
    localparam logic [5:0] OP_LQ    = 6'h1E;

    localparam int RV0 = 2;
    localparam int RA1 = 5;     // unused but useful for the qbert-shape encoding assertion
    localparam int RT1 = 9;
    localparam int RT2 = 10;
    localparam int RTMP = 24;

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    // ----- EE core -----
    logic        core_go, core_halt, core_trap;
    logic [31:0] core_pc, core_trap_pc, core_trap_instr;
    logic        ee_rd_en, ee_rd_valid, ee_wr_en;
    logic [31:0] ee_rd_addr, ee_rd_data, ee_wr_addr, ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(.STRICT_UNSUPPORTED(1'b1)) u_core (
        .clk(clk), .rst_n(rst_n), .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(1'b0),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    // ----- Map + RAM + BIOS -----
    logic         bios_rd_en, bios_rd_valid;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         ee_ram_rd_en, ee_ram_rd_valid, ee_ram_wr_en;
    logic [24:0]  ee_ram_rd_addr, ee_ram_wr_addr;
    logic [127:0] ee_ram_rd_data, ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_lq_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events, core_halt_events, core_trap_events, errors;
    initial begin
        core_retired_events = 0; core_halt_events = 0;
        core_trap_events = 0; errors = 0;
    end
    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0) core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0) core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask
    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction
    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction
    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    task automatic ram_word(input logic [31:0] phys_addr, input logic [31:0] word);
        int           qw_idx;
        logic [1:0]   lane;
        logic [127:0] cur;
        qw_idx = phys_addr >> 4;
        lane   = phys_addr[3:2];
        cur    = u_ee_ram.mem[qw_idx];
        case (lane)
            2'd0: cur[ 31:  0] = word;
            2'd1: cur[ 63: 32] = word;
            2'd2: cur[ 95: 64] = word;
            2'd3: cur[127: 96] = word;
        endcase
        u_ee_ram.mem[qw_idx] = cur;
    endtask

    initial begin
        logic [31:0] qbert_lq_raw;

        rst_n = 1'b0; core_go = 1'b0;
        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_word(RESET_SLOT,     enc_j(BOOTSTRAP_VA));
        bios_word(RESET_SLOT + 1, 32'd0);

        // Base = 0x80000400
        bios_word(B_LUI_V0, enc_i(OP_LUI, 0, RV0, 16'h8000));
        bios_word(B_ORI_V0, enc_i(OP_ORI, RV0, RV0, 16'h0400));

        // LQ $t1, 0($v0)
        bios_word(B_LQ, enc_i(OP_LQ, RV0, RT1, 16'h0000));

        // Encoder-output assertion: qbert's instruction has the same
        // shape with rs=$a1, rt=$t1, imm=0. Build that and assert
        // matches 0x78A90000.
        qbert_lq_raw = enc_i(OP_LQ, RA1, RT1, 16'h0000);
        if (qbert_lq_raw !== 32'h78A9_0000) begin
            $error("[tb_ee_core_lq] enc_i mismatch: produced 0x%08h, expected 0x78A90000",
                   qbert_lq_raw);
            errors = errors + 1;
        end

        // Verify $t1 == 0xAABBCCDD (the low 32 of the qword).
        bios_word(B_LUI_TMP_H, enc_i(OP_LUI, 0, RTMP, 16'hAABB));
        bios_word(B_ORI_TMP_L, enc_i(OP_ORI, RTMP, RTMP, 16'hCCDD));
        bios_word(B_BNE_VALUE, enc_i(OP_BNE, RT1, RTMP, branch_imm(B_BNE_VALUE, B_FAIL)));
        bios_word(B_DS_VALUE,  32'd0);

        // Cross-check: LW at same EA returns same value.
        bios_word(B_LW,        enc_i(OP_LW, RV0, RT2, 16'h0000));
        bios_word(B_BNE_CROSS, enc_i(OP_BNE, RT2, RT1, branch_imm(B_BNE_CROSS, B_FAIL)));
        bios_word(B_DS_CROSS,  32'd0);

        bios_word(B_PASS, 32'h0000_000C);
        bios_word(B_FAIL, 32'h0000_000C);

        // Pre-poke distinct patterns across all 4 lanes of the qword.
        ram_word(TARGET_PHYS + 32'd0,  PATTERN_WORD0);   // <-- LQ low lane
        ram_word(TARGET_PHYS + 32'd4,  PATTERN_WORD1);
        ram_word(TARGET_PHYS + 32'd8,  PATTERN_WORD2);
        ram_word(TARGET_PHYS + 32'd12, PATTERN_WORD3);

        @(negedge clk); core_go = 1'b1;
        @(negedge clk); core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        // ---- Checks ----
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_lq] unexpected trap (LQ unsupported?): %0d pc=0x%08h instr=0x%08h",
                   core_trap_events, core_trap_pc, core_trap_instr);
            errors = errors + 1;
        end
        if (core_halt_events != 1) begin
            $error("[tb_ee_core_lq] expected 1 halt, got %0d", core_halt_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_lq] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc, BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        // Register peek: $t1 == PATTERN_WORD0; $t2 (LW cross-check) == same.
        if (u_core.regfile[RT1] !== PATTERN_WORD0) begin
            $error("[tb_ee_core_lq] $t1 = 0x%08h (expected 0x%08h)",
                   u_core.regfile[RT1], PATTERN_WORD0);
            errors = errors + 1;
        end
        if (u_core.regfile[RT2] !== PATTERN_WORD0) begin
            $error("[tb_ee_core_lq] $t2 (LW cross-check) = 0x%08h (expected 0x%08h)",
                   u_core.regfile[RT2], PATTERN_WORD0);
            errors = errors + 1;
        end

        // RAM must NOT have changed (LQ is a load, no write).
        begin
            int           qw_idx;
            logic [127:0] cur;
            logic [31:0]  w0, w1, w2, w3;
            qw_idx = TARGET_PHYS >> 4;
            cur    = u_ee_ram.mem[qw_idx];
            w0 = cur[31:0]; w1 = cur[63:32]; w2 = cur[95:64]; w3 = cur[127:96];
            if (w0 !== PATTERN_WORD0 || w1 !== PATTERN_WORD1
             || w2 !== PATTERN_WORD2 || w3 !== PATTERN_WORD3) begin
                $error("[tb_ee_core_lq] RAM was modified by LQ: w0=0x%08h w1=0x%08h w2=0x%08h w3=0x%08h",
                       w0, w1, w2, w3);
                errors = errors + 1;
            end
        end

        $display("[tb_ee_core_lq] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);
        $display("[tb_ee_core_lq]   $t1=0x%08h  $t2=0x%08h",
                 u_core.regfile[RT1], u_core.regfile[RT2]);

        if (errors == 0)
            $display("[tb_ee_core_lq] PASS");
        else
            $display("[tb_ee_core_lq] FAIL");
        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_lq] timeout");
        $finish;
    end

endmodule : tb_ee_core_lq
