<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2026.05.11.21:03:51"
 outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Agilex 5"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="A5ED065BB32AE6SR0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="6"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_BOARD"
     type="String"
     defaultValue="default"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S1_CPU_INFO_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <interface name="clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="reset" kind="reset" start="0">
   <property name="associatedClock" value="clk" />
   <property name="synchronousEdges" value="DEASSERT" />
   <port name="reset_n" direction="input" role="reset_n" width="1" />
  </interface>
  <interface name="s1" kind="avalon" start="0">
   <property name="addressAlignment" value="NATIVE" />
   <property name="addressGroup" value="0" />
   <property name="addressSpan" value="4" />
   <property name="addressUnits" value="WORDS" />
   <property name="alwaysBurstMaxBurst" value="false" />
   <property name="associatedClock" value="clk" />
   <property name="associatedReset" value="reset" />
   <property name="bitsPerSymbol" value="8" />
   <property name="bridgedAddressOffset" value="0" />
   <property name="bridgesToMaster" value="" />
   <property name="burstOnBurstBoundariesOnly" value="false" />
   <property name="burstcountUnits" value="WORDS" />
   <property name="constantBurstBehavior" value="false" />
   <property name="explicitAddressSpan" value="0" />
   <property name="holdTime" value="0" />
   <property name="interleaveBursts" value="false" />
   <property name="isBigEndian" value="false" />
   <property name="isFlash" value="false" />
   <property name="isMemoryDevice" value="false" />
   <property name="isNonVolatileStorage" value="false" />
   <property name="linewrapBursts" value="false" />
   <property name="maximumPendingReadTransactions" value="0" />
   <property name="maximumPendingWriteTransactions" value="0" />
   <property name="minimumReadLatency" value="1" />
   <property name="minimumResponseLatency" value="1" />
   <property name="minimumUninterruptedRunLength" value="1" />
   <property name="prSafe" value="false" />
   <property name="printableDevice" value="false" />
   <property name="readLatency" value="0" />
   <property name="readWaitStates" value="1" />
   <property name="readWaitTime" value="1" />
   <property name="registerIncomingSignals" value="false" />
   <property name="registerOutgoingSignals" value="false" />
   <property name="setupTime" value="0" />
   <property name="timingUnits" value="Cycles" />
   <property name="transparentBridge" value="false" />
   <property name="waitrequestAllowance" value="0" />
   <property name="waitrequestTimeout" value="1024" />
   <property name="wellBehavedWaitrequest" value="false" />
   <property name="writeLatency" value="0" />
   <property name="writeWaitStates" value="0" />
   <property name="writeWaitTime" value="0" />
   <property name="dfhFeatureGuid" value="0" />
   <property name="dfhGroupId" value="0" />
   <property name="dfhParameterId" value="" />
   <property name="dfhParameterName" value="" />
   <property name="dfhParameterVersion" value="" />
   <property name="dfhParameterData" value="" />
   <property name="dfhParameterDataLength" value="" />
   <property name="dfhFeatureMajorVersion" value="0" />
   <property name="dfhFeatureMinorVersion" value="0" />
   <property name="dfhFeatureId" value="35" />
   <property name="dfhFeatureType" value="3" />
   <port name="address" direction="input" role="address" width="2" />
   <port name="write_n" direction="input" role="write_n" width="1" />
   <port name="writedata" direction="input" role="writedata" width="32" />
   <port name="chipselect" direction="input" role="chipselect" width="1" />
   <port name="readdata" direction="output" role="readdata" width="32" />
  </interface>
  <interface name="external_connection" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="in_port" direction="input" role="in_port" width="3" />
   <port name="out_port" direction="output" role="out_port" width="3" />
  </interface>
 </perimeter>
 <entity kind="led_pio" version="1.0" name="led_pio">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_S1_CPU_INFO_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/synth/led_pio.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/synth/led_pio.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio.ip" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Info" culprit="led_pio">"Generating: led_pio"</message>
   <message level="Info" culprit="led_pio">"Generating: led_pio_altera_avalon_pio_1924_yrkgeby"</message>
   <message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
   <message level="Info" culprit="altera_avalon_pio_inst">  Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=led_pio_altera_avalon_pio_1924_yrkgeby --dir=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen//led_pio_altera_avalon_pio_1924_yrkgeby_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_pio"
   version="19.2.4"
   name="led_pio_altera_avalon_pio_1924_yrkgeby">
  <parameter name="DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="derived_do_test_bench_wiring" value="false" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="derived_has_irq" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="100000000" />
  <parameter name="derived_has_out" value="true" />
  <parameter name="derived_has_in" value="true" />
  <parameter name="resetValue" value="7" />
  <parameter name="derived_has_tri" value="false" />
  <parameter name="derived_capture" value="false" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="derived_edge_type" value="NONE" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="derived_irq_type" value="NONE" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="width" value="3" />
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="direction" value="InOut" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/altera_avalon_pio_1924/synth/led_pio_altera_avalon_pio_1924_yrkgeby.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/ip/peripheral_subsys/led_pio/altera_avalon_pio_1924/synth/led_pio_altera_avalon_pio_1924_yrkgeby.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/eip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="led_pio" as="altera_avalon_pio_inst" />
  <messages>
   <message level="Info" culprit="led_pio">"Generating: led_pio_altera_avalon_pio_1924_yrkgeby"</message>
   <message level="Info" culprit="altera_avalon_pio_inst">Starting RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
   <message level="Info" culprit="altera_avalon_pio_inst">  Generation command is [exec /opt/altera_pro/26.1/quartus/linux64//perl/bin/perl -I /opt/altera_pro/26.1/quartus/linux64//perl/lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/europa -I /opt/altera_pro/26.1/quartus/sopc_builder/bin/perl_lib -I /opt/altera_pro/26.1/quartus/sopc_builder/bin -I /opt/altera_pro/26.1/quartus/../ip/altera/sopc_builder_ip/common -I /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio -- /opt/altera_pro/26.1/quartus/../ip/altera/eip/altera_avalon_pio/generate_rtl.pl --name=led_pio_altera_avalon_pio_1924_yrkgeby --dir=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen/ --quartus_dir=/opt/altera_pro/26.1/quartus --verilog --config=/tmp/alt0585_45303246639317964.dir/0003_altera_avalon_pio_inst_gen//led_pio_altera_avalon_pio_1924_yrkgeby_component_configuration.pl  --do_build_sim=0  ]</message>
   <message level="Info" culprit="altera_avalon_pio_inst">Done RTL generation for module 'led_pio_altera_avalon_pio_1924_yrkgeby'</message>
  </messages>
 </entity>
</deploy>
