// retroDE_ps2 — tb_ee_core_dsll
//
// Ch276 — Focused TB for R5900 DSLL (Doubleword Shift Left Logical),
// MIPS-III SPECIAL funct 0x38. qbert.elf hits `dsll $t1, $t1, 16` at
// PC 0x00112C54 (instr 0x00094C38). Modelled as SLL semantics on the
// low 32 bits — for any valid sa < 32 the low 32 bits are identical
// to a plain SLL, and our regfile is 32-bit so upper bits aren't
// observable.
//
// Test cases:
//   1. Exact qbert encoding: `dsll $t1, $t1, 16` (rt=rd=9, sa=16).
//      With $t1 = 0x00001234 → $t1 = 0x12340000. Encoded shape
//      asserted against 0x00094C38.
//   2. Low-bit case: `dsll $t2, $t3, 1` with $t3 = 0x40000001 →
//      $t2 = 0x80000002.
//   3. Wrap-out case: `dsll $t4, $t5, 1` with $t5 = 0x80000001 →
//      $t4 = 0x00000002 (low 32 truncation; bit-31 falls off).
//   4. sa = 0 no-shift case: `dsll $t6, $t7, 0` with $t7 = 0xABCD1234
//      → $t6 = 0xABCD1234 (identity).
//
// Strict mode ON. Pre-Ch276 this would trap at is_unsupported.

`timescale 1ns/1ps

module tb_ee_core_dsll;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    // Slot layout
    localparam int B_ORI_T1_1234 = BOOTSTRAP_SLOT + 0;   // ori $t1,$0,0x1234
    localparam int B_DSLL_T1     = BOOTSTRAP_SLOT + 1;   // dsll $t1,$t1,16 (qbert exact)
    localparam int B_LUI_TMP_A   = BOOTSTRAP_SLOT + 2;   // lui $tmp,0x1234 -> 0x12340000
    localparam int B_BNE_QB      = BOOTSTRAP_SLOT + 3;   // bne $t1,$tmp,FAIL
    localparam int B_DS_QB       = BOOTSTRAP_SLOT + 4;

    // Case 2: low-bit shift
    localparam int B_LUI_T3      = BOOTSTRAP_SLOT + 5;   // lui $t3,0x4000
    localparam int B_ORI_T3      = BOOTSTRAP_SLOT + 6;   // ori $t3,$t3,0x0001 -> 0x40000001
    localparam int B_DSLL_T2     = BOOTSTRAP_SLOT + 7;   // dsll $t2,$t3,1 -> 0x80000002
    localparam int B_LUI_TMP_B1  = BOOTSTRAP_SLOT + 8;   // lui $tmp,0x8000
    localparam int B_ORI_TMP_B   = BOOTSTRAP_SLOT + 9;   // ori $tmp,$tmp,0x0002 -> 0x80000002
    localparam int B_BNE_LOW     = BOOTSTRAP_SLOT + 10;  // bne $t2,$tmp,FAIL
    localparam int B_DS_LOW      = BOOTSTRAP_SLOT + 11;

    // Case 3: wrap-out (bit-31 falls off in low-32-bit model)
    localparam int B_LUI_T5      = BOOTSTRAP_SLOT + 12;  // lui $t5,0x8000
    localparam int B_ORI_T5      = BOOTSTRAP_SLOT + 13;  // ori $t5,$t5,0x0001 -> 0x80000001
    localparam int B_DSLL_T4     = BOOTSTRAP_SLOT + 14;  // dsll $t4,$t5,1 -> 0x00000002 (low 32)
    localparam int B_ORI_TMP_C   = BOOTSTRAP_SLOT + 15;  // ori $tmp,$0,0x0002
    localparam int B_BNE_WRAP    = BOOTSTRAP_SLOT + 16;  // bne $t4,$tmp,FAIL
    localparam int B_DS_WRAP     = BOOTSTRAP_SLOT + 17;

    // Case 4: sa=0 identity
    localparam int B_LUI_T7      = BOOTSTRAP_SLOT + 18;  // lui $t7,0xABCD
    localparam int B_ORI_T7      = BOOTSTRAP_SLOT + 19;  // ori $t7,$t7,0x1234 -> 0xABCD1234
    localparam int B_DSLL_T6     = BOOTSTRAP_SLOT + 20;  // dsll $t6,$t7,0 -> 0xABCD1234
    localparam int B_LUI_TMP_D1  = BOOTSTRAP_SLOT + 21;  // lui $tmp,0xABCD
    localparam int B_ORI_TMP_D   = BOOTSTRAP_SLOT + 22;  // ori $tmp,$tmp,0x1234
    localparam int B_BNE_IDENT   = BOOTSTRAP_SLOT + 23;  // bne $t6,$tmp,FAIL
    localparam int B_DS_IDENT    = BOOTSTRAP_SLOT + 24;

    localparam int B_PASS        = BOOTSTRAP_SLOT + 25;
    localparam int B_FAIL        = BOOTSTRAP_SLOT + 26;

    localparam logic [5:0] OP_J     = 6'h02;
    localparam logic [5:0] OP_BNE   = 6'h05;
    localparam logic [5:0] OP_ORI   = 6'h0D;
    localparam logic [5:0] OP_LUI   = 6'h0F;
    localparam logic [5:0] OP_SPCL  = 6'h00;
    localparam logic [5:0] FUNC_DSLL = 6'h38;

    // GPRs
    localparam int RT1 = 9;
    localparam int RT2 = 10;
    localparam int RT3 = 11;
    localparam int RT4 = 12;
    localparam int RT5 = 13;
    localparam int RT6 = 14;
    localparam int RT7 = 15;
    localparam int RTMP = 24;  // $t8 as scratch comparand

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    // ----- EE core -----
    logic        core_go, core_halt, core_trap;
    logic [31:0] core_pc, core_trap_pc, core_trap_instr;
    logic        ee_rd_en, ee_rd_valid, ee_wr_en;
    logic [31:0] ee_rd_addr, ee_rd_data, ee_wr_addr, ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(.STRICT_UNSUPPORTED(1'b1)) u_core (
        .clk(clk), .rst_n(rst_n), .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(1'b0),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    // ----- Map + RAM + BIOS -----
    logic         bios_rd_en, bios_rd_valid;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         ee_ram_rd_en, ee_ram_rd_valid, ee_ram_wr_en;
    logic [24:0]  ee_ram_rd_addr, ee_ram_wr_addr;
    logic [127:0] ee_ram_rd_data, ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_dsll_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events, core_halt_events, core_trap_events, errors;
    initial begin
        core_retired_events = 0; core_halt_events = 0;
        core_trap_events = 0; errors = 0;
    end
    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0) core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0) core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction
    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction
    function automatic logic [31:0] enc_rtype(input logic [5:0] op,
                                              input int rs, input int rt,
                                              input int rd, input int sa,
                                              input logic [5:0] funct);
        return {op, rs[4:0], rt[4:0], rd[4:0], sa[4:0], funct};
    endfunction
    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    initial begin
        logic [31:0] qbert_dsll_raw;

        rst_n = 1'b0; core_go = 1'b0;
        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_word(RESET_SLOT,     enc_j(BOOTSTRAP_VA));
        bios_word(RESET_SLOT + 1, 32'd0);

        // Case 1: qbert encoding `dsll $t1, $t1, 16`.
        bios_word(B_ORI_T1_1234, enc_i(OP_ORI, 0, RT1, 16'h1234));
        // Build the canonical 0x00094C38 from the encoder helper and
        // assert. rs=0, rt=$t1, rd=$t1, sa=16, funct=DSLL.
        qbert_dsll_raw = enc_rtype(OP_SPCL, 0, RT1, RT1, 16, FUNC_DSLL);
        if (qbert_dsll_raw !== 32'h0009_4C38) begin
            $error("[tb_ee_core_dsll] enc_rtype mismatch: produced 0x%08h, expected 0x00094C38",
                   qbert_dsll_raw);
            errors = errors + 1;
        end
        bios_word(B_DSLL_T1,   qbert_dsll_raw);
        bios_word(B_LUI_TMP_A, enc_i(OP_LUI, 0, RTMP, 16'h1234));     // $tmp = 0x12340000
        bios_word(B_BNE_QB,    enc_i(OP_BNE, RT1, RTMP,
                                     branch_imm(B_BNE_QB, B_FAIL)));
        bios_word(B_DS_QB,     32'd0);

        // Case 2: $t3 = 0x40000001; dsll $t2, $t3, 1 -> 0x80000002
        bios_word(B_LUI_T3,    enc_i(OP_LUI, 0, RT3, 16'h4000));
        bios_word(B_ORI_T3,    enc_i(OP_ORI, RT3, RT3, 16'h0001));
        bios_word(B_DSLL_T2,   enc_rtype(OP_SPCL, 0, RT3, RT2, 1, FUNC_DSLL));
        bios_word(B_LUI_TMP_B1, enc_i(OP_LUI, 0, RTMP, 16'h8000));
        bios_word(B_ORI_TMP_B,  enc_i(OP_ORI, RTMP, RTMP, 16'h0002));
        bios_word(B_BNE_LOW,    enc_i(OP_BNE, RT2, RTMP,
                                      branch_imm(B_BNE_LOW, B_FAIL)));
        bios_word(B_DS_LOW,     32'd0);

        // Case 3: $t5 = 0x80000001; dsll $t4, $t5, 1 -> 0x00000002 (low 32 truncation)
        bios_word(B_LUI_T5,    enc_i(OP_LUI, 0, RT5, 16'h8000));
        bios_word(B_ORI_T5,    enc_i(OP_ORI, RT5, RT5, 16'h0001));
        bios_word(B_DSLL_T4,   enc_rtype(OP_SPCL, 0, RT5, RT4, 1, FUNC_DSLL));
        bios_word(B_ORI_TMP_C, enc_i(OP_ORI, 0, RTMP, 16'h0002));
        bios_word(B_BNE_WRAP,  enc_i(OP_BNE, RT4, RTMP,
                                     branch_imm(B_BNE_WRAP, B_FAIL)));
        bios_word(B_DS_WRAP,   32'd0);

        // Case 4: sa=0 identity. $t7 = 0xABCD1234; dsll $t6, $t7, 0 -> 0xABCD1234
        bios_word(B_LUI_T7,     enc_i(OP_LUI, 0, RT7, 16'hABCD));
        bios_word(B_ORI_T7,     enc_i(OP_ORI, RT7, RT7, 16'h1234));
        bios_word(B_DSLL_T6,    enc_rtype(OP_SPCL, 0, RT7, RT6, 0, FUNC_DSLL));
        bios_word(B_LUI_TMP_D1, enc_i(OP_LUI, 0, RTMP, 16'hABCD));
        bios_word(B_ORI_TMP_D,  enc_i(OP_ORI, RTMP, RTMP, 16'h1234));
        bios_word(B_BNE_IDENT,  enc_i(OP_BNE, RT6, RTMP,
                                      branch_imm(B_BNE_IDENT, B_FAIL)));
        bios_word(B_DS_IDENT,   32'd0);

        bios_word(B_PASS, 32'h0000_000C);
        bios_word(B_FAIL, 32'h0000_000C);

        @(negedge clk); core_go = 1'b1;
        @(negedge clk); core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        // ---- Checks ----
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_dsll] unexpected trap: %0d pc=0x%08h instr=0x%08h",
                   core_trap_events, core_trap_pc, core_trap_instr);
            errors = errors + 1;
        end
        if (core_halt_events != 1) begin
            $error("[tb_ee_core_dsll] expected 1 halt, got %0d", core_halt_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_dsll] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc, BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        if (u_core.regfile[RT1] !== 32'h1234_0000) begin
            $error("[tb_ee_core_dsll] CASE 1: $t1 = 0x%08h (expected 0x12340000)",
                   u_core.regfile[RT1]);
            errors = errors + 1;
        end
        if (u_core.regfile[RT2] !== 32'h8000_0002) begin
            $error("[tb_ee_core_dsll] CASE 2: $t2 = 0x%08h (expected 0x80000002)",
                   u_core.regfile[RT2]);
            errors = errors + 1;
        end
        if (u_core.regfile[RT4] !== 32'h0000_0002) begin
            $error("[tb_ee_core_dsll] CASE 3: $t4 = 0x%08h (expected 0x00000002 — low-32 wrap)",
                   u_core.regfile[RT4]);
            errors = errors + 1;
        end
        if (u_core.regfile[RT6] !== 32'hABCD_1234) begin
            $error("[tb_ee_core_dsll] CASE 4: $t6 = 0x%08h (expected 0xABCD1234 — sa=0 identity)",
                   u_core.regfile[RT6]);
            errors = errors + 1;
        end

        $display("[tb_ee_core_dsll] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);
        $display("[tb_ee_core_dsll]   $t1=0x%08h $t2=0x%08h $t4=0x%08h $t6=0x%08h",
                 u_core.regfile[RT1], u_core.regfile[RT2],
                 u_core.regfile[RT4], u_core.regfile[RT6]);

        if (errors == 0)
            $display("[tb_ee_core_dsll] PASS");
        else
            $display("[tb_ee_core_dsll] FAIL");
        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_dsll] timeout");
        $finish;
    end

endmodule : tb_ee_core_dsll
