// peripheral_subsys_altera_mm_interconnect_1920_patoohq.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.3.1 100

`timescale 1 ps / 1 ps
module peripheral_subsys_altera_mm_interconnect_1920_patoohq (
		input  wire [16:0] pb_cpu_0_m0_address,                                      //                                        pb_cpu_0_m0.address
		output wire        pb_cpu_0_m0_waitrequest,                                  //                                                   .waitrequest
		input  wire [0:0]  pb_cpu_0_m0_burstcount,                                   //                                                   .burstcount
		input  wire [3:0]  pb_cpu_0_m0_byteenable,                                   //                                                   .byteenable
		input  wire        pb_cpu_0_m0_read,                                         //                                                   .read
		output wire [31:0] pb_cpu_0_m0_readdata,                                     //                                                   .readdata
		output wire        pb_cpu_0_m0_readdatavalid,                                //                                                   .readdatavalid
		input  wire        pb_cpu_0_m0_write,                                        //                                                   .write
		input  wire [31:0] pb_cpu_0_m0_writedata,                                    //                                                   .writedata
		input  wire        pb_cpu_0_m0_debugaccess,                                  //                                                   .debugaccess
		output wire [0:0]  sysid_control_slave_address,                              //                                sysid_control_slave.address
		input  wire [31:0] sysid_control_slave_readdata,                             //                                                   .readdata
		output wire [1:0]  led_pio_s1_address,                                       //                                         led_pio_s1.address
		output wire        led_pio_s1_write,                                         //                                                   .write
		input  wire [31:0] led_pio_s1_readdata,                                      //                                                   .readdata
		output wire [31:0] led_pio_s1_writedata,                                     //                                                   .writedata
		output wire        led_pio_s1_chipselect,                                    //                                                   .chipselect
		output wire [1:0]  dipsw_pio_s1_address,                                     //                                       dipsw_pio_s1.address
		output wire        dipsw_pio_s1_write,                                       //                                                   .write
		input  wire [31:0] dipsw_pio_s1_readdata,                                    //                                                   .readdata
		output wire [31:0] dipsw_pio_s1_writedata,                                   //                                                   .writedata
		output wire        dipsw_pio_s1_chipselect,                                  //                                                   .chipselect
		output wire [1:0]  button_pio_s1_address,                                    //                                      button_pio_s1.address
		output wire        button_pio_s1_write,                                      //                                                   .write
		input  wire [31:0] button_pio_s1_readdata,                                   //                                                   .readdata
		output wire [31:0] button_pio_s1_writedata,                                  //                                                   .writedata
		output wire        button_pio_s1_chipselect,                                 //                                                   .chipselect
		input  wire        pb_cpu_0_reset_reset_bridge_in_reset_reset,               //               pb_cpu_0_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset, // pb_cpu_0_m0_translator_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        periph_clk_out_clk_clk                                    //                                 periph_clk_out_clk.clk,          Clock Input
	);

	wire          pb_cpu_0_m0_translator_avalon_universal_master_0_waitrequest;   // pb_cpu_0_m0_agent:av_waitrequest -> pb_cpu_0_m0_translator:uav_waitrequest
	wire   [31:0] pb_cpu_0_m0_translator_avalon_universal_master_0_readdata;      // pb_cpu_0_m0_agent:av_readdata -> pb_cpu_0_m0_translator:uav_readdata
	wire          pb_cpu_0_m0_translator_avalon_universal_master_0_debugaccess;   // pb_cpu_0_m0_translator:uav_debugaccess -> pb_cpu_0_m0_agent:av_debugaccess
	wire   [16:0] pb_cpu_0_m0_translator_avalon_universal_master_0_address;       // pb_cpu_0_m0_translator:uav_address -> pb_cpu_0_m0_agent:av_address
	wire          pb_cpu_0_m0_translator_avalon_universal_master_0_read;          // pb_cpu_0_m0_translator:uav_read -> pb_cpu_0_m0_agent:av_read
	wire    [3:0] pb_cpu_0_m0_translator_avalon_universal_master_0_byteenable;    // pb_cpu_0_m0_translator:uav_byteenable -> pb_cpu_0_m0_agent:av_byteenable
	wire          pb_cpu_0_m0_translator_avalon_universal_master_0_readdatavalid; // pb_cpu_0_m0_agent:av_readdatavalid -> pb_cpu_0_m0_translator:uav_readdatavalid
	wire          pb_cpu_0_m0_translator_avalon_universal_master_0_lock;          // pb_cpu_0_m0_translator:uav_lock -> pb_cpu_0_m0_agent:av_lock
	wire          pb_cpu_0_m0_translator_avalon_universal_master_0_write;         // pb_cpu_0_m0_translator:uav_write -> pb_cpu_0_m0_agent:av_write
	wire   [31:0] pb_cpu_0_m0_translator_avalon_universal_master_0_writedata;     // pb_cpu_0_m0_translator:uav_writedata -> pb_cpu_0_m0_agent:av_writedata
	wire    [2:0] pb_cpu_0_m0_translator_avalon_universal_master_0_burstcount;    // pb_cpu_0_m0_translator:uav_burstcount -> pb_cpu_0_m0_agent:av_burstcount
	wire   [31:0] sysid_control_slave_agent_m0_readdata;                          // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_agent:m0_readdata
	wire          sysid_control_slave_agent_m0_waitrequest;                       // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_agent:m0_waitrequest
	wire          sysid_control_slave_agent_m0_debugaccess;                       // sysid_control_slave_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess
	wire   [16:0] sysid_control_slave_agent_m0_address;                           // sysid_control_slave_agent:m0_address -> sysid_control_slave_translator:uav_address
	wire    [3:0] sysid_control_slave_agent_m0_byteenable;                        // sysid_control_slave_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable
	wire          sysid_control_slave_agent_m0_read;                              // sysid_control_slave_agent:m0_read -> sysid_control_slave_translator:uav_read
	wire          sysid_control_slave_agent_m0_readdatavalid;                     // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_agent:m0_readdatavalid
	wire          sysid_control_slave_agent_m0_lock;                              // sysid_control_slave_agent:m0_lock -> sysid_control_slave_translator:uav_lock
	wire   [31:0] sysid_control_slave_agent_m0_writedata;                         // sysid_control_slave_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata
	wire          sysid_control_slave_agent_m0_write;                             // sysid_control_slave_agent:m0_write -> sysid_control_slave_translator:uav_write
	wire    [2:0] sysid_control_slave_agent_m0_burstcount;                        // sysid_control_slave_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount
	wire          sysid_control_slave_agent_rf_source_valid;                      // sysid_control_slave_agent:rf_source_valid -> sysid_control_slave_agent_rsp_fifo:in_valid
	wire  [143:0] sysid_control_slave_agent_rf_source_data;                       // sysid_control_slave_agent:rf_source_data -> sysid_control_slave_agent_rsp_fifo:in_data
	wire          sysid_control_slave_agent_rf_source_ready;                      // sysid_control_slave_agent_rsp_fifo:in_ready -> sysid_control_slave_agent:rf_source_ready
	wire          sysid_control_slave_agent_rf_source_startofpacket;              // sysid_control_slave_agent:rf_source_startofpacket -> sysid_control_slave_agent_rsp_fifo:in_startofpacket
	wire          sysid_control_slave_agent_rf_source_endofpacket;                // sysid_control_slave_agent:rf_source_endofpacket -> sysid_control_slave_agent_rsp_fifo:in_endofpacket
	wire          sysid_control_slave_agent_rsp_fifo_out_valid;                   // sysid_control_slave_agent_rsp_fifo:out_valid -> sysid_control_slave_agent:rf_sink_valid
	wire  [143:0] sysid_control_slave_agent_rsp_fifo_out_data;                    // sysid_control_slave_agent_rsp_fifo:out_data -> sysid_control_slave_agent:rf_sink_data
	wire          sysid_control_slave_agent_rsp_fifo_out_ready;                   // sysid_control_slave_agent:rf_sink_ready -> sysid_control_slave_agent_rsp_fifo:out_ready
	wire          sysid_control_slave_agent_rsp_fifo_out_startofpacket;           // sysid_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_agent:rf_sink_startofpacket
	wire          sysid_control_slave_agent_rsp_fifo_out_endofpacket;             // sysid_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_agent:rf_sink_endofpacket
	wire          sysid_control_slave_agent_rdata_fifo_src_valid;                 // sysid_control_slave_agent:rdata_fifo_src_valid -> sysid_control_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] sysid_control_slave_agent_rdata_fifo_src_data;                  // sysid_control_slave_agent:rdata_fifo_src_data -> sysid_control_slave_agent:rdata_fifo_sink_data
	wire          sysid_control_slave_agent_rdata_fifo_src_ready;                 // sysid_control_slave_agent:rdata_fifo_sink_ready -> sysid_control_slave_agent:rdata_fifo_src_ready
	wire          cmd_mux_src_valid;                                              // cmd_mux:src_valid -> sysid_control_slave_agent:cp_valid
	wire  [142:0] cmd_mux_src_data;                                               // cmd_mux:src_data -> sysid_control_slave_agent:cp_data
	wire          cmd_mux_src_ready;                                              // sysid_control_slave_agent:cp_ready -> cmd_mux:src_ready
	wire    [3:0] cmd_mux_src_channel;                                            // cmd_mux:src_channel -> sysid_control_slave_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                      // cmd_mux:src_startofpacket -> sysid_control_slave_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                        // cmd_mux:src_endofpacket -> sysid_control_slave_agent:cp_endofpacket
	wire   [31:0] led_pio_s1_agent_m0_readdata;                                   // led_pio_s1_translator:uav_readdata -> led_pio_s1_agent:m0_readdata
	wire          led_pio_s1_agent_m0_waitrequest;                                // led_pio_s1_translator:uav_waitrequest -> led_pio_s1_agent:m0_waitrequest
	wire          led_pio_s1_agent_m0_debugaccess;                                // led_pio_s1_agent:m0_debugaccess -> led_pio_s1_translator:uav_debugaccess
	wire   [16:0] led_pio_s1_agent_m0_address;                                    // led_pio_s1_agent:m0_address -> led_pio_s1_translator:uav_address
	wire    [3:0] led_pio_s1_agent_m0_byteenable;                                 // led_pio_s1_agent:m0_byteenable -> led_pio_s1_translator:uav_byteenable
	wire          led_pio_s1_agent_m0_read;                                       // led_pio_s1_agent:m0_read -> led_pio_s1_translator:uav_read
	wire          led_pio_s1_agent_m0_readdatavalid;                              // led_pio_s1_translator:uav_readdatavalid -> led_pio_s1_agent:m0_readdatavalid
	wire          led_pio_s1_agent_m0_lock;                                       // led_pio_s1_agent:m0_lock -> led_pio_s1_translator:uav_lock
	wire   [31:0] led_pio_s1_agent_m0_writedata;                                  // led_pio_s1_agent:m0_writedata -> led_pio_s1_translator:uav_writedata
	wire          led_pio_s1_agent_m0_write;                                      // led_pio_s1_agent:m0_write -> led_pio_s1_translator:uav_write
	wire    [2:0] led_pio_s1_agent_m0_burstcount;                                 // led_pio_s1_agent:m0_burstcount -> led_pio_s1_translator:uav_burstcount
	wire          led_pio_s1_agent_rf_source_valid;                               // led_pio_s1_agent:rf_source_valid -> led_pio_s1_agent_rsp_fifo:in_valid
	wire  [143:0] led_pio_s1_agent_rf_source_data;                                // led_pio_s1_agent:rf_source_data -> led_pio_s1_agent_rsp_fifo:in_data
	wire          led_pio_s1_agent_rf_source_ready;                               // led_pio_s1_agent_rsp_fifo:in_ready -> led_pio_s1_agent:rf_source_ready
	wire          led_pio_s1_agent_rf_source_startofpacket;                       // led_pio_s1_agent:rf_source_startofpacket -> led_pio_s1_agent_rsp_fifo:in_startofpacket
	wire          led_pio_s1_agent_rf_source_endofpacket;                         // led_pio_s1_agent:rf_source_endofpacket -> led_pio_s1_agent_rsp_fifo:in_endofpacket
	wire          led_pio_s1_agent_rsp_fifo_out_valid;                            // led_pio_s1_agent_rsp_fifo:out_valid -> led_pio_s1_agent:rf_sink_valid
	wire  [143:0] led_pio_s1_agent_rsp_fifo_out_data;                             // led_pio_s1_agent_rsp_fifo:out_data -> led_pio_s1_agent:rf_sink_data
	wire          led_pio_s1_agent_rsp_fifo_out_ready;                            // led_pio_s1_agent:rf_sink_ready -> led_pio_s1_agent_rsp_fifo:out_ready
	wire          led_pio_s1_agent_rsp_fifo_out_startofpacket;                    // led_pio_s1_agent_rsp_fifo:out_startofpacket -> led_pio_s1_agent:rf_sink_startofpacket
	wire          led_pio_s1_agent_rsp_fifo_out_endofpacket;                      // led_pio_s1_agent_rsp_fifo:out_endofpacket -> led_pio_s1_agent:rf_sink_endofpacket
	wire          led_pio_s1_agent_rdata_fifo_src_valid;                          // led_pio_s1_agent:rdata_fifo_src_valid -> led_pio_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] led_pio_s1_agent_rdata_fifo_src_data;                           // led_pio_s1_agent:rdata_fifo_src_data -> led_pio_s1_agent:rdata_fifo_sink_data
	wire          led_pio_s1_agent_rdata_fifo_src_ready;                          // led_pio_s1_agent:rdata_fifo_sink_ready -> led_pio_s1_agent:rdata_fifo_src_ready
	wire          cmd_mux_001_src_valid;                                          // cmd_mux_001:src_valid -> led_pio_s1_agent:cp_valid
	wire  [142:0] cmd_mux_001_src_data;                                           // cmd_mux_001:src_data -> led_pio_s1_agent:cp_data
	wire          cmd_mux_001_src_ready;                                          // led_pio_s1_agent:cp_ready -> cmd_mux_001:src_ready
	wire    [3:0] cmd_mux_001_src_channel;                                        // cmd_mux_001:src_channel -> led_pio_s1_agent:cp_channel
	wire          cmd_mux_001_src_startofpacket;                                  // cmd_mux_001:src_startofpacket -> led_pio_s1_agent:cp_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                    // cmd_mux_001:src_endofpacket -> led_pio_s1_agent:cp_endofpacket
	wire   [31:0] dipsw_pio_s1_agent_m0_readdata;                                 // dipsw_pio_s1_translator:uav_readdata -> dipsw_pio_s1_agent:m0_readdata
	wire          dipsw_pio_s1_agent_m0_waitrequest;                              // dipsw_pio_s1_translator:uav_waitrequest -> dipsw_pio_s1_agent:m0_waitrequest
	wire          dipsw_pio_s1_agent_m0_debugaccess;                              // dipsw_pio_s1_agent:m0_debugaccess -> dipsw_pio_s1_translator:uav_debugaccess
	wire   [16:0] dipsw_pio_s1_agent_m0_address;                                  // dipsw_pio_s1_agent:m0_address -> dipsw_pio_s1_translator:uav_address
	wire    [3:0] dipsw_pio_s1_agent_m0_byteenable;                               // dipsw_pio_s1_agent:m0_byteenable -> dipsw_pio_s1_translator:uav_byteenable
	wire          dipsw_pio_s1_agent_m0_read;                                     // dipsw_pio_s1_agent:m0_read -> dipsw_pio_s1_translator:uav_read
	wire          dipsw_pio_s1_agent_m0_readdatavalid;                            // dipsw_pio_s1_translator:uav_readdatavalid -> dipsw_pio_s1_agent:m0_readdatavalid
	wire          dipsw_pio_s1_agent_m0_lock;                                     // dipsw_pio_s1_agent:m0_lock -> dipsw_pio_s1_translator:uav_lock
	wire   [31:0] dipsw_pio_s1_agent_m0_writedata;                                // dipsw_pio_s1_agent:m0_writedata -> dipsw_pio_s1_translator:uav_writedata
	wire          dipsw_pio_s1_agent_m0_write;                                    // dipsw_pio_s1_agent:m0_write -> dipsw_pio_s1_translator:uav_write
	wire    [2:0] dipsw_pio_s1_agent_m0_burstcount;                               // dipsw_pio_s1_agent:m0_burstcount -> dipsw_pio_s1_translator:uav_burstcount
	wire          dipsw_pio_s1_agent_rf_source_valid;                             // dipsw_pio_s1_agent:rf_source_valid -> dipsw_pio_s1_agent_rsp_fifo:in_valid
	wire  [143:0] dipsw_pio_s1_agent_rf_source_data;                              // dipsw_pio_s1_agent:rf_source_data -> dipsw_pio_s1_agent_rsp_fifo:in_data
	wire          dipsw_pio_s1_agent_rf_source_ready;                             // dipsw_pio_s1_agent_rsp_fifo:in_ready -> dipsw_pio_s1_agent:rf_source_ready
	wire          dipsw_pio_s1_agent_rf_source_startofpacket;                     // dipsw_pio_s1_agent:rf_source_startofpacket -> dipsw_pio_s1_agent_rsp_fifo:in_startofpacket
	wire          dipsw_pio_s1_agent_rf_source_endofpacket;                       // dipsw_pio_s1_agent:rf_source_endofpacket -> dipsw_pio_s1_agent_rsp_fifo:in_endofpacket
	wire          dipsw_pio_s1_agent_rsp_fifo_out_valid;                          // dipsw_pio_s1_agent_rsp_fifo:out_valid -> dipsw_pio_s1_agent:rf_sink_valid
	wire  [143:0] dipsw_pio_s1_agent_rsp_fifo_out_data;                           // dipsw_pio_s1_agent_rsp_fifo:out_data -> dipsw_pio_s1_agent:rf_sink_data
	wire          dipsw_pio_s1_agent_rsp_fifo_out_ready;                          // dipsw_pio_s1_agent:rf_sink_ready -> dipsw_pio_s1_agent_rsp_fifo:out_ready
	wire          dipsw_pio_s1_agent_rsp_fifo_out_startofpacket;                  // dipsw_pio_s1_agent_rsp_fifo:out_startofpacket -> dipsw_pio_s1_agent:rf_sink_startofpacket
	wire          dipsw_pio_s1_agent_rsp_fifo_out_endofpacket;                    // dipsw_pio_s1_agent_rsp_fifo:out_endofpacket -> dipsw_pio_s1_agent:rf_sink_endofpacket
	wire          dipsw_pio_s1_agent_rdata_fifo_src_valid;                        // dipsw_pio_s1_agent:rdata_fifo_src_valid -> dipsw_pio_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] dipsw_pio_s1_agent_rdata_fifo_src_data;                         // dipsw_pio_s1_agent:rdata_fifo_src_data -> dipsw_pio_s1_agent:rdata_fifo_sink_data
	wire          dipsw_pio_s1_agent_rdata_fifo_src_ready;                        // dipsw_pio_s1_agent:rdata_fifo_sink_ready -> dipsw_pio_s1_agent:rdata_fifo_src_ready
	wire          cmd_mux_002_src_valid;                                          // cmd_mux_002:src_valid -> dipsw_pio_s1_agent:cp_valid
	wire  [142:0] cmd_mux_002_src_data;                                           // cmd_mux_002:src_data -> dipsw_pio_s1_agent:cp_data
	wire          cmd_mux_002_src_ready;                                          // dipsw_pio_s1_agent:cp_ready -> cmd_mux_002:src_ready
	wire    [3:0] cmd_mux_002_src_channel;                                        // cmd_mux_002:src_channel -> dipsw_pio_s1_agent:cp_channel
	wire          cmd_mux_002_src_startofpacket;                                  // cmd_mux_002:src_startofpacket -> dipsw_pio_s1_agent:cp_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                    // cmd_mux_002:src_endofpacket -> dipsw_pio_s1_agent:cp_endofpacket
	wire   [31:0] button_pio_s1_agent_m0_readdata;                                // button_pio_s1_translator:uav_readdata -> button_pio_s1_agent:m0_readdata
	wire          button_pio_s1_agent_m0_waitrequest;                             // button_pio_s1_translator:uav_waitrequest -> button_pio_s1_agent:m0_waitrequest
	wire          button_pio_s1_agent_m0_debugaccess;                             // button_pio_s1_agent:m0_debugaccess -> button_pio_s1_translator:uav_debugaccess
	wire   [16:0] button_pio_s1_agent_m0_address;                                 // button_pio_s1_agent:m0_address -> button_pio_s1_translator:uav_address
	wire    [3:0] button_pio_s1_agent_m0_byteenable;                              // button_pio_s1_agent:m0_byteenable -> button_pio_s1_translator:uav_byteenable
	wire          button_pio_s1_agent_m0_read;                                    // button_pio_s1_agent:m0_read -> button_pio_s1_translator:uav_read
	wire          button_pio_s1_agent_m0_readdatavalid;                           // button_pio_s1_translator:uav_readdatavalid -> button_pio_s1_agent:m0_readdatavalid
	wire          button_pio_s1_agent_m0_lock;                                    // button_pio_s1_agent:m0_lock -> button_pio_s1_translator:uav_lock
	wire   [31:0] button_pio_s1_agent_m0_writedata;                               // button_pio_s1_agent:m0_writedata -> button_pio_s1_translator:uav_writedata
	wire          button_pio_s1_agent_m0_write;                                   // button_pio_s1_agent:m0_write -> button_pio_s1_translator:uav_write
	wire    [2:0] button_pio_s1_agent_m0_burstcount;                              // button_pio_s1_agent:m0_burstcount -> button_pio_s1_translator:uav_burstcount
	wire          button_pio_s1_agent_rf_source_valid;                            // button_pio_s1_agent:rf_source_valid -> button_pio_s1_agent_rsp_fifo:in_valid
	wire  [143:0] button_pio_s1_agent_rf_source_data;                             // button_pio_s1_agent:rf_source_data -> button_pio_s1_agent_rsp_fifo:in_data
	wire          button_pio_s1_agent_rf_source_ready;                            // button_pio_s1_agent_rsp_fifo:in_ready -> button_pio_s1_agent:rf_source_ready
	wire          button_pio_s1_agent_rf_source_startofpacket;                    // button_pio_s1_agent:rf_source_startofpacket -> button_pio_s1_agent_rsp_fifo:in_startofpacket
	wire          button_pio_s1_agent_rf_source_endofpacket;                      // button_pio_s1_agent:rf_source_endofpacket -> button_pio_s1_agent_rsp_fifo:in_endofpacket
	wire          button_pio_s1_agent_rsp_fifo_out_valid;                         // button_pio_s1_agent_rsp_fifo:out_valid -> button_pio_s1_agent:rf_sink_valid
	wire  [143:0] button_pio_s1_agent_rsp_fifo_out_data;                          // button_pio_s1_agent_rsp_fifo:out_data -> button_pio_s1_agent:rf_sink_data
	wire          button_pio_s1_agent_rsp_fifo_out_ready;                         // button_pio_s1_agent:rf_sink_ready -> button_pio_s1_agent_rsp_fifo:out_ready
	wire          button_pio_s1_agent_rsp_fifo_out_startofpacket;                 // button_pio_s1_agent_rsp_fifo:out_startofpacket -> button_pio_s1_agent:rf_sink_startofpacket
	wire          button_pio_s1_agent_rsp_fifo_out_endofpacket;                   // button_pio_s1_agent_rsp_fifo:out_endofpacket -> button_pio_s1_agent:rf_sink_endofpacket
	wire          button_pio_s1_agent_rdata_fifo_src_valid;                       // button_pio_s1_agent:rdata_fifo_src_valid -> button_pio_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] button_pio_s1_agent_rdata_fifo_src_data;                        // button_pio_s1_agent:rdata_fifo_src_data -> button_pio_s1_agent:rdata_fifo_sink_data
	wire          button_pio_s1_agent_rdata_fifo_src_ready;                       // button_pio_s1_agent:rdata_fifo_sink_ready -> button_pio_s1_agent:rdata_fifo_src_ready
	wire          cmd_mux_003_src_valid;                                          // cmd_mux_003:src_valid -> button_pio_s1_agent:cp_valid
	wire  [142:0] cmd_mux_003_src_data;                                           // cmd_mux_003:src_data -> button_pio_s1_agent:cp_data
	wire          cmd_mux_003_src_ready;                                          // button_pio_s1_agent:cp_ready -> cmd_mux_003:src_ready
	wire    [3:0] cmd_mux_003_src_channel;                                        // cmd_mux_003:src_channel -> button_pio_s1_agent:cp_channel
	wire          cmd_mux_003_src_startofpacket;                                  // cmd_mux_003:src_startofpacket -> button_pio_s1_agent:cp_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                    // cmd_mux_003:src_endofpacket -> button_pio_s1_agent:cp_endofpacket
	wire          pb_cpu_0_m0_agent_cp_valid;                                     // pb_cpu_0_m0_agent:cp_valid -> router:sink_valid
	wire  [142:0] pb_cpu_0_m0_agent_cp_data;                                      // pb_cpu_0_m0_agent:cp_data -> router:sink_data
	wire          pb_cpu_0_m0_agent_cp_ready;                                     // router:sink_ready -> pb_cpu_0_m0_agent:cp_ready
	wire          pb_cpu_0_m0_agent_cp_startofpacket;                             // pb_cpu_0_m0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          pb_cpu_0_m0_agent_cp_endofpacket;                               // pb_cpu_0_m0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          sysid_control_slave_agent_rp_valid;                             // sysid_control_slave_agent:rp_valid -> router_001:sink_valid
	wire  [142:0] sysid_control_slave_agent_rp_data;                              // sysid_control_slave_agent:rp_data -> router_001:sink_data
	wire          sysid_control_slave_agent_rp_ready;                             // router_001:sink_ready -> sysid_control_slave_agent:rp_ready
	wire          sysid_control_slave_agent_rp_startofpacket;                     // sysid_control_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          sysid_control_slave_agent_rp_endofpacket;                       // sysid_control_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                           // router_001:src_valid -> rsp_demux:sink_valid
	wire  [142:0] router_001_src_data;                                            // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                           // rsp_demux:sink_ready -> router_001:src_ready
	wire    [3:0] router_001_src_channel;                                         // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                   // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                     // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          led_pio_s1_agent_rp_valid;                                      // led_pio_s1_agent:rp_valid -> router_002:sink_valid
	wire  [142:0] led_pio_s1_agent_rp_data;                                       // led_pio_s1_agent:rp_data -> router_002:sink_data
	wire          led_pio_s1_agent_rp_ready;                                      // router_002:sink_ready -> led_pio_s1_agent:rp_ready
	wire          led_pio_s1_agent_rp_startofpacket;                              // led_pio_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          led_pio_s1_agent_rp_endofpacket;                                // led_pio_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                           // router_002:src_valid -> rsp_demux_001:sink_valid
	wire  [142:0] router_002_src_data;                                            // router_002:src_data -> rsp_demux_001:sink_data
	wire          router_002_src_ready;                                           // rsp_demux_001:sink_ready -> router_002:src_ready
	wire    [3:0] router_002_src_channel;                                         // router_002:src_channel -> rsp_demux_001:sink_channel
	wire          router_002_src_startofpacket;                                   // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_002_src_endofpacket;                                     // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          dipsw_pio_s1_agent_rp_valid;                                    // dipsw_pio_s1_agent:rp_valid -> router_003:sink_valid
	wire  [142:0] dipsw_pio_s1_agent_rp_data;                                     // dipsw_pio_s1_agent:rp_data -> router_003:sink_data
	wire          dipsw_pio_s1_agent_rp_ready;                                    // router_003:sink_ready -> dipsw_pio_s1_agent:rp_ready
	wire          dipsw_pio_s1_agent_rp_startofpacket;                            // dipsw_pio_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire          dipsw_pio_s1_agent_rp_endofpacket;                              // dipsw_pio_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire          router_003_src_valid;                                           // router_003:src_valid -> rsp_demux_002:sink_valid
	wire  [142:0] router_003_src_data;                                            // router_003:src_data -> rsp_demux_002:sink_data
	wire          router_003_src_ready;                                           // rsp_demux_002:sink_ready -> router_003:src_ready
	wire    [3:0] router_003_src_channel;                                         // router_003:src_channel -> rsp_demux_002:sink_channel
	wire          router_003_src_startofpacket;                                   // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_003_src_endofpacket;                                     // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          button_pio_s1_agent_rp_valid;                                   // button_pio_s1_agent:rp_valid -> router_004:sink_valid
	wire  [142:0] button_pio_s1_agent_rp_data;                                    // button_pio_s1_agent:rp_data -> router_004:sink_data
	wire          button_pio_s1_agent_rp_ready;                                   // router_004:sink_ready -> button_pio_s1_agent:rp_ready
	wire          button_pio_s1_agent_rp_startofpacket;                           // button_pio_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          button_pio_s1_agent_rp_endofpacket;                             // button_pio_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                           // router_004:src_valid -> rsp_demux_003:sink_valid
	wire  [142:0] router_004_src_data;                                            // router_004:src_data -> rsp_demux_003:sink_data
	wire          router_004_src_ready;                                           // rsp_demux_003:sink_ready -> router_004:src_ready
	wire    [3:0] router_004_src_channel;                                         // router_004:src_channel -> rsp_demux_003:sink_channel
	wire          router_004_src_startofpacket;                                   // router_004:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_004_src_endofpacket;                                     // router_004:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          router_src_valid;                                               // router:src_valid -> pb_cpu_0_m0_limiter:cmd_sink_valid
	wire  [142:0] router_src_data;                                                // router:src_data -> pb_cpu_0_m0_limiter:cmd_sink_data
	wire          router_src_ready;                                               // pb_cpu_0_m0_limiter:cmd_sink_ready -> router:src_ready
	wire    [3:0] router_src_channel;                                             // router:src_channel -> pb_cpu_0_m0_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                       // router:src_startofpacket -> pb_cpu_0_m0_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                         // router:src_endofpacket -> pb_cpu_0_m0_limiter:cmd_sink_endofpacket
	wire  [142:0] pb_cpu_0_m0_limiter_cmd_src_data;                               // pb_cpu_0_m0_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          pb_cpu_0_m0_limiter_cmd_src_ready;                              // cmd_demux:sink_ready -> pb_cpu_0_m0_limiter:cmd_src_ready
	wire    [3:0] pb_cpu_0_m0_limiter_cmd_src_channel;                            // pb_cpu_0_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          pb_cpu_0_m0_limiter_cmd_src_startofpacket;                      // pb_cpu_0_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          pb_cpu_0_m0_limiter_cmd_src_endofpacket;                        // pb_cpu_0_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                              // rsp_mux:src_valid -> pb_cpu_0_m0_limiter:rsp_sink_valid
	wire  [142:0] rsp_mux_src_data;                                               // rsp_mux:src_data -> pb_cpu_0_m0_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                              // pb_cpu_0_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [3:0] rsp_mux_src_channel;                                            // rsp_mux:src_channel -> pb_cpu_0_m0_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                      // rsp_mux:src_startofpacket -> pb_cpu_0_m0_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                        // rsp_mux:src_endofpacket -> pb_cpu_0_m0_limiter:rsp_sink_endofpacket
	wire          pb_cpu_0_m0_limiter_rsp_src_valid;                              // pb_cpu_0_m0_limiter:rsp_src_valid -> pb_cpu_0_m0_agent:rp_valid
	wire  [142:0] pb_cpu_0_m0_limiter_rsp_src_data;                               // pb_cpu_0_m0_limiter:rsp_src_data -> pb_cpu_0_m0_agent:rp_data
	wire          pb_cpu_0_m0_limiter_rsp_src_ready;                              // pb_cpu_0_m0_agent:rp_ready -> pb_cpu_0_m0_limiter:rsp_src_ready
	wire    [3:0] pb_cpu_0_m0_limiter_rsp_src_channel;                            // pb_cpu_0_m0_limiter:rsp_src_channel -> pb_cpu_0_m0_agent:rp_channel
	wire          pb_cpu_0_m0_limiter_rsp_src_startofpacket;                      // pb_cpu_0_m0_limiter:rsp_src_startofpacket -> pb_cpu_0_m0_agent:rp_startofpacket
	wire          pb_cpu_0_m0_limiter_rsp_src_endofpacket;                        // pb_cpu_0_m0_limiter:rsp_src_endofpacket -> pb_cpu_0_m0_agent:rp_endofpacket
	wire          cmd_demux_src0_valid;                                           // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [142:0] cmd_demux_src0_data;                                            // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                           // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [3:0] cmd_demux_src0_channel;                                         // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                   // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                     // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                           // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [142:0] cmd_demux_src1_data;                                            // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                           // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [3:0] cmd_demux_src1_channel;                                         // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                   // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                     // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                           // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire  [142:0] cmd_demux_src2_data;                                            // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                           // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire    [3:0] cmd_demux_src2_channel;                                         // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                   // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                     // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                           // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire  [142:0] cmd_demux_src3_data;                                            // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_src3_ready;                                           // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire    [3:0] cmd_demux_src3_channel;                                         // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_src3_startofpacket;                                   // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_src3_endofpacket;                                     // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                           // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [142:0] rsp_demux_src0_data;                                            // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                           // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [3:0] rsp_demux_src0_channel;                                         // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                   // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                     // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                       // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [142:0] rsp_demux_001_src0_data;                                        // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                       // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [3:0] rsp_demux_001_src0_channel;                                     // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                               // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                 // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                       // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire  [142:0] rsp_demux_002_src0_data;                                        // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                       // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire    [3:0] rsp_demux_002_src0_channel;                                     // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                               // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                 // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                       // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire  [142:0] rsp_demux_003_src0_data;                                        // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire          rsp_demux_003_src0_ready;                                       // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire    [3:0] rsp_demux_003_src0_channel;                                     // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                               // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                 // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire    [3:0] pb_cpu_0_m0_limiter_cmd_valid_data;                             // pb_cpu_0_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid

	peripheral_subsys_altera_merlin_master_translator_193_lgcew2q #(
		.AV_ADDRESS_W                (17),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (17),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (1),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) pb_cpu_0_m0_translator (
		.clk                    (periph_clk_out_clk_clk),                                         //   input,   width = 1,                       clk.clk
		.reset                  (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset),       //   input,   width = 1,                     reset.reset
		.uav_address            (pb_cpu_0_m0_translator_avalon_universal_master_0_address),       //  output,  width = 17, avalon_universal_master_0.address
		.uav_burstcount         (pb_cpu_0_m0_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (pb_cpu_0_m0_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (pb_cpu_0_m0_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (pb_cpu_0_m0_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (pb_cpu_0_m0_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (pb_cpu_0_m0_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (pb_cpu_0_m0_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (pb_cpu_0_m0_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (pb_cpu_0_m0_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (pb_cpu_0_m0_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (pb_cpu_0_m0_address),                                            //   input,  width = 17,      avalon_anti_master_0.address
		.av_waitrequest         (pb_cpu_0_m0_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_burstcount          (pb_cpu_0_m0_burstcount),                                         //   input,   width = 1,                          .burstcount
		.av_byteenable          (pb_cpu_0_m0_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (pb_cpu_0_m0_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (pb_cpu_0_m0_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (pb_cpu_0_m0_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (pb_cpu_0_m0_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (pb_cpu_0_m0_writedata),                                          //   input,  width = 32,                          .writedata
		.av_debugaccess         (pb_cpu_0_m0_debugaccess),                                        //   input,   width = 1,                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                           // (terminated),                                        
		.av_begintransfer       (1'b0),                                                           // (terminated),                                        
		.av_chipselect          (1'b0),                                                           // (terminated),                                        
		.av_lock                (1'b0),                                                           // (terminated),                                        
		.uav_outputenable       (1'b0),                                                           // (terminated),                                        
		.uav_clken              (),                                                               // (terminated),                                        
		.av_clken               (1'b1),                                                           // (terminated),                                        
		.uav_response           (2'b00),                                                          // (terminated),                                        
		.av_response            (),                                                               // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                           // (terminated),                                        
		.av_writeresponsevalid  ()                                                                // (terminated),                                        
	);

	peripheral_subsys_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) sysid_control_slave_translator (
		.clk                    (periph_clk_out_clk_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (sysid_control_slave_agent_m0_address),                     //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (sysid_control_slave_agent_m0_burstcount),                  //   input,   width = 3,                         .burstcount
		.uav_read               (sysid_control_slave_agent_m0_read),                        //   input,   width = 1,                         .read
		.uav_write              (sysid_control_slave_agent_m0_write),                       //   input,   width = 1,                         .write
		.uav_waitrequest        (sysid_control_slave_agent_m0_waitrequest),                 //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (sysid_control_slave_agent_m0_readdatavalid),               //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (sysid_control_slave_agent_m0_byteenable),                  //   input,   width = 4,                         .byteenable
		.uav_readdata           (sysid_control_slave_agent_m0_readdata),                    //  output,  width = 32,                         .readdata
		.uav_writedata          (sysid_control_slave_agent_m0_writedata),                   //   input,  width = 32,                         .writedata
		.uav_lock               (sysid_control_slave_agent_m0_lock),                        //   input,   width = 1,                         .lock
		.uav_debugaccess        (sysid_control_slave_agent_m0_debugaccess),                 //   input,   width = 1,                         .debugaccess
		.av_address             (sysid_control_slave_address),                              //  output,   width = 1,      avalon_anti_slave_0.address
		.av_readdata            (sysid_control_slave_readdata),                             //   input,  width = 32,                         .readdata
		.av_write               (),                                                         // (terminated),                                       
		.av_read                (),                                                         // (terminated),                                       
		.av_writedata           (),                                                         // (terminated),                                       
		.av_begintransfer       (),                                                         // (terminated),                                       
		.av_beginbursttransfer  (),                                                         // (terminated),                                       
		.av_burstcount          (),                                                         // (terminated),                                       
		.av_byteenable          (),                                                         // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                     // (terminated),                                       
		.av_waitrequest         (1'b0),                                                     // (terminated),                                       
		.av_writebyteenable     (),                                                         // (terminated),                                       
		.av_lock                (),                                                         // (terminated),                                       
		.av_chipselect          (),                                                         // (terminated),                                       
		.av_clken               (),                                                         // (terminated),                                       
		.uav_clken              (1'b0),                                                     // (terminated),                                       
		.av_debugaccess         (),                                                         // (terminated),                                       
		.av_outputenable        (),                                                         // (terminated),                                       
		.uav_response           (),                                                         // (terminated),                                       
		.av_response            (2'b00),                                                    // (terminated),                                       
		.uav_writeresponsevalid (),                                                         // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                      // (terminated),                                       
	);

	peripheral_subsys_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) led_pio_s1_translator (
		.clk                    (periph_clk_out_clk_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (led_pio_s1_agent_m0_address),                              //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (led_pio_s1_agent_m0_burstcount),                           //   input,   width = 3,                         .burstcount
		.uav_read               (led_pio_s1_agent_m0_read),                                 //   input,   width = 1,                         .read
		.uav_write              (led_pio_s1_agent_m0_write),                                //   input,   width = 1,                         .write
		.uav_waitrequest        (led_pio_s1_agent_m0_waitrequest),                          //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (led_pio_s1_agent_m0_readdatavalid),                        //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (led_pio_s1_agent_m0_byteenable),                           //   input,   width = 4,                         .byteenable
		.uav_readdata           (led_pio_s1_agent_m0_readdata),                             //  output,  width = 32,                         .readdata
		.uav_writedata          (led_pio_s1_agent_m0_writedata),                            //   input,  width = 32,                         .writedata
		.uav_lock               (led_pio_s1_agent_m0_lock),                                 //   input,   width = 1,                         .lock
		.uav_debugaccess        (led_pio_s1_agent_m0_debugaccess),                          //   input,   width = 1,                         .debugaccess
		.av_address             (led_pio_s1_address),                                       //  output,   width = 2,      avalon_anti_slave_0.address
		.av_write               (led_pio_s1_write),                                         //  output,   width = 1,                         .write
		.av_readdata            (led_pio_s1_readdata),                                      //   input,  width = 32,                         .readdata
		.av_writedata           (led_pio_s1_writedata),                                     //  output,  width = 32,                         .writedata
		.av_chipselect          (led_pio_s1_chipselect),                                    //  output,   width = 1,                         .chipselect
		.av_read                (),                                                         // (terminated),                                       
		.av_begintransfer       (),                                                         // (terminated),                                       
		.av_beginbursttransfer  (),                                                         // (terminated),                                       
		.av_burstcount          (),                                                         // (terminated),                                       
		.av_byteenable          (),                                                         // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                     // (terminated),                                       
		.av_waitrequest         (1'b0),                                                     // (terminated),                                       
		.av_writebyteenable     (),                                                         // (terminated),                                       
		.av_lock                (),                                                         // (terminated),                                       
		.av_clken               (),                                                         // (terminated),                                       
		.uav_clken              (1'b0),                                                     // (terminated),                                       
		.av_debugaccess         (),                                                         // (terminated),                                       
		.av_outputenable        (),                                                         // (terminated),                                       
		.uav_response           (),                                                         // (terminated),                                       
		.av_response            (2'b00),                                                    // (terminated),                                       
		.uav_writeresponsevalid (),                                                         // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                      // (terminated),                                       
	);

	peripheral_subsys_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) dipsw_pio_s1_translator (
		.clk                    (periph_clk_out_clk_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (dipsw_pio_s1_agent_m0_address),                            //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (dipsw_pio_s1_agent_m0_burstcount),                         //   input,   width = 3,                         .burstcount
		.uav_read               (dipsw_pio_s1_agent_m0_read),                               //   input,   width = 1,                         .read
		.uav_write              (dipsw_pio_s1_agent_m0_write),                              //   input,   width = 1,                         .write
		.uav_waitrequest        (dipsw_pio_s1_agent_m0_waitrequest),                        //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (dipsw_pio_s1_agent_m0_readdatavalid),                      //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (dipsw_pio_s1_agent_m0_byteenable),                         //   input,   width = 4,                         .byteenable
		.uav_readdata           (dipsw_pio_s1_agent_m0_readdata),                           //  output,  width = 32,                         .readdata
		.uav_writedata          (dipsw_pio_s1_agent_m0_writedata),                          //   input,  width = 32,                         .writedata
		.uav_lock               (dipsw_pio_s1_agent_m0_lock),                               //   input,   width = 1,                         .lock
		.uav_debugaccess        (dipsw_pio_s1_agent_m0_debugaccess),                        //   input,   width = 1,                         .debugaccess
		.av_address             (dipsw_pio_s1_address),                                     //  output,   width = 2,      avalon_anti_slave_0.address
		.av_write               (dipsw_pio_s1_write),                                       //  output,   width = 1,                         .write
		.av_readdata            (dipsw_pio_s1_readdata),                                    //   input,  width = 32,                         .readdata
		.av_writedata           (dipsw_pio_s1_writedata),                                   //  output,  width = 32,                         .writedata
		.av_chipselect          (dipsw_pio_s1_chipselect),                                  //  output,   width = 1,                         .chipselect
		.av_read                (),                                                         // (terminated),                                       
		.av_begintransfer       (),                                                         // (terminated),                                       
		.av_beginbursttransfer  (),                                                         // (terminated),                                       
		.av_burstcount          (),                                                         // (terminated),                                       
		.av_byteenable          (),                                                         // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                     // (terminated),                                       
		.av_waitrequest         (1'b0),                                                     // (terminated),                                       
		.av_writebyteenable     (),                                                         // (terminated),                                       
		.av_lock                (),                                                         // (terminated),                                       
		.av_clken               (),                                                         // (terminated),                                       
		.uav_clken              (1'b0),                                                     // (terminated),                                       
		.av_debugaccess         (),                                                         // (terminated),                                       
		.av_outputenable        (),                                                         // (terminated),                                       
		.uav_response           (),                                                         // (terminated),                                       
		.av_response            (2'b00),                                                    // (terminated),                                       
		.uav_writeresponsevalid (),                                                         // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                      // (terminated),                                       
	);

	peripheral_subsys_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (17),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) button_pio_s1_translator (
		.clk                    (periph_clk_out_clk_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (button_pio_s1_agent_m0_address),                           //   input,  width = 17, avalon_universal_slave_0.address
		.uav_burstcount         (button_pio_s1_agent_m0_burstcount),                        //   input,   width = 3,                         .burstcount
		.uav_read               (button_pio_s1_agent_m0_read),                              //   input,   width = 1,                         .read
		.uav_write              (button_pio_s1_agent_m0_write),                             //   input,   width = 1,                         .write
		.uav_waitrequest        (button_pio_s1_agent_m0_waitrequest),                       //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (button_pio_s1_agent_m0_readdatavalid),                     //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (button_pio_s1_agent_m0_byteenable),                        //   input,   width = 4,                         .byteenable
		.uav_readdata           (button_pio_s1_agent_m0_readdata),                          //  output,  width = 32,                         .readdata
		.uav_writedata          (button_pio_s1_agent_m0_writedata),                         //   input,  width = 32,                         .writedata
		.uav_lock               (button_pio_s1_agent_m0_lock),                              //   input,   width = 1,                         .lock
		.uav_debugaccess        (button_pio_s1_agent_m0_debugaccess),                       //   input,   width = 1,                         .debugaccess
		.av_address             (button_pio_s1_address),                                    //  output,   width = 2,      avalon_anti_slave_0.address
		.av_write               (button_pio_s1_write),                                      //  output,   width = 1,                         .write
		.av_readdata            (button_pio_s1_readdata),                                   //   input,  width = 32,                         .readdata
		.av_writedata           (button_pio_s1_writedata),                                  //  output,  width = 32,                         .writedata
		.av_chipselect          (button_pio_s1_chipselect),                                 //  output,   width = 1,                         .chipselect
		.av_read                (),                                                         // (terminated),                                       
		.av_begintransfer       (),                                                         // (terminated),                                       
		.av_beginbursttransfer  (),                                                         // (terminated),                                       
		.av_burstcount          (),                                                         // (terminated),                                       
		.av_byteenable          (),                                                         // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                     // (terminated),                                       
		.av_waitrequest         (1'b0),                                                     // (terminated),                                       
		.av_writebyteenable     (),                                                         // (terminated),                                       
		.av_lock                (),                                                         // (terminated),                                       
		.av_clken               (),                                                         // (terminated),                                       
		.uav_clken              (1'b0),                                                     // (terminated),                                       
		.av_debugaccess         (),                                                         // (terminated),                                       
		.av_outputenable        (),                                                         // (terminated),                                       
		.uav_response           (),                                                         // (terminated),                                       
		.av_response            (2'b00),                                                    // (terminated),                                       
		.uav_writeresponsevalid (),                                                         // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                      // (terminated),                                       
	);

	peripheral_subsys_altera_merlin_master_agent_1940_r3ep6da #(
		.PKT_WUNIQUE               (97),
		.PKT_DOMAIN_H              (96),
		.PKT_DOMAIN_L              (95),
		.PKT_SNOOP_H               (94),
		.PKT_SNOOP_L               (91),
		.PKT_BARRIER_H             (90),
		.PKT_BARRIER_L             (89),
		.PKT_ORI_BURST_SIZE_H      (88),
		.PKT_ORI_BURST_SIZE_L      (86),
		.PKT_RESPONSE_STATUS_H     (85),
		.PKT_RESPONSE_STATUS_L     (84),
		.PKT_QOS_H                 (71),
		.PKT_QOS_L                 (71),
		.PKT_DATA_SIDEBAND_H       (69),
		.PKT_DATA_SIDEBAND_L       (69),
		.PKT_ADDR_SIDEBAND_H       (68),
		.PKT_ADDR_SIDEBAND_L       (68),
		.PKT_BURST_TYPE_H          (67),
		.PKT_BURST_TYPE_L          (66),
		.PKT_CACHE_H               (83),
		.PKT_CACHE_L               (80),
		.PKT_THREAD_ID_H           (76),
		.PKT_THREAD_ID_L           (76),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_EXCLUSIVE       (58),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (77),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (73),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (75),
		.PKT_DEST_ID_L             (74),
		.PKT_POISON_H              (98),
		.PKT_POISON_L              (98),
		.PKT_DATACHK_H             (99),
		.PKT_DATACHK_L             (99),
		.PKT_ADDRCHK_H             (102),
		.PKT_ADDRCHK_L             (101),
		.PKT_SAI_H                 (103),
		.PKT_SAI_L                 (103),
		.PKT_USER_DATA_H           (100),
		.PKT_USER_DATA_L           (100),
		.PKT_ATRACE                (113),
		.PKT_TRACE                 (114),
		.PKT_AWAKEUP               (115),
		.PKT_AWATOP_H              (121),
		.PKT_AWATOP_L              (116),
		.PKT_AWSTASHNID_H          (132),
		.PKT_AWSTASHNID_L          (122),
		.PKT_AWSTASHNIDEN          (133),
		.PKT_AWSTASHLPID_H         (138),
		.PKT_AWSTASHLPID_L         (134),
		.PKT_AWSTASHLPIDEN         (139),
		.PKT_MMUSECSID             (141),
		.PKT_MMUSID_H              (140),
		.PKT_MMUSID_L              (140),
		.PKT_DATALESS              (142),
		.ST_DATA_W                 (143),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.AWATOP_VALUE              (0),
		.AWSTASHNID_VALUE          (0),
		.AWSTASHNIDEN_VALUE        (0),
		.AWSTASHLPID_VALUE         (0),
		.AWSTASHLPIDEN_VALUE       (0),
		.MMUSECSID_VALUE           (0),
		.MMUSID_VALUE              (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.OPTIMIZED_READS_WITH_BE   (0)
	) pb_cpu_0_m0_agent (
		.clk                   (periph_clk_out_clk_clk),                                         //   input,    width = 1,       clk.clk
		.reset                 (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset),       //   input,    width = 1, clk_reset.reset
		.av_address            (pb_cpu_0_m0_translator_avalon_universal_master_0_address),       //   input,   width = 17,        av.address
		.av_write              (pb_cpu_0_m0_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (pb_cpu_0_m0_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (pb_cpu_0_m0_translator_avalon_universal_master_0_writedata),     //   input,   width = 32,          .writedata
		.av_readdata           (pb_cpu_0_m0_translator_avalon_universal_master_0_readdata),      //  output,   width = 32,          .readdata
		.av_waitrequest        (pb_cpu_0_m0_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (pb_cpu_0_m0_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (pb_cpu_0_m0_translator_avalon_universal_master_0_byteenable),    //   input,    width = 4,          .byteenable
		.av_burstcount         (pb_cpu_0_m0_translator_avalon_universal_master_0_burstcount),    //   input,    width = 3,          .burstcount
		.av_debugaccess        (pb_cpu_0_m0_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (pb_cpu_0_m0_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (pb_cpu_0_m0_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (pb_cpu_0_m0_agent_cp_data),                                      //  output,  width = 143,          .data
		.cp_startofpacket      (pb_cpu_0_m0_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (pb_cpu_0_m0_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (pb_cpu_0_m0_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (pb_cpu_0_m0_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (pb_cpu_0_m0_limiter_rsp_src_data),                               //   input,  width = 143,          .data
		.rp_channel            (pb_cpu_0_m0_limiter_rsp_src_channel),                            //   input,    width = 4,          .channel
		.rp_startofpacket      (pb_cpu_0_m0_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (pb_cpu_0_m0_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (pb_cpu_0_m0_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                               // (terminated),                         
		.av_writeresponsevalid ()                                                                // (terminated),                         
	);

	peripheral_subsys_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (88),
		.PKT_ORI_BURST_SIZE_L      (86),
		.PKT_RESPONSE_STATUS_H     (85),
		.PKT_RESPONSE_STATUS_L     (84),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (77),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (73),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (75),
		.PKT_DEST_ID_L             (74),
		.PKT_POISON_H              (98),
		.PKT_POISON_L              (98),
		.PKT_DATACHK_H             (99),
		.PKT_DATACHK_L             (99),
		.PKT_SAI_H                 (103),
		.PKT_SAI_L                 (103),
		.PKT_ADDRCHK_H             (102),
		.PKT_ADDRCHK_L             (101),
		.PKT_USER_DATA_H           (100),
		.PKT_USER_DATA_L           (100),
		.PKT_ATRACE                (113),
		.PKT_TRACE                 (114),
		.PKT_AWAKEUP               (115),
		.PKT_AWATOP_H              (121),
		.PKT_AWATOP_L              (116),
		.PKT_AWSTASHNID_H          (132),
		.PKT_AWSTASHNID_L          (122),
		.PKT_AWSTASHNIDEN          (133),
		.PKT_AWSTASHLPID_H         (138),
		.PKT_AWSTASHLPID_L         (134),
		.PKT_AWSTASHLPIDEN         (139),
		.PKT_MMUSECSID             (141),
		.PKT_MMUSID_H              (140),
		.PKT_MMUSID_L              (140),
		.PKT_DATALESS              (142),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (143),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) sysid_control_slave_agent (
		.clk                     (periph_clk_out_clk_clk),                                   //   input,    width = 1,             clk.clk
		.reset                   (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (sysid_control_slave_agent_m0_address),                     //  output,   width = 17,              m0.address
		.m0_burstcount           (sysid_control_slave_agent_m0_burstcount),                  //  output,    width = 3,                .burstcount
		.m0_byteenable           (sysid_control_slave_agent_m0_byteenable),                  //  output,    width = 4,                .byteenable
		.m0_debugaccess          (sysid_control_slave_agent_m0_debugaccess),                 //  output,    width = 1,                .debugaccess
		.m0_lock                 (sysid_control_slave_agent_m0_lock),                        //  output,    width = 1,                .lock
		.m0_readdata             (sysid_control_slave_agent_m0_readdata),                    //   input,   width = 32,                .readdata
		.m0_readdatavalid        (sysid_control_slave_agent_m0_readdatavalid),               //   input,    width = 1,                .readdatavalid
		.m0_read                 (sysid_control_slave_agent_m0_read),                        //  output,    width = 1,                .read
		.m0_waitrequest          (sysid_control_slave_agent_m0_waitrequest),                 //   input,    width = 1,                .waitrequest
		.m0_writedata            (sysid_control_slave_agent_m0_writedata),                   //  output,   width = 32,                .writedata
		.m0_write                (sysid_control_slave_agent_m0_write),                       //  output,    width = 1,                .write
		.rp_endofpacket          (sysid_control_slave_agent_rp_endofpacket),                 //  output,    width = 1,              rp.endofpacket
		.rp_ready                (sysid_control_slave_agent_rp_ready),                       //   input,    width = 1,                .ready
		.rp_valid                (sysid_control_slave_agent_rp_valid),                       //  output,    width = 1,                .valid
		.rp_data                 (sysid_control_slave_agent_rp_data),                        //  output,  width = 143,                .data
		.rp_startofpacket        (sysid_control_slave_agent_rp_startofpacket),               //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                        //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                        //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_src_data),                                         //   input,  width = 143,                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                  //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                      //   input,    width = 4,                .channel
		.rf_sink_ready           (sysid_control_slave_agent_rsp_fifo_out_ready),             //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (sysid_control_slave_agent_rsp_fifo_out_valid),             //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (sysid_control_slave_agent_rsp_fifo_out_startofpacket),     //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (sysid_control_slave_agent_rsp_fifo_out_endofpacket),       //   input,    width = 1,                .endofpacket
		.rf_sink_data            (sysid_control_slave_agent_rsp_fifo_out_data),              //   input,  width = 144,                .data
		.rf_source_ready         (sysid_control_slave_agent_rf_source_ready),                //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (sysid_control_slave_agent_rf_source_valid),                //  output,    width = 1,                .valid
		.rf_source_startofpacket (sysid_control_slave_agent_rf_source_startofpacket),        //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (sysid_control_slave_agent_rf_source_endofpacket),          //  output,    width = 1,                .endofpacket
		.rf_source_data          (sysid_control_slave_agent_rf_source_data),                 //  output,  width = 144,                .data
		.rdata_fifo_sink_ready   (sysid_control_slave_agent_rdata_fifo_src_ready),           //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sysid_control_slave_agent_rdata_fifo_src_valid),           //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (sysid_control_slave_agent_rdata_fifo_src_data),            //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (sysid_control_slave_agent_rdata_fifo_src_ready),           //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sysid_control_slave_agent_rdata_fifo_src_valid),           //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (sysid_control_slave_agent_rdata_fifo_src_data),            //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                    // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                     // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                      // (terminated),                               
	);

	peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (144),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) sysid_control_slave_agent_rsp_fifo (
		.clk               (periph_clk_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset             (pb_cpu_0_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (sysid_control_slave_agent_rf_source_data),             //   input,  width = 144,        in.data
		.in_valid          (sysid_control_slave_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (sysid_control_slave_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (sysid_control_slave_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (sysid_control_slave_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (sysid_control_slave_agent_rsp_fifo_out_data),          //  output,  width = 144,       out.data
		.out_valid         (sysid_control_slave_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (sysid_control_slave_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (sysid_control_slave_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (sysid_control_slave_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                // (terminated),                         
		.csr_read          (1'b0),                                                 // (terminated),                         
		.csr_write         (1'b0),                                                 // (terminated),                         
		.csr_readdata      (),                                                     // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated),                         
		.almost_full_data  (),                                                     // (terminated),                         
		.almost_empty_data (),                                                     // (terminated),                         
		.in_empty          (1'b0),                                                 // (terminated),                         
		.out_empty         (),                                                     // (terminated),                         
		.in_error          (1'b0),                                                 // (terminated),                         
		.out_error         (),                                                     // (terminated),                         
		.in_channel        (1'b0),                                                 // (terminated),                         
		.out_channel       ()                                                      // (terminated),                         
	);

	peripheral_subsys_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (88),
		.PKT_ORI_BURST_SIZE_L      (86),
		.PKT_RESPONSE_STATUS_H     (85),
		.PKT_RESPONSE_STATUS_L     (84),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (77),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (73),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (75),
		.PKT_DEST_ID_L             (74),
		.PKT_POISON_H              (98),
		.PKT_POISON_L              (98),
		.PKT_DATACHK_H             (99),
		.PKT_DATACHK_L             (99),
		.PKT_SAI_H                 (103),
		.PKT_SAI_L                 (103),
		.PKT_ADDRCHK_H             (102),
		.PKT_ADDRCHK_L             (101),
		.PKT_USER_DATA_H           (100),
		.PKT_USER_DATA_L           (100),
		.PKT_ATRACE                (113),
		.PKT_TRACE                 (114),
		.PKT_AWAKEUP               (115),
		.PKT_AWATOP_H              (121),
		.PKT_AWATOP_L              (116),
		.PKT_AWSTASHNID_H          (132),
		.PKT_AWSTASHNID_L          (122),
		.PKT_AWSTASHNIDEN          (133),
		.PKT_AWSTASHLPID_H         (138),
		.PKT_AWSTASHLPID_L         (134),
		.PKT_AWSTASHLPIDEN         (139),
		.PKT_MMUSECSID             (141),
		.PKT_MMUSID_H              (140),
		.PKT_MMUSID_L              (140),
		.PKT_DATALESS              (142),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (143),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) led_pio_s1_agent (
		.clk                     (periph_clk_out_clk_clk),                                   //   input,    width = 1,             clk.clk
		.reset                   (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (led_pio_s1_agent_m0_address),                              //  output,   width = 17,              m0.address
		.m0_burstcount           (led_pio_s1_agent_m0_burstcount),                           //  output,    width = 3,                .burstcount
		.m0_byteenable           (led_pio_s1_agent_m0_byteenable),                           //  output,    width = 4,                .byteenable
		.m0_debugaccess          (led_pio_s1_agent_m0_debugaccess),                          //  output,    width = 1,                .debugaccess
		.m0_lock                 (led_pio_s1_agent_m0_lock),                                 //  output,    width = 1,                .lock
		.m0_readdata             (led_pio_s1_agent_m0_readdata),                             //   input,   width = 32,                .readdata
		.m0_readdatavalid        (led_pio_s1_agent_m0_readdatavalid),                        //   input,    width = 1,                .readdatavalid
		.m0_read                 (led_pio_s1_agent_m0_read),                                 //  output,    width = 1,                .read
		.m0_waitrequest          (led_pio_s1_agent_m0_waitrequest),                          //   input,    width = 1,                .waitrequest
		.m0_writedata            (led_pio_s1_agent_m0_writedata),                            //  output,   width = 32,                .writedata
		.m0_write                (led_pio_s1_agent_m0_write),                                //  output,    width = 1,                .write
		.rp_endofpacket          (led_pio_s1_agent_rp_endofpacket),                          //  output,    width = 1,              rp.endofpacket
		.rp_ready                (led_pio_s1_agent_rp_ready),                                //   input,    width = 1,                .ready
		.rp_valid                (led_pio_s1_agent_rp_valid),                                //  output,    width = 1,                .valid
		.rp_data                 (led_pio_s1_agent_rp_data),                                 //  output,  width = 143,                .data
		.rp_startofpacket        (led_pio_s1_agent_rp_startofpacket),                        //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_001_src_ready),                                    //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_001_src_valid),                                    //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_001_src_data),                                     //   input,  width = 143,                .data
		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                            //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                              //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_001_src_channel),                                  //   input,    width = 4,                .channel
		.rf_sink_ready           (led_pio_s1_agent_rsp_fifo_out_ready),                      //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (led_pio_s1_agent_rsp_fifo_out_valid),                      //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (led_pio_s1_agent_rsp_fifo_out_startofpacket),              //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (led_pio_s1_agent_rsp_fifo_out_endofpacket),                //   input,    width = 1,                .endofpacket
		.rf_sink_data            (led_pio_s1_agent_rsp_fifo_out_data),                       //   input,  width = 144,                .data
		.rf_source_ready         (led_pio_s1_agent_rf_source_ready),                         //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (led_pio_s1_agent_rf_source_valid),                         //  output,    width = 1,                .valid
		.rf_source_startofpacket (led_pio_s1_agent_rf_source_startofpacket),                 //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (led_pio_s1_agent_rf_source_endofpacket),                   //  output,    width = 1,                .endofpacket
		.rf_source_data          (led_pio_s1_agent_rf_source_data),                          //  output,  width = 144,                .data
		.rdata_fifo_sink_ready   (led_pio_s1_agent_rdata_fifo_src_ready),                    //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (led_pio_s1_agent_rdata_fifo_src_valid),                    //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (led_pio_s1_agent_rdata_fifo_src_data),                     //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (led_pio_s1_agent_rdata_fifo_src_ready),                    //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (led_pio_s1_agent_rdata_fifo_src_valid),                    //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (led_pio_s1_agent_rdata_fifo_src_data),                     //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                    // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                     // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                      // (terminated),                               
	);

	peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (144),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) led_pio_s1_agent_rsp_fifo (
		.clk               (periph_clk_out_clk_clk),                      //   input,    width = 1,       clk.clk
		.reset             (pb_cpu_0_reset_reset_bridge_in_reset_reset),  //   input,    width = 1, clk_reset.reset
		.in_data           (led_pio_s1_agent_rf_source_data),             //   input,  width = 144,        in.data
		.in_valid          (led_pio_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (led_pio_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (led_pio_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (led_pio_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (led_pio_s1_agent_rsp_fifo_out_data),          //  output,  width = 144,       out.data
		.out_valid         (led_pio_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (led_pio_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (led_pio_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (led_pio_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                       // (terminated),                         
		.csr_read          (1'b0),                                        // (terminated),                         
		.csr_write         (1'b0),                                        // (terminated),                         
		.csr_readdata      (),                                            // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),        // (terminated),                         
		.almost_full_data  (),                                            // (terminated),                         
		.almost_empty_data (),                                            // (terminated),                         
		.in_empty          (1'b0),                                        // (terminated),                         
		.out_empty         (),                                            // (terminated),                         
		.in_error          (1'b0),                                        // (terminated),                         
		.out_error         (),                                            // (terminated),                         
		.in_channel        (1'b0),                                        // (terminated),                         
		.out_channel       ()                                             // (terminated),                         
	);

	peripheral_subsys_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (88),
		.PKT_ORI_BURST_SIZE_L      (86),
		.PKT_RESPONSE_STATUS_H     (85),
		.PKT_RESPONSE_STATUS_L     (84),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (77),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (73),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (75),
		.PKT_DEST_ID_L             (74),
		.PKT_POISON_H              (98),
		.PKT_POISON_L              (98),
		.PKT_DATACHK_H             (99),
		.PKT_DATACHK_L             (99),
		.PKT_SAI_H                 (103),
		.PKT_SAI_L                 (103),
		.PKT_ADDRCHK_H             (102),
		.PKT_ADDRCHK_L             (101),
		.PKT_USER_DATA_H           (100),
		.PKT_USER_DATA_L           (100),
		.PKT_ATRACE                (113),
		.PKT_TRACE                 (114),
		.PKT_AWAKEUP               (115),
		.PKT_AWATOP_H              (121),
		.PKT_AWATOP_L              (116),
		.PKT_AWSTASHNID_H          (132),
		.PKT_AWSTASHNID_L          (122),
		.PKT_AWSTASHNIDEN          (133),
		.PKT_AWSTASHLPID_H         (138),
		.PKT_AWSTASHLPID_L         (134),
		.PKT_AWSTASHLPIDEN         (139),
		.PKT_MMUSECSID             (141),
		.PKT_MMUSID_H              (140),
		.PKT_MMUSID_L              (140),
		.PKT_DATALESS              (142),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (143),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) dipsw_pio_s1_agent (
		.clk                     (periph_clk_out_clk_clk),                                   //   input,    width = 1,             clk.clk
		.reset                   (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (dipsw_pio_s1_agent_m0_address),                            //  output,   width = 17,              m0.address
		.m0_burstcount           (dipsw_pio_s1_agent_m0_burstcount),                         //  output,    width = 3,                .burstcount
		.m0_byteenable           (dipsw_pio_s1_agent_m0_byteenable),                         //  output,    width = 4,                .byteenable
		.m0_debugaccess          (dipsw_pio_s1_agent_m0_debugaccess),                        //  output,    width = 1,                .debugaccess
		.m0_lock                 (dipsw_pio_s1_agent_m0_lock),                               //  output,    width = 1,                .lock
		.m0_readdata             (dipsw_pio_s1_agent_m0_readdata),                           //   input,   width = 32,                .readdata
		.m0_readdatavalid        (dipsw_pio_s1_agent_m0_readdatavalid),                      //   input,    width = 1,                .readdatavalid
		.m0_read                 (dipsw_pio_s1_agent_m0_read),                               //  output,    width = 1,                .read
		.m0_waitrequest          (dipsw_pio_s1_agent_m0_waitrequest),                        //   input,    width = 1,                .waitrequest
		.m0_writedata            (dipsw_pio_s1_agent_m0_writedata),                          //  output,   width = 32,                .writedata
		.m0_write                (dipsw_pio_s1_agent_m0_write),                              //  output,    width = 1,                .write
		.rp_endofpacket          (dipsw_pio_s1_agent_rp_endofpacket),                        //  output,    width = 1,              rp.endofpacket
		.rp_ready                (dipsw_pio_s1_agent_rp_ready),                              //   input,    width = 1,                .ready
		.rp_valid                (dipsw_pio_s1_agent_rp_valid),                              //  output,    width = 1,                .valid
		.rp_data                 (dipsw_pio_s1_agent_rp_data),                               //  output,  width = 143,                .data
		.rp_startofpacket        (dipsw_pio_s1_agent_rp_startofpacket),                      //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_002_src_ready),                                    //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_002_src_valid),                                    //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_002_src_data),                                     //   input,  width = 143,                .data
		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                            //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                              //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_002_src_channel),                                  //   input,    width = 4,                .channel
		.rf_sink_ready           (dipsw_pio_s1_agent_rsp_fifo_out_ready),                    //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (dipsw_pio_s1_agent_rsp_fifo_out_valid),                    //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (dipsw_pio_s1_agent_rsp_fifo_out_startofpacket),            //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (dipsw_pio_s1_agent_rsp_fifo_out_endofpacket),              //   input,    width = 1,                .endofpacket
		.rf_sink_data            (dipsw_pio_s1_agent_rsp_fifo_out_data),                     //   input,  width = 144,                .data
		.rf_source_ready         (dipsw_pio_s1_agent_rf_source_ready),                       //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (dipsw_pio_s1_agent_rf_source_valid),                       //  output,    width = 1,                .valid
		.rf_source_startofpacket (dipsw_pio_s1_agent_rf_source_startofpacket),               //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (dipsw_pio_s1_agent_rf_source_endofpacket),                 //  output,    width = 1,                .endofpacket
		.rf_source_data          (dipsw_pio_s1_agent_rf_source_data),                        //  output,  width = 144,                .data
		.rdata_fifo_sink_ready   (dipsw_pio_s1_agent_rdata_fifo_src_ready),                  //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (dipsw_pio_s1_agent_rdata_fifo_src_valid),                  //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (dipsw_pio_s1_agent_rdata_fifo_src_data),                   //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (dipsw_pio_s1_agent_rdata_fifo_src_ready),                  //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (dipsw_pio_s1_agent_rdata_fifo_src_valid),                  //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (dipsw_pio_s1_agent_rdata_fifo_src_data),                   //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                    // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                     // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                      // (terminated),                               
	);

	peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (144),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) dipsw_pio_s1_agent_rsp_fifo (
		.clk               (periph_clk_out_clk_clk),                        //   input,    width = 1,       clk.clk
		.reset             (pb_cpu_0_reset_reset_bridge_in_reset_reset),    //   input,    width = 1, clk_reset.reset
		.in_data           (dipsw_pio_s1_agent_rf_source_data),             //   input,  width = 144,        in.data
		.in_valid          (dipsw_pio_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (dipsw_pio_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (dipsw_pio_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (dipsw_pio_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (dipsw_pio_s1_agent_rsp_fifo_out_data),          //  output,  width = 144,       out.data
		.out_valid         (dipsw_pio_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (dipsw_pio_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (dipsw_pio_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (dipsw_pio_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                         // (terminated),                         
		.csr_read          (1'b0),                                          // (terminated),                         
		.csr_write         (1'b0),                                          // (terminated),                         
		.csr_readdata      (),                                              // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),          // (terminated),                         
		.almost_full_data  (),                                              // (terminated),                         
		.almost_empty_data (),                                              // (terminated),                         
		.in_empty          (1'b0),                                          // (terminated),                         
		.out_empty         (),                                              // (terminated),                         
		.in_error          (1'b0),                                          // (terminated),                         
		.out_error         (),                                              // (terminated),                         
		.in_channel        (1'b0),                                          // (terminated),                         
		.out_channel       ()                                               // (terminated),                         
	);

	peripheral_subsys_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (88),
		.PKT_ORI_BURST_SIZE_L      (86),
		.PKT_RESPONSE_STATUS_H     (85),
		.PKT_RESPONSE_STATUS_L     (84),
		.PKT_BURST_SIZE_H          (65),
		.PKT_BURST_SIZE_L          (63),
		.PKT_TRANS_LOCK            (57),
		.PKT_BEGIN_BURST           (70),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (77),
		.PKT_BURSTWRAP_H           (62),
		.PKT_BURSTWRAP_L           (62),
		.PKT_BYTE_CNT_H            (61),
		.PKT_BYTE_CNT_L            (59),
		.PKT_ADDR_H                (52),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (53),
		.PKT_TRANS_POSTED          (54),
		.PKT_TRANS_WRITE           (55),
		.PKT_TRANS_READ            (56),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (73),
		.PKT_SRC_ID_L              (72),
		.PKT_DEST_ID_H             (75),
		.PKT_DEST_ID_L             (74),
		.PKT_POISON_H              (98),
		.PKT_POISON_L              (98),
		.PKT_DATACHK_H             (99),
		.PKT_DATACHK_L             (99),
		.PKT_SAI_H                 (103),
		.PKT_SAI_L                 (103),
		.PKT_ADDRCHK_H             (102),
		.PKT_ADDRCHK_L             (101),
		.PKT_USER_DATA_H           (100),
		.PKT_USER_DATA_L           (100),
		.PKT_ATRACE                (113),
		.PKT_TRACE                 (114),
		.PKT_AWAKEUP               (115),
		.PKT_AWATOP_H              (121),
		.PKT_AWATOP_L              (116),
		.PKT_AWSTASHNID_H          (132),
		.PKT_AWSTASHNID_L          (122),
		.PKT_AWSTASHNIDEN          (133),
		.PKT_AWSTASHLPID_H         (138),
		.PKT_AWSTASHLPID_L         (134),
		.PKT_AWSTASHLPIDEN         (139),
		.PKT_MMUSECSID             (141),
		.PKT_MMUSID_H              (140),
		.PKT_MMUSID_L              (140),
		.PKT_DATALESS              (142),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (143),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) button_pio_s1_agent (
		.clk                     (periph_clk_out_clk_clk),                                   //   input,    width = 1,             clk.clk
		.reset                   (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (button_pio_s1_agent_m0_address),                           //  output,   width = 17,              m0.address
		.m0_burstcount           (button_pio_s1_agent_m0_burstcount),                        //  output,    width = 3,                .burstcount
		.m0_byteenable           (button_pio_s1_agent_m0_byteenable),                        //  output,    width = 4,                .byteenable
		.m0_debugaccess          (button_pio_s1_agent_m0_debugaccess),                       //  output,    width = 1,                .debugaccess
		.m0_lock                 (button_pio_s1_agent_m0_lock),                              //  output,    width = 1,                .lock
		.m0_readdata             (button_pio_s1_agent_m0_readdata),                          //   input,   width = 32,                .readdata
		.m0_readdatavalid        (button_pio_s1_agent_m0_readdatavalid),                     //   input,    width = 1,                .readdatavalid
		.m0_read                 (button_pio_s1_agent_m0_read),                              //  output,    width = 1,                .read
		.m0_waitrequest          (button_pio_s1_agent_m0_waitrequest),                       //   input,    width = 1,                .waitrequest
		.m0_writedata            (button_pio_s1_agent_m0_writedata),                         //  output,   width = 32,                .writedata
		.m0_write                (button_pio_s1_agent_m0_write),                             //  output,    width = 1,                .write
		.rp_endofpacket          (button_pio_s1_agent_rp_endofpacket),                       //  output,    width = 1,              rp.endofpacket
		.rp_ready                (button_pio_s1_agent_rp_ready),                             //   input,    width = 1,                .ready
		.rp_valid                (button_pio_s1_agent_rp_valid),                             //  output,    width = 1,                .valid
		.rp_data                 (button_pio_s1_agent_rp_data),                              //  output,  width = 143,                .data
		.rp_startofpacket        (button_pio_s1_agent_rp_startofpacket),                     //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_003_src_ready),                                    //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_003_src_valid),                                    //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_003_src_data),                                     //   input,  width = 143,                .data
		.cp_startofpacket        (cmd_mux_003_src_startofpacket),                            //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                              //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_003_src_channel),                                  //   input,    width = 4,                .channel
		.rf_sink_ready           (button_pio_s1_agent_rsp_fifo_out_ready),                   //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (button_pio_s1_agent_rsp_fifo_out_valid),                   //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (button_pio_s1_agent_rsp_fifo_out_startofpacket),           //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (button_pio_s1_agent_rsp_fifo_out_endofpacket),             //   input,    width = 1,                .endofpacket
		.rf_sink_data            (button_pio_s1_agent_rsp_fifo_out_data),                    //   input,  width = 144,                .data
		.rf_source_ready         (button_pio_s1_agent_rf_source_ready),                      //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (button_pio_s1_agent_rf_source_valid),                      //  output,    width = 1,                .valid
		.rf_source_startofpacket (button_pio_s1_agent_rf_source_startofpacket),              //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (button_pio_s1_agent_rf_source_endofpacket),                //  output,    width = 1,                .endofpacket
		.rf_source_data          (button_pio_s1_agent_rf_source_data),                       //  output,  width = 144,                .data
		.rdata_fifo_sink_ready   (button_pio_s1_agent_rdata_fifo_src_ready),                 //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (button_pio_s1_agent_rdata_fifo_src_valid),                 //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (button_pio_s1_agent_rdata_fifo_src_data),                  //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (button_pio_s1_agent_rdata_fifo_src_ready),                 //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (button_pio_s1_agent_rdata_fifo_src_valid),                 //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (button_pio_s1_agent_rdata_fifo_src_data),                  //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                    // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                     // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                      // (terminated),                               
	);

	peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (144),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) button_pio_s1_agent_rsp_fifo (
		.clk               (periph_clk_out_clk_clk),                         //   input,    width = 1,       clk.clk
		.reset             (pb_cpu_0_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.in_data           (button_pio_s1_agent_rf_source_data),             //   input,  width = 144,        in.data
		.in_valid          (button_pio_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (button_pio_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (button_pio_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (button_pio_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (button_pio_s1_agent_rsp_fifo_out_data),          //  output,  width = 144,       out.data
		.out_valid         (button_pio_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (button_pio_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (button_pio_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (button_pio_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                          // (terminated),                         
		.csr_read          (1'b0),                                           // (terminated),                         
		.csr_write         (1'b0),                                           // (terminated),                         
		.csr_readdata      (),                                               // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),           // (terminated),                         
		.almost_full_data  (),                                               // (terminated),                         
		.almost_empty_data (),                                               // (terminated),                         
		.in_empty          (1'b0),                                           // (terminated),                         
		.out_empty         (),                                               // (terminated),                         
		.in_error          (1'b0),                                           // (terminated),                         
		.out_error         (),                                               // (terminated),                         
		.in_channel        (1'b0),                                           // (terminated),                         
		.out_channel       ()                                                // (terminated),                         
	);

	peripheral_subsys_altera_merlin_router_1921_iesulwy router (
		.sink_ready         (pb_cpu_0_m0_agent_cp_ready),                               //  output,    width = 1,      sink.ready
		.sink_valid         (pb_cpu_0_m0_agent_cp_valid),                               //   input,    width = 1,          .valid
		.sink_data          (pb_cpu_0_m0_agent_cp_data),                                //   input,  width = 143,          .data
		.sink_startofpacket (pb_cpu_0_m0_agent_cp_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (pb_cpu_0_m0_agent_cp_endofpacket),                         //   input,    width = 1,          .endofpacket
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                         //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                          //  output,  width = 143,          .data
		.src_channel        (router_src_channel),                                       //  output,    width = 4,          .channel
		.src_startofpacket  (router_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                    //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_router_1921_wxl7gvy router_001 (
		.sink_ready         (sysid_control_slave_agent_rp_ready),                       //  output,    width = 1,      sink.ready
		.sink_valid         (sysid_control_slave_agent_rp_valid),                       //   input,    width = 1,          .valid
		.sink_data          (sysid_control_slave_agent_rp_data),                        //   input,  width = 143,          .data
		.sink_startofpacket (sysid_control_slave_agent_rp_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sysid_control_slave_agent_rp_endofpacket),                 //   input,    width = 1,          .endofpacket
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                     //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                     //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                      //  output,  width = 143,          .data
		.src_channel        (router_001_src_channel),                                   //  output,    width = 4,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                             //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_router_1921_wxl7gvy router_002 (
		.sink_ready         (led_pio_s1_agent_rp_ready),                                //  output,    width = 1,      sink.ready
		.sink_valid         (led_pio_s1_agent_rp_valid),                                //   input,    width = 1,          .valid
		.sink_data          (led_pio_s1_agent_rp_data),                                 //   input,  width = 143,          .data
		.sink_startofpacket (led_pio_s1_agent_rp_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (led_pio_s1_agent_rp_endofpacket),                          //   input,    width = 1,          .endofpacket
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                     //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                     //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                      //  output,  width = 143,          .data
		.src_channel        (router_002_src_channel),                                   //  output,    width = 4,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                             //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_router_1921_wxl7gvy router_003 (
		.sink_ready         (dipsw_pio_s1_agent_rp_ready),                              //  output,    width = 1,      sink.ready
		.sink_valid         (dipsw_pio_s1_agent_rp_valid),                              //   input,    width = 1,          .valid
		.sink_data          (dipsw_pio_s1_agent_rp_data),                               //   input,  width = 143,          .data
		.sink_startofpacket (dipsw_pio_s1_agent_rp_startofpacket),                      //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (dipsw_pio_s1_agent_rp_endofpacket),                        //   input,    width = 1,          .endofpacket
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_003_src_ready),                                     //   input,    width = 1,       src.ready
		.src_valid          (router_003_src_valid),                                     //  output,    width = 1,          .valid
		.src_data           (router_003_src_data),                                      //  output,  width = 143,          .data
		.src_channel        (router_003_src_channel),                                   //  output,    width = 4,          .channel
		.src_startofpacket  (router_003_src_startofpacket),                             //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                                //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_router_1921_wxl7gvy router_004 (
		.sink_ready         (button_pio_s1_agent_rp_ready),                             //  output,    width = 1,      sink.ready
		.sink_valid         (button_pio_s1_agent_rp_valid),                             //   input,    width = 1,          .valid
		.sink_data          (button_pio_s1_agent_rp_data),                              //   input,  width = 143,          .data
		.sink_startofpacket (button_pio_s1_agent_rp_startofpacket),                     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (button_pio_s1_agent_rp_endofpacket),                       //   input,    width = 1,          .endofpacket
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_004_src_ready),                                     //   input,    width = 1,       src.ready
		.src_valid          (router_004_src_valid),                                     //  output,    width = 1,          .valid
		.src_data           (router_004_src_data),                                      //  output,  width = 143,          .data
		.src_channel        (router_004_src_channel),                                   //  output,    width = 4,          .channel
		.src_startofpacket  (router_004_src_startofpacket),                             //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                                //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_traffic_limiter_1921_p3fvlba #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (75),
		.PKT_DEST_ID_L                        (74),
		.PKT_SRC_ID_H                         (73),
		.PKT_SRC_ID_L                         (72),
		.PKT_BYTE_CNT_H                       (61),
		.PKT_BYTE_CNT_L                       (59),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (54),
		.PKT_TRANS_WRITE                      (55),
		.PKT_TRANS_SEQ_H                      (112),
		.PKT_TRANS_SEQ_L                      (106),
		.MAX_OUTSTANDING_RESPONSES            (2),
		.PIPELINED                            (0),
		.ST_DATA_W                            (143),
		.ST_CHANNEL_W                         (4),
		.VALID_WIDTH                          (4),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) pb_cpu_0_m0_limiter (
		.clk                    (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset                  (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                         //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                         //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                          //   input,  width = 143,          .data
		.cmd_sink_channel       (router_src_channel),                                       //   input,    width = 4,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                   //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (pb_cpu_0_m0_limiter_cmd_src_ready),                        //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (pb_cpu_0_m0_limiter_cmd_src_data),                         //  output,  width = 143,          .data
		.cmd_src_channel        (pb_cpu_0_m0_limiter_cmd_src_channel),                      //  output,    width = 4,          .channel
		.cmd_src_startofpacket  (pb_cpu_0_m0_limiter_cmd_src_startofpacket),                //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (pb_cpu_0_m0_limiter_cmd_src_endofpacket),                  //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                        //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                        //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                      //   input,    width = 4,          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                         //   input,  width = 143,          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                  //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (pb_cpu_0_m0_limiter_rsp_src_ready),                        //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (pb_cpu_0_m0_limiter_rsp_src_valid),                        //  output,    width = 1,          .valid
		.rsp_src_data           (pb_cpu_0_m0_limiter_rsp_src_data),                         //  output,  width = 143,          .data
		.rsp_src_channel        (pb_cpu_0_m0_limiter_rsp_src_channel),                      //  output,    width = 4,          .channel
		.rsp_src_startofpacket  (pb_cpu_0_m0_limiter_rsp_src_startofpacket),                //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (pb_cpu_0_m0_limiter_rsp_src_endofpacket),                  //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (pb_cpu_0_m0_limiter_cmd_valid_data)                        //  output,    width = 4, cmd_valid.data
	);

	peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi cmd_demux (
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,        clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,  clk_reset.reset
		.sink_ready         (pb_cpu_0_m0_limiter_cmd_src_ready),                        //  output,    width = 1,       sink.ready
		.sink_channel       (pb_cpu_0_m0_limiter_cmd_src_channel),                      //   input,    width = 4,           .channel
		.sink_data          (pb_cpu_0_m0_limiter_cmd_src_data),                         //   input,  width = 143,           .data
		.sink_startofpacket (pb_cpu_0_m0_limiter_cmd_src_startofpacket),                //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (pb_cpu_0_m0_limiter_cmd_src_endofpacket),                  //   input,    width = 1,           .endofpacket
		.sink_valid         (pb_cpu_0_m0_limiter_cmd_valid_data),                       //   input,    width = 4, sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                     //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                     //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_src0_data),                                      //  output,  width = 143,           .data
		.src0_channel       (cmd_demux_src0_channel),                                   //  output,    width = 4,           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                               //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                     //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                     //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_src1_data),                                      //  output,  width = 143,           .data
		.src1_channel       (cmd_demux_src1_channel),                                   //  output,    width = 4,           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),                               //  output,    width = 1,           .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                                     //   input,    width = 1,       src2.ready
		.src2_valid         (cmd_demux_src2_valid),                                     //  output,    width = 1,           .valid
		.src2_data          (cmd_demux_src2_data),                                      //  output,  width = 143,           .data
		.src2_channel       (cmd_demux_src2_channel),                                   //  output,    width = 4,           .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket),                               //  output,    width = 1,           .endofpacket
		.src3_ready         (cmd_demux_src3_ready),                                     //   input,    width = 1,       src3.ready
		.src3_valid         (cmd_demux_src3_valid),                                     //  output,    width = 1,           .valid
		.src3_data          (cmd_demux_src3_data),                                      //  output,  width = 143,           .data
		.src3_channel       (cmd_demux_src3_channel),                                   //  output,    width = 4,           .channel
		.src3_startofpacket (cmd_demux_src3_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src3_endofpacket   (cmd_demux_src3_endofpacket)                                //  output,    width = 1,           .endofpacket
	);

	peripheral_subsys_altera_merlin_multiplexer_1922_ufdjdoq cmd_mux (
		.clk                 (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                        //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                        //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                         //  output,  width = 143,          .data
		.src_channel         (cmd_mux_src_channel),                                      //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                  //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                     //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                     //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                   //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src0_data),                                      //   input,  width = 143,          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                                //   input,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_multiplexer_1922_ufdjdoq cmd_mux_001 (
		.clk                 (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                    //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                    //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                                     //  output,  width = 143,          .data
		.src_channel         (cmd_mux_001_src_channel),                                  //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                            //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                              //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                                     //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                                     //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src1_channel),                                   //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src1_data),                                      //   input,  width = 143,          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                                //   input,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_multiplexer_1922_ufdjdoq cmd_mux_002 (
		.clk                 (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                                    //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_002_src_valid),                                    //  output,    width = 1,          .valid
		.src_data            (cmd_mux_002_src_data),                                     //  output,  width = 143,          .data
		.src_channel         (cmd_mux_002_src_channel),                                  //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                            //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                              //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                                     //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                                     //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src2_channel),                                   //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src2_data),                                      //   input,  width = 143,          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket)                                //   input,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_multiplexer_1922_ufdjdoq cmd_mux_003 (
		.clk                 (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                                    //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_003_src_valid),                                    //  output,    width = 1,          .valid
		.src_data            (cmd_mux_003_src_data),                                     //  output,  width = 143,          .data
		.src_channel         (cmd_mux_003_src_channel),                                  //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                            //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                              //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src3_ready),                                     //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src3_valid),                                     //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src3_channel),                                   //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src3_data),                                      //   input,  width = 143,          .data
		.sink0_startofpacket (cmd_demux_src3_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src3_endofpacket)                                //   input,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_demultiplexer_1921_4xqokvi rsp_demux (
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                                     //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                                   //   input,    width = 4,          .channel
		.sink_data          (router_001_src_data),                                      //   input,  width = 143,          .data
		.sink_startofpacket (router_001_src_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                               //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                                     //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                     //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                     //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                      //  output,  width = 143,          .data
		.src0_channel       (rsp_demux_src0_channel),                                   //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                             //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_demultiplexer_1921_4xqokvi rsp_demux_001 (
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_002_src_ready),                                     //  output,    width = 1,      sink.ready
		.sink_channel       (router_002_src_channel),                                   //   input,    width = 4,          .channel
		.sink_data          (router_002_src_data),                                      //   input,  width = 143,          .data
		.sink_startofpacket (router_002_src_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                               //   input,    width = 1,          .endofpacket
		.sink_valid         (router_002_src_valid),                                     //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                                 //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                                 //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                                  //  output,  width = 143,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                               //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                         //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                            //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_demultiplexer_1921_4xqokvi rsp_demux_002 (
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_003_src_ready),                                     //  output,    width = 1,      sink.ready
		.sink_channel       (router_003_src_channel),                                   //   input,    width = 4,          .channel
		.sink_data          (router_003_src_data),                                      //   input,  width = 143,          .data
		.sink_startofpacket (router_003_src_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                               //   input,    width = 1,          .endofpacket
		.sink_valid         (router_003_src_valid),                                     //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                                 //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                                 //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_002_src0_data),                                  //  output,  width = 143,          .data
		.src0_channel       (rsp_demux_002_src0_channel),                               //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                         //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                            //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_demultiplexer_1921_4xqokvi rsp_demux_003 (
		.clk                (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_004_src_ready),                                     //  output,    width = 1,      sink.ready
		.sink_channel       (router_004_src_channel),                                   //   input,    width = 4,          .channel
		.sink_data          (router_004_src_data),                                      //   input,  width = 143,          .data
		.sink_startofpacket (router_004_src_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                               //   input,    width = 1,          .endofpacket
		.sink_valid         (router_004_src_valid),                                     //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                                 //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                                 //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_003_src0_data),                                  //  output,  width = 143,          .data
		.src0_channel       (rsp_demux_003_src0_channel),                               //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                         //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)                            //  output,    width = 1,          .endofpacket
	);

	peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq rsp_mux (
		.clk                 (periph_clk_out_clk_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                        //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                        //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                         //  output,  width = 143,          .data
		.src_channel         (rsp_mux_src_channel),                                      //  output,    width = 4,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                  //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                     //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                     //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                   //   input,    width = 4,          .channel
		.sink0_data          (rsp_demux_src0_data),                                      //   input,  width = 143,          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                               //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                                 //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                               //   input,    width = 4,          .channel
		.sink1_data          (rsp_demux_001_src0_data),                                  //   input,  width = 143,          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                           //   input,    width = 1,          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                                 //  output,    width = 1,     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                                 //   input,    width = 1,          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),                               //   input,    width = 4,          .channel
		.sink2_data          (rsp_demux_002_src0_data),                                  //   input,  width = 143,          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                         //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),                           //   input,    width = 1,          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),                                 //  output,    width = 1,     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),                                 //   input,    width = 1,          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),                               //   input,    width = 4,          .channel
		.sink3_data          (rsp_demux_003_src0_data),                                  //   input,  width = 143,          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),                         //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket)                            //   input,    width = 1,          .endofpacket
	);

endmodule
