// qsys_top_altera_mm_interconnect_1920_6wkpj2i.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.3.1 100

`timescale 1 ps / 1 ps
module qsys_top_altera_mm_interconnect_1920_6wkpj2i (
		input  wire [3:0]  subsys_hps_lwhps2fpga_awid,                                                     //                                                    subsys_hps_lwhps2fpga.awid
		input  wire [28:0] subsys_hps_lwhps2fpga_awaddr,                                                   //                                                                         .awaddr
		input  wire [7:0]  subsys_hps_lwhps2fpga_awlen,                                                    //                                                                         .awlen
		input  wire [2:0]  subsys_hps_lwhps2fpga_awsize,                                                   //                                                                         .awsize
		input  wire [1:0]  subsys_hps_lwhps2fpga_awburst,                                                  //                                                                         .awburst
		input  wire [0:0]  subsys_hps_lwhps2fpga_awlock,                                                   //                                                                         .awlock
		input  wire [3:0]  subsys_hps_lwhps2fpga_awcache,                                                  //                                                                         .awcache
		input  wire [2:0]  subsys_hps_lwhps2fpga_awprot,                                                   //                                                                         .awprot
		input  wire        subsys_hps_lwhps2fpga_awvalid,                                                  //                                                                         .awvalid
		output wire        subsys_hps_lwhps2fpga_awready,                                                  //                                                                         .awready
		input  wire [31:0] subsys_hps_lwhps2fpga_wdata,                                                    //                                                                         .wdata
		input  wire [3:0]  subsys_hps_lwhps2fpga_wstrb,                                                    //                                                                         .wstrb
		input  wire        subsys_hps_lwhps2fpga_wlast,                                                    //                                                                         .wlast
		input  wire        subsys_hps_lwhps2fpga_wvalid,                                                   //                                                                         .wvalid
		output wire        subsys_hps_lwhps2fpga_wready,                                                   //                                                                         .wready
		output wire [3:0]  subsys_hps_lwhps2fpga_bid,                                                      //                                                                         .bid
		output wire [1:0]  subsys_hps_lwhps2fpga_bresp,                                                    //                                                                         .bresp
		output wire        subsys_hps_lwhps2fpga_bvalid,                                                   //                                                                         .bvalid
		input  wire        subsys_hps_lwhps2fpga_bready,                                                   //                                                                         .bready
		input  wire [3:0]  subsys_hps_lwhps2fpga_arid,                                                     //                                                                         .arid
		input  wire [28:0] subsys_hps_lwhps2fpga_araddr,                                                   //                                                                         .araddr
		input  wire [7:0]  subsys_hps_lwhps2fpga_arlen,                                                    //                                                                         .arlen
		input  wire [2:0]  subsys_hps_lwhps2fpga_arsize,                                                   //                                                                         .arsize
		input  wire [1:0]  subsys_hps_lwhps2fpga_arburst,                                                  //                                                                         .arburst
		input  wire [0:0]  subsys_hps_lwhps2fpga_arlock,                                                   //                                                                         .arlock
		input  wire [3:0]  subsys_hps_lwhps2fpga_arcache,                                                  //                                                                         .arcache
		input  wire [2:0]  subsys_hps_lwhps2fpga_arprot,                                                   //                                                                         .arprot
		input  wire        subsys_hps_lwhps2fpga_arvalid,                                                  //                                                                         .arvalid
		output wire        subsys_hps_lwhps2fpga_arready,                                                  //                                                                         .arready
		output wire [3:0]  subsys_hps_lwhps2fpga_rid,                                                      //                                                                         .rid
		output wire [31:0] subsys_hps_lwhps2fpga_rdata,                                                    //                                                                         .rdata
		output wire [1:0]  subsys_hps_lwhps2fpga_rresp,                                                    //                                                                         .rresp
		output wire        subsys_hps_lwhps2fpga_rlast,                                                    //                                                                         .rlast
		output wire        subsys_hps_lwhps2fpga_rvalid,                                                   //                                                                         .rvalid
		input  wire        subsys_hps_lwhps2fpga_rready,                                                   //                                                                         .rready
		output wire [16:0] subsys_periph_pb_cpu_0_s0_address,                                              //                                                subsys_periph_pb_cpu_0_s0.address
		output wire        subsys_periph_pb_cpu_0_s0_write,                                                //                                                                         .write
		output wire        subsys_periph_pb_cpu_0_s0_read,                                                 //                                                                         .read
		input  wire [31:0] subsys_periph_pb_cpu_0_s0_readdata,                                             //                                                                         .readdata
		output wire [31:0] subsys_periph_pb_cpu_0_s0_writedata,                                            //                                                                         .writedata
		output wire [0:0]  subsys_periph_pb_cpu_0_s0_burstcount,                                           //                                                                         .burstcount
		output wire [3:0]  subsys_periph_pb_cpu_0_s0_byteenable,                                           //                                                                         .byteenable
		input  wire        subsys_periph_pb_cpu_0_s0_readdatavalid,                                        //                                                                         .readdatavalid
		input  wire        subsys_periph_pb_cpu_0_s0_waitrequest,                                          //                                                                         .waitrequest
		output wire        subsys_periph_pb_cpu_0_s0_debugaccess,                                          //                                                                         .debugaccess
		input  wire        subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset,         //         subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset, // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        clk_100_out_clk_clk                                                             //                                                          clk_100_out_clk.clk,          Clock Input
	);

	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_ruser;                     // subsys_hps_lwhps2fpga_agent:ruser -> subsys_hps_lwhps2fpga_translator:m0_ruser
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_wuser;                     // subsys_hps_lwhps2fpga_translator:m0_wuser -> subsys_hps_lwhps2fpga_agent:wuser
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_awburst;                   // subsys_hps_lwhps2fpga_translator:m0_awburst -> subsys_hps_lwhps2fpga_agent:awburst
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arregion;                  // subsys_hps_lwhps2fpga_translator:m0_arregion -> subsys_hps_lwhps2fpga_agent:arregion
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_awuser;                    // subsys_hps_lwhps2fpga_translator:m0_awuser -> subsys_hps_lwhps2fpga_agent:awuser
	wire    [7:0] subsys_hps_lwhps2fpga_translator_m0_arlen;                     // subsys_hps_lwhps2fpga_translator:m0_arlen -> subsys_hps_lwhps2fpga_agent:arlen
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arqos;                     // subsys_hps_lwhps2fpga_translator:m0_arqos -> subsys_hps_lwhps2fpga_agent:arqos
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_wstrb;                     // subsys_hps_lwhps2fpga_translator:m0_wstrb -> subsys_hps_lwhps2fpga_agent:wstrb
	wire          subsys_hps_lwhps2fpga_translator_m0_wready;                    // subsys_hps_lwhps2fpga_agent:wready -> subsys_hps_lwhps2fpga_translator:m0_wready
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_rid;                       // subsys_hps_lwhps2fpga_agent:rid -> subsys_hps_lwhps2fpga_translator:m0_rid
	wire          subsys_hps_lwhps2fpga_translator_m0_rready;                    // subsys_hps_lwhps2fpga_translator:m0_rready -> subsys_hps_lwhps2fpga_agent:rready
	wire    [7:0] subsys_hps_lwhps2fpga_translator_m0_awlen;                     // subsys_hps_lwhps2fpga_translator:m0_awlen -> subsys_hps_lwhps2fpga_agent:awlen
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awqos;                     // subsys_hps_lwhps2fpga_translator:m0_awqos -> subsys_hps_lwhps2fpga_agent:awqos
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arcache;                   // subsys_hps_lwhps2fpga_translator:m0_arcache -> subsys_hps_lwhps2fpga_agent:arcache
	wire          subsys_hps_lwhps2fpga_translator_m0_wvalid;                    // subsys_hps_lwhps2fpga_translator:m0_wvalid -> subsys_hps_lwhps2fpga_agent:wvalid
	wire   [28:0] subsys_hps_lwhps2fpga_translator_m0_araddr;                    // subsys_hps_lwhps2fpga_translator:m0_araddr -> subsys_hps_lwhps2fpga_agent:araddr
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_arprot;                    // subsys_hps_lwhps2fpga_translator:m0_arprot -> subsys_hps_lwhps2fpga_agent:arprot
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_awprot;                    // subsys_hps_lwhps2fpga_translator:m0_awprot -> subsys_hps_lwhps2fpga_agent:awprot
	wire   [31:0] subsys_hps_lwhps2fpga_translator_m0_wdata;                     // subsys_hps_lwhps2fpga_translator:m0_wdata -> subsys_hps_lwhps2fpga_agent:wdata
	wire          subsys_hps_lwhps2fpga_translator_m0_arvalid;                   // subsys_hps_lwhps2fpga_translator:m0_arvalid -> subsys_hps_lwhps2fpga_agent:arvalid
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awcache;                   // subsys_hps_lwhps2fpga_translator:m0_awcache -> subsys_hps_lwhps2fpga_agent:awcache
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arid;                      // subsys_hps_lwhps2fpga_translator:m0_arid -> subsys_hps_lwhps2fpga_agent:arid
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_arlock;                    // subsys_hps_lwhps2fpga_translator:m0_arlock -> subsys_hps_lwhps2fpga_agent:arlock
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_awlock;                    // subsys_hps_lwhps2fpga_translator:m0_awlock -> subsys_hps_lwhps2fpga_agent:awlock
	wire   [28:0] subsys_hps_lwhps2fpga_translator_m0_awaddr;                    // subsys_hps_lwhps2fpga_translator:m0_awaddr -> subsys_hps_lwhps2fpga_agent:awaddr
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_bresp;                     // subsys_hps_lwhps2fpga_agent:bresp -> subsys_hps_lwhps2fpga_translator:m0_bresp
	wire          subsys_hps_lwhps2fpga_translator_m0_arready;                   // subsys_hps_lwhps2fpga_agent:arready -> subsys_hps_lwhps2fpga_translator:m0_arready
	wire   [31:0] subsys_hps_lwhps2fpga_translator_m0_rdata;                     // subsys_hps_lwhps2fpga_agent:rdata -> subsys_hps_lwhps2fpga_translator:m0_rdata
	wire          subsys_hps_lwhps2fpga_translator_m0_awready;                   // subsys_hps_lwhps2fpga_agent:awready -> subsys_hps_lwhps2fpga_translator:m0_awready
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_arburst;                   // subsys_hps_lwhps2fpga_translator:m0_arburst -> subsys_hps_lwhps2fpga_agent:arburst
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_arsize;                    // subsys_hps_lwhps2fpga_translator:m0_arsize -> subsys_hps_lwhps2fpga_agent:arsize
	wire          subsys_hps_lwhps2fpga_translator_m0_bready;                    // subsys_hps_lwhps2fpga_translator:m0_bready -> subsys_hps_lwhps2fpga_agent:bready
	wire          subsys_hps_lwhps2fpga_translator_m0_rlast;                     // subsys_hps_lwhps2fpga_agent:rlast -> subsys_hps_lwhps2fpga_translator:m0_rlast
	wire          subsys_hps_lwhps2fpga_translator_m0_wlast;                     // subsys_hps_lwhps2fpga_translator:m0_wlast -> subsys_hps_lwhps2fpga_agent:wlast
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awregion;                  // subsys_hps_lwhps2fpga_translator:m0_awregion -> subsys_hps_lwhps2fpga_agent:awregion
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_buser;                     // subsys_hps_lwhps2fpga_agent:buser -> subsys_hps_lwhps2fpga_translator:m0_buser
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_rresp;                     // subsys_hps_lwhps2fpga_agent:rresp -> subsys_hps_lwhps2fpga_translator:m0_rresp
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awid;                      // subsys_hps_lwhps2fpga_translator:m0_awid -> subsys_hps_lwhps2fpga_agent:awid
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_bid;                       // subsys_hps_lwhps2fpga_agent:bid -> subsys_hps_lwhps2fpga_translator:m0_bid
	wire          subsys_hps_lwhps2fpga_translator_m0_bvalid;                    // subsys_hps_lwhps2fpga_agent:bvalid -> subsys_hps_lwhps2fpga_translator:m0_bvalid
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_awsize;                    // subsys_hps_lwhps2fpga_translator:m0_awsize -> subsys_hps_lwhps2fpga_agent:awsize
	wire          subsys_hps_lwhps2fpga_translator_m0_awvalid;                   // subsys_hps_lwhps2fpga_translator:m0_awvalid -> subsys_hps_lwhps2fpga_agent:awvalid
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_aruser;                    // subsys_hps_lwhps2fpga_translator:m0_aruser -> subsys_hps_lwhps2fpga_agent:aruser
	wire          subsys_hps_lwhps2fpga_translator_m0_rvalid;                    // subsys_hps_lwhps2fpga_agent:rvalid -> subsys_hps_lwhps2fpga_translator:m0_rvalid
	wire          rsp_mux_src_valid;                                             // rsp_mux:src_valid -> subsys_hps_lwhps2fpga_agent:write_rp_valid
	wire  [170:0] rsp_mux_src_data;                                              // rsp_mux:src_data -> subsys_hps_lwhps2fpga_agent:write_rp_data
	wire          rsp_mux_src_ready;                                             // subsys_hps_lwhps2fpga_agent:write_rp_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                           // rsp_mux:src_channel -> subsys_hps_lwhps2fpga_agent:write_rp_channel
	wire          rsp_mux_src_startofpacket;                                     // rsp_mux:src_startofpacket -> subsys_hps_lwhps2fpga_agent:write_rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                       // rsp_mux:src_endofpacket -> subsys_hps_lwhps2fpga_agent:write_rp_endofpacket
	wire          rsp_mux_001_src_valid;                                         // rsp_mux_001:src_valid -> subsys_hps_lwhps2fpga_agent:read_rp_valid
	wire  [170:0] rsp_mux_001_src_data;                                          // rsp_mux_001:src_data -> subsys_hps_lwhps2fpga_agent:read_rp_data
	wire          rsp_mux_001_src_ready;                                         // subsys_hps_lwhps2fpga_agent:read_rp_ready -> rsp_mux_001:src_ready
	wire    [1:0] rsp_mux_001_src_channel;                                       // rsp_mux_001:src_channel -> subsys_hps_lwhps2fpga_agent:read_rp_channel
	wire          rsp_mux_001_src_startofpacket;                                 // rsp_mux_001:src_startofpacket -> subsys_hps_lwhps2fpga_agent:read_rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                   // rsp_mux_001:src_endofpacket -> subsys_hps_lwhps2fpga_agent:read_rp_endofpacket
	wire   [31:0] subsys_periph_pb_cpu_0_s0_agent_m0_readdata;                   // subsys_periph_pb_cpu_0_s0_translator:uav_readdata -> subsys_periph_pb_cpu_0_s0_agent:m0_readdata
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_waitrequest;                // subsys_periph_pb_cpu_0_s0_translator:uav_waitrequest -> subsys_periph_pb_cpu_0_s0_agent:m0_waitrequest
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_debugaccess;                // subsys_periph_pb_cpu_0_s0_agent:m0_debugaccess -> subsys_periph_pb_cpu_0_s0_translator:uav_debugaccess
	wire   [28:0] subsys_periph_pb_cpu_0_s0_agent_m0_address;                    // subsys_periph_pb_cpu_0_s0_agent:m0_address -> subsys_periph_pb_cpu_0_s0_translator:uav_address
	wire    [3:0] subsys_periph_pb_cpu_0_s0_agent_m0_byteenable;                 // subsys_periph_pb_cpu_0_s0_agent:m0_byteenable -> subsys_periph_pb_cpu_0_s0_translator:uav_byteenable
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_read;                       // subsys_periph_pb_cpu_0_s0_agent:m0_read -> subsys_periph_pb_cpu_0_s0_translator:uav_read
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_readdatavalid;              // subsys_periph_pb_cpu_0_s0_translator:uav_readdatavalid -> subsys_periph_pb_cpu_0_s0_agent:m0_readdatavalid
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_lock;                       // subsys_periph_pb_cpu_0_s0_agent:m0_lock -> subsys_periph_pb_cpu_0_s0_translator:uav_lock
	wire   [31:0] subsys_periph_pb_cpu_0_s0_agent_m0_writedata;                  // subsys_periph_pb_cpu_0_s0_agent:m0_writedata -> subsys_periph_pb_cpu_0_s0_translator:uav_writedata
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_write;                      // subsys_periph_pb_cpu_0_s0_agent:m0_write -> subsys_periph_pb_cpu_0_s0_translator:uav_write
	wire    [2:0] subsys_periph_pb_cpu_0_s0_agent_m0_burstcount;                 // subsys_periph_pb_cpu_0_s0_agent:m0_burstcount -> subsys_periph_pb_cpu_0_s0_translator:uav_burstcount
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_valid;               // subsys_periph_pb_cpu_0_s0_agent:rf_source_valid -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_valid
	wire  [171:0] subsys_periph_pb_cpu_0_s0_agent_rf_source_data;                // subsys_periph_pb_cpu_0_s0_agent:rf_source_data -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_ready;               // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_ready -> subsys_periph_pb_cpu_0_s0_agent:rf_source_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_startofpacket;       // subsys_periph_pb_cpu_0_s0_agent:rf_source_startofpacket -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_endofpacket;         // subsys_periph_pb_cpu_0_s0_agent:rf_source_endofpacket -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_valid;            // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_valid -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_valid
	wire  [171:0] subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_data;             // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_data -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_ready;            // subsys_periph_pb_cpu_0_s0_agent:rf_sink_ready -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_startofpacket;    // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_startofpacket -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_endofpacket;      // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_endofpacket -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_valid;          // subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_src_valid -> subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:in_valid
	wire   [33:0] subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_data;           // subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_src_data -> subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:in_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_ready;          // subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:in_ready -> subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_src_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_valid;          // subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:out_valid -> subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_data;           // subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:out_data -> subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_sink_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_ready;          // subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_sink_ready -> subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:out_ready
	wire          subsys_hps_lwhps2fpga_agent_write_cp_valid;                    // subsys_hps_lwhps2fpga_agent:write_cp_valid -> router:sink_valid
	wire  [170:0] subsys_hps_lwhps2fpga_agent_write_cp_data;                     // subsys_hps_lwhps2fpga_agent:write_cp_data -> router:sink_data
	wire          subsys_hps_lwhps2fpga_agent_write_cp_ready;                    // router:sink_ready -> subsys_hps_lwhps2fpga_agent:write_cp_ready
	wire          subsys_hps_lwhps2fpga_agent_write_cp_startofpacket;            // subsys_hps_lwhps2fpga_agent:write_cp_startofpacket -> router:sink_startofpacket
	wire          subsys_hps_lwhps2fpga_agent_write_cp_endofpacket;              // subsys_hps_lwhps2fpga_agent:write_cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                              // router:src_valid -> cmd_demux:sink_valid
	wire  [170:0] router_src_data;                                               // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                              // cmd_demux:sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                            // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                      // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                        // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          subsys_hps_lwhps2fpga_agent_read_cp_valid;                     // subsys_hps_lwhps2fpga_agent:read_cp_valid -> router_001:sink_valid
	wire  [170:0] subsys_hps_lwhps2fpga_agent_read_cp_data;                      // subsys_hps_lwhps2fpga_agent:read_cp_data -> router_001:sink_data
	wire          subsys_hps_lwhps2fpga_agent_read_cp_ready;                     // router_001:sink_ready -> subsys_hps_lwhps2fpga_agent:read_cp_ready
	wire          subsys_hps_lwhps2fpga_agent_read_cp_startofpacket;             // subsys_hps_lwhps2fpga_agent:read_cp_startofpacket -> router_001:sink_startofpacket
	wire          subsys_hps_lwhps2fpga_agent_read_cp_endofpacket;               // subsys_hps_lwhps2fpga_agent:read_cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                          // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [170:0] router_001_src_data;                                           // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                          // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                        // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                  // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                    // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          router_002_src_valid;                                          // router_002:src_valid -> rsp_demux:sink_valid
	wire  [170:0] router_002_src_data;                                           // router_002:src_data -> rsp_demux:sink_data
	wire          router_002_src_ready;                                          // rsp_demux:sink_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                        // router_002:src_channel -> rsp_demux:sink_channel
	wire          router_002_src_startofpacket;                                  // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_002_src_endofpacket;                                    // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_mux_src_valid;                                             // cmd_mux:src_valid -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_valid
	wire  [170:0] cmd_mux_src_data;                                              // cmd_mux:src_data -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                             // subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                           // cmd_mux:src_channel -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                     // cmd_mux:src_startofpacket -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                       // cmd_mux:src_endofpacket -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_valid;         // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_valid -> agent_pipeline:in_valid
	wire  [170:0] subsys_periph_pb_cpu_0_s0_burst_adapter_source0_data;          // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_data -> agent_pipeline:in_data
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_ready;         // agent_pipeline:in_ready -> subsys_periph_pb_cpu_0_s0_burst_adapter:source0_ready
	wire    [1:0] subsys_periph_pb_cpu_0_s0_burst_adapter_source0_channel;       // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_channel -> agent_pipeline:in_channel
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_startofpacket; // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_startofpacket -> agent_pipeline:in_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_endofpacket;   // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_endofpacket -> agent_pipeline:in_endofpacket
	wire          agent_pipeline_source0_valid;                                  // agent_pipeline:out_valid -> subsys_periph_pb_cpu_0_s0_agent:cp_valid
	wire  [170:0] agent_pipeline_source0_data;                                   // agent_pipeline:out_data -> subsys_periph_pb_cpu_0_s0_agent:cp_data
	wire          agent_pipeline_source0_ready;                                  // subsys_periph_pb_cpu_0_s0_agent:cp_ready -> agent_pipeline:out_ready
	wire    [1:0] agent_pipeline_source0_channel;                                // agent_pipeline:out_channel -> subsys_periph_pb_cpu_0_s0_agent:cp_channel
	wire          agent_pipeline_source0_startofpacket;                          // agent_pipeline:out_startofpacket -> subsys_periph_pb_cpu_0_s0_agent:cp_startofpacket
	wire          agent_pipeline_source0_endofpacket;                            // agent_pipeline:out_endofpacket -> subsys_periph_pb_cpu_0_s0_agent:cp_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_valid;                      // subsys_periph_pb_cpu_0_s0_agent:rp_valid -> agent_pipeline_001:in_valid
	wire  [170:0] subsys_periph_pb_cpu_0_s0_agent_rp_data;                       // subsys_periph_pb_cpu_0_s0_agent:rp_data -> agent_pipeline_001:in_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_ready;                      // agent_pipeline_001:in_ready -> subsys_periph_pb_cpu_0_s0_agent:rp_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_startofpacket;              // subsys_periph_pb_cpu_0_s0_agent:rp_startofpacket -> agent_pipeline_001:in_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_endofpacket;                // subsys_periph_pb_cpu_0_s0_agent:rp_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          agent_pipeline_001_source0_valid;                              // agent_pipeline_001:out_valid -> router_002:sink_valid
	wire  [170:0] agent_pipeline_001_source0_data;                               // agent_pipeline_001:out_data -> router_002:sink_data
	wire          agent_pipeline_001_source0_ready;                              // router_002:sink_ready -> agent_pipeline_001:out_ready
	wire          agent_pipeline_001_source0_startofpacket;                      // agent_pipeline_001:out_startofpacket -> router_002:sink_startofpacket
	wire          agent_pipeline_001_source0_endofpacket;                        // agent_pipeline_001:out_endofpacket -> router_002:sink_endofpacket
	wire          cmd_demux_src0_valid;                                          // cmd_demux:src0_valid -> mux_pipeline:in_valid
	wire  [170:0] cmd_demux_src0_data;                                           // cmd_demux:src0_data -> mux_pipeline:in_data
	wire          cmd_demux_src0_ready;                                          // mux_pipeline:in_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                        // cmd_demux:src0_channel -> mux_pipeline:in_channel
	wire          cmd_demux_src0_startofpacket;                                  // cmd_demux:src0_startofpacket -> mux_pipeline:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                    // cmd_demux:src0_endofpacket -> mux_pipeline:in_endofpacket
	wire          mux_pipeline_source0_valid;                                    // mux_pipeline:out_valid -> cmd_mux:sink0_valid
	wire  [170:0] mux_pipeline_source0_data;                                     // mux_pipeline:out_data -> cmd_mux:sink0_data
	wire          mux_pipeline_source0_ready;                                    // cmd_mux:sink0_ready -> mux_pipeline:out_ready
	wire    [1:0] mux_pipeline_source0_channel;                                  // mux_pipeline:out_channel -> cmd_mux:sink0_channel
	wire          mux_pipeline_source0_startofpacket;                            // mux_pipeline:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          mux_pipeline_source0_endofpacket;                              // mux_pipeline:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                      // cmd_demux_001:src0_valid -> mux_pipeline_001:in_valid
	wire  [170:0] cmd_demux_001_src0_data;                                       // cmd_demux_001:src0_data -> mux_pipeline_001:in_data
	wire          cmd_demux_001_src0_ready;                                      // mux_pipeline_001:in_ready -> cmd_demux_001:src0_ready
	wire    [1:0] cmd_demux_001_src0_channel;                                    // cmd_demux_001:src0_channel -> mux_pipeline_001:in_channel
	wire          cmd_demux_001_src0_startofpacket;                              // cmd_demux_001:src0_startofpacket -> mux_pipeline_001:in_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                // cmd_demux_001:src0_endofpacket -> mux_pipeline_001:in_endofpacket
	wire          mux_pipeline_001_source0_valid;                                // mux_pipeline_001:out_valid -> cmd_mux:sink1_valid
	wire  [170:0] mux_pipeline_001_source0_data;                                 // mux_pipeline_001:out_data -> cmd_mux:sink1_data
	wire          mux_pipeline_001_source0_ready;                                // cmd_mux:sink1_ready -> mux_pipeline_001:out_ready
	wire    [1:0] mux_pipeline_001_source0_channel;                              // mux_pipeline_001:out_channel -> cmd_mux:sink1_channel
	wire          mux_pipeline_001_source0_startofpacket;                        // mux_pipeline_001:out_startofpacket -> cmd_mux:sink1_startofpacket
	wire          mux_pipeline_001_source0_endofpacket;                          // mux_pipeline_001:out_endofpacket -> cmd_mux:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                          // rsp_demux:src0_valid -> mux_pipeline_002:in_valid
	wire  [170:0] rsp_demux_src0_data;                                           // rsp_demux:src0_data -> mux_pipeline_002:in_data
	wire          rsp_demux_src0_ready;                                          // mux_pipeline_002:in_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                        // rsp_demux:src0_channel -> mux_pipeline_002:in_channel
	wire          rsp_demux_src0_startofpacket;                                  // rsp_demux:src0_startofpacket -> mux_pipeline_002:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                    // rsp_demux:src0_endofpacket -> mux_pipeline_002:in_endofpacket
	wire          mux_pipeline_002_source0_valid;                                // mux_pipeline_002:out_valid -> rsp_mux:sink0_valid
	wire  [170:0] mux_pipeline_002_source0_data;                                 // mux_pipeline_002:out_data -> rsp_mux:sink0_data
	wire          mux_pipeline_002_source0_ready;                                // rsp_mux:sink0_ready -> mux_pipeline_002:out_ready
	wire    [1:0] mux_pipeline_002_source0_channel;                              // mux_pipeline_002:out_channel -> rsp_mux:sink0_channel
	wire          mux_pipeline_002_source0_startofpacket;                        // mux_pipeline_002:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          mux_pipeline_002_source0_endofpacket;                          // mux_pipeline_002:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                          // rsp_demux:src1_valid -> mux_pipeline_003:in_valid
	wire  [170:0] rsp_demux_src1_data;                                           // rsp_demux:src1_data -> mux_pipeline_003:in_data
	wire          rsp_demux_src1_ready;                                          // mux_pipeline_003:in_ready -> rsp_demux:src1_ready
	wire    [1:0] rsp_demux_src1_channel;                                        // rsp_demux:src1_channel -> mux_pipeline_003:in_channel
	wire          rsp_demux_src1_startofpacket;                                  // rsp_demux:src1_startofpacket -> mux_pipeline_003:in_startofpacket
	wire          rsp_demux_src1_endofpacket;                                    // rsp_demux:src1_endofpacket -> mux_pipeline_003:in_endofpacket
	wire          mux_pipeline_003_source0_valid;                                // mux_pipeline_003:out_valid -> rsp_mux_001:sink0_valid
	wire  [170:0] mux_pipeline_003_source0_data;                                 // mux_pipeline_003:out_data -> rsp_mux_001:sink0_data
	wire          mux_pipeline_003_source0_ready;                                // rsp_mux_001:sink0_ready -> mux_pipeline_003:out_ready
	wire    [1:0] mux_pipeline_003_source0_channel;                              // mux_pipeline_003:out_channel -> rsp_mux_001:sink0_channel
	wire          mux_pipeline_003_source0_startofpacket;                        // mux_pipeline_003:out_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          mux_pipeline_003_source0_endofpacket;                          // mux_pipeline_003:out_endofpacket -> rsp_mux_001:sink0_endofpacket

	qsys_top_altera_merlin_axi_translator_1986_4khp5ei #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.USE_M0_AWUSER_ADDRCHK             (1),
		.USE_M0_AWUSER_SAI                 (1),
		.USE_M0_ARUSER_ADDRCHK             (1),
		.USE_M0_ARUSER_SAI                 (1),
		.USE_M0_WUSER_DATACHK              (1),
		.USE_M0_WUSER_POISON               (1),
		.USE_M0_RUSER_DATACHK              (1),
		.USE_M0_RUSER_POISON               (1),
		.USE_M0_WUSER_DATA                 (1),
		.USE_M0_RUSER_DATA                 (1),
		.USE_M0_AWAKEUP                    (0),
		.USE_M0_WPOISON                    (0),
		.USE_M0_RPOISON                    (0),
		.USE_M0_AWTRACE                    (0),
		.USE_M0_ARTRACE                    (0),
		.USE_M0_WTRACE                     (0),
		.USE_M0_BTRACE                     (0),
		.USE_M0_RTRACE                     (0),
		.USE_M0_WDATACHK                   (0),
		.USE_M0_RDATACHK                   (0),
		.USE_M0_AWUNIQUE                   (1),
		.USE_S0_AWAKEUP                    (0),
		.USE_S0_WPOISON                    (0),
		.USE_S0_RPOISON                    (0),
		.USE_S0_AWTRACE                    (0),
		.USE_S0_ARTRACE                    (0),
		.USE_S0_WTRACE                     (0),
		.USE_S0_BTRACE                     (0),
		.USE_S0_RTRACE                     (0),
		.USE_S0_WDATACHK                   (0),
		.USE_S0_RDATACHK                   (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.USE_S0_AWUNIQUE                   (0),
		.USE_S0_AWATOP                     (0),
		.USE_S0_AWSTASHNID                 (0),
		.USE_S0_AWSTASHNIDEN               (0),
		.USE_S0_AWSTASHLPID                (0),
		.USE_S0_AWSTASHLPIDEN              (0),
		.USE_S0_AWMMUSECSID                (0),
		.USE_S0_AWMMUSID                   (0),
		.USE_S0_ARMMUSECSID                (0),
		.USE_S0_ARMMUSID                   (0),
		.USE_M0_AWATOP                     (0),
		.USE_M0_AWSTASHNID                 (0),
		.USE_M0_AWSTASHNIDEN               (0),
		.USE_M0_AWSTASHLPID                (0),
		.USE_M0_AWSTASHLPIDEN              (0),
		.USE_M0_AWMMUSECSID                (0),
		.USE_M0_AWMMUSID                   (0),
		.USE_M0_ARMMUSECSID                (0),
		.USE_M0_ARMMUSID                   (0),
		.USE_S0_AWSNOOP                    (1),
		.USE_S0_ARSNOOP                    (1),
		.USE_S0_AWADDRCHK                  (0),
		.USE_S0_ARADDRCHK                  (0),
		.USE_M0_AWADDRCHK                  (0),
		.USE_M0_ARADDRCHK                  (0),
		.M0_ID_WIDTH                       (4),
		.DATA_WIDTH                        (32),
		.M0_SAI_WIDTH                      (1),
		.S0_SAI_WIDTH                      (1),
		.USER_DATA_WIDTH                   (1),
		.M0_USER_ADDRCHK_WIDTH             (1),
		.S0_USER_ADDRCHK_WIDTH             (1),
		.S0_ID_WIDTH                       (4),
		.M0_ADDR_WIDTH                     (29),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (29),
		.M0_SID_WIDTH                      (16),
		.S0_SID_WIDTH                      (16),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.M0_AWSNOOP_WIDTH                  (3),
		.S0_AWSNOOP_WIDTH                  (3),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.ACE5_LITE_SUPPORT                 (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) subsys_hps_lwhps2fpga_translator (
		.aclk              (clk_100_out_clk_clk),                                                     //   input,   width = 1,       clk.clk
		.aresetn           (~subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (subsys_hps_lwhps2fpga_translator_m0_awid),                                //  output,   width = 4,        m0.awid
		.m0_awaddr         (subsys_hps_lwhps2fpga_translator_m0_awaddr),                              //  output,  width = 29,          .awaddr
		.m0_awlen          (subsys_hps_lwhps2fpga_translator_m0_awlen),                               //  output,   width = 8,          .awlen
		.m0_awsize         (subsys_hps_lwhps2fpga_translator_m0_awsize),                              //  output,   width = 3,          .awsize
		.m0_awburst        (subsys_hps_lwhps2fpga_translator_m0_awburst),                             //  output,   width = 2,          .awburst
		.m0_awlock         (subsys_hps_lwhps2fpga_translator_m0_awlock),                              //  output,   width = 1,          .awlock
		.m0_awcache        (subsys_hps_lwhps2fpga_translator_m0_awcache),                             //  output,   width = 4,          .awcache
		.m0_awprot         (subsys_hps_lwhps2fpga_translator_m0_awprot),                              //  output,   width = 3,          .awprot
		.m0_awuser         (subsys_hps_lwhps2fpga_translator_m0_awuser),                              //  output,   width = 1,          .awuser
		.m0_awqos          (subsys_hps_lwhps2fpga_translator_m0_awqos),                               //  output,   width = 4,          .awqos
		.m0_awregion       (subsys_hps_lwhps2fpga_translator_m0_awregion),                            //  output,   width = 4,          .awregion
		.m0_awvalid        (subsys_hps_lwhps2fpga_translator_m0_awvalid),                             //  output,   width = 1,          .awvalid
		.m0_awready        (subsys_hps_lwhps2fpga_translator_m0_awready),                             //   input,   width = 1,          .awready
		.m0_wdata          (subsys_hps_lwhps2fpga_translator_m0_wdata),                               //  output,  width = 32,          .wdata
		.m0_wstrb          (subsys_hps_lwhps2fpga_translator_m0_wstrb),                               //  output,   width = 4,          .wstrb
		.m0_wlast          (subsys_hps_lwhps2fpga_translator_m0_wlast),                               //  output,   width = 1,          .wlast
		.m0_wvalid         (subsys_hps_lwhps2fpga_translator_m0_wvalid),                              //  output,   width = 1,          .wvalid
		.m0_wuser          (subsys_hps_lwhps2fpga_translator_m0_wuser),                               //  output,   width = 1,          .wuser
		.m0_wready         (subsys_hps_lwhps2fpga_translator_m0_wready),                              //   input,   width = 1,          .wready
		.m0_bid            (subsys_hps_lwhps2fpga_translator_m0_bid),                                 //   input,   width = 4,          .bid
		.m0_bresp          (subsys_hps_lwhps2fpga_translator_m0_bresp),                               //   input,   width = 2,          .bresp
		.m0_buser          (subsys_hps_lwhps2fpga_translator_m0_buser),                               //   input,   width = 1,          .buser
		.m0_bvalid         (subsys_hps_lwhps2fpga_translator_m0_bvalid),                              //   input,   width = 1,          .bvalid
		.m0_bready         (subsys_hps_lwhps2fpga_translator_m0_bready),                              //  output,   width = 1,          .bready
		.m0_arid           (subsys_hps_lwhps2fpga_translator_m0_arid),                                //  output,   width = 4,          .arid
		.m0_araddr         (subsys_hps_lwhps2fpga_translator_m0_araddr),                              //  output,  width = 29,          .araddr
		.m0_arlen          (subsys_hps_lwhps2fpga_translator_m0_arlen),                               //  output,   width = 8,          .arlen
		.m0_arsize         (subsys_hps_lwhps2fpga_translator_m0_arsize),                              //  output,   width = 3,          .arsize
		.m0_arburst        (subsys_hps_lwhps2fpga_translator_m0_arburst),                             //  output,   width = 2,          .arburst
		.m0_arlock         (subsys_hps_lwhps2fpga_translator_m0_arlock),                              //  output,   width = 1,          .arlock
		.m0_arcache        (subsys_hps_lwhps2fpga_translator_m0_arcache),                             //  output,   width = 4,          .arcache
		.m0_arprot         (subsys_hps_lwhps2fpga_translator_m0_arprot),                              //  output,   width = 3,          .arprot
		.m0_aruser         (subsys_hps_lwhps2fpga_translator_m0_aruser),                              //  output,   width = 1,          .aruser
		.m0_arqos          (subsys_hps_lwhps2fpga_translator_m0_arqos),                               //  output,   width = 4,          .arqos
		.m0_arregion       (subsys_hps_lwhps2fpga_translator_m0_arregion),                            //  output,   width = 4,          .arregion
		.m0_arvalid        (subsys_hps_lwhps2fpga_translator_m0_arvalid),                             //  output,   width = 1,          .arvalid
		.m0_arready        (subsys_hps_lwhps2fpga_translator_m0_arready),                             //   input,   width = 1,          .arready
		.m0_rid            (subsys_hps_lwhps2fpga_translator_m0_rid),                                 //   input,   width = 4,          .rid
		.m0_rdata          (subsys_hps_lwhps2fpga_translator_m0_rdata),                               //   input,  width = 32,          .rdata
		.m0_rresp          (subsys_hps_lwhps2fpga_translator_m0_rresp),                               //   input,   width = 2,          .rresp
		.m0_rlast          (subsys_hps_lwhps2fpga_translator_m0_rlast),                               //   input,   width = 1,          .rlast
		.m0_rvalid         (subsys_hps_lwhps2fpga_translator_m0_rvalid),                              //   input,   width = 1,          .rvalid
		.m0_rready         (subsys_hps_lwhps2fpga_translator_m0_rready),                              //  output,   width = 1,          .rready
		.m0_ruser          (subsys_hps_lwhps2fpga_translator_m0_ruser),                               //   input,   width = 1,          .ruser
		.s0_awid           (subsys_hps_lwhps2fpga_awid),                                              //   input,   width = 4,        s0.awid
		.s0_awaddr         (subsys_hps_lwhps2fpga_awaddr),                                            //   input,  width = 29,          .awaddr
		.s0_awlen          (subsys_hps_lwhps2fpga_awlen),                                             //   input,   width = 8,          .awlen
		.s0_awsize         (subsys_hps_lwhps2fpga_awsize),                                            //   input,   width = 3,          .awsize
		.s0_awburst        (subsys_hps_lwhps2fpga_awburst),                                           //   input,   width = 2,          .awburst
		.s0_awlock         (subsys_hps_lwhps2fpga_awlock),                                            //   input,   width = 1,          .awlock
		.s0_awcache        (subsys_hps_lwhps2fpga_awcache),                                           //   input,   width = 4,          .awcache
		.s0_awprot         (subsys_hps_lwhps2fpga_awprot),                                            //   input,   width = 3,          .awprot
		.s0_awvalid        (subsys_hps_lwhps2fpga_awvalid),                                           //   input,   width = 1,          .awvalid
		.s0_awready        (subsys_hps_lwhps2fpga_awready),                                           //  output,   width = 1,          .awready
		.s0_wdata          (subsys_hps_lwhps2fpga_wdata),                                             //   input,  width = 32,          .wdata
		.s0_wstrb          (subsys_hps_lwhps2fpga_wstrb),                                             //   input,   width = 4,          .wstrb
		.s0_wlast          (subsys_hps_lwhps2fpga_wlast),                                             //   input,   width = 1,          .wlast
		.s0_wvalid         (subsys_hps_lwhps2fpga_wvalid),                                            //   input,   width = 1,          .wvalid
		.s0_wready         (subsys_hps_lwhps2fpga_wready),                                            //  output,   width = 1,          .wready
		.s0_bid            (subsys_hps_lwhps2fpga_bid),                                               //  output,   width = 4,          .bid
		.s0_bresp          (subsys_hps_lwhps2fpga_bresp),                                             //  output,   width = 2,          .bresp
		.s0_bvalid         (subsys_hps_lwhps2fpga_bvalid),                                            //  output,   width = 1,          .bvalid
		.s0_bready         (subsys_hps_lwhps2fpga_bready),                                            //   input,   width = 1,          .bready
		.s0_arid           (subsys_hps_lwhps2fpga_arid),                                              //   input,   width = 4,          .arid
		.s0_araddr         (subsys_hps_lwhps2fpga_araddr),                                            //   input,  width = 29,          .araddr
		.s0_arlen          (subsys_hps_lwhps2fpga_arlen),                                             //   input,   width = 8,          .arlen
		.s0_arsize         (subsys_hps_lwhps2fpga_arsize),                                            //   input,   width = 3,          .arsize
		.s0_arburst        (subsys_hps_lwhps2fpga_arburst),                                           //   input,   width = 2,          .arburst
		.s0_arlock         (subsys_hps_lwhps2fpga_arlock),                                            //   input,   width = 1,          .arlock
		.s0_arcache        (subsys_hps_lwhps2fpga_arcache),                                           //   input,   width = 4,          .arcache
		.s0_arprot         (subsys_hps_lwhps2fpga_arprot),                                            //   input,   width = 3,          .arprot
		.s0_arvalid        (subsys_hps_lwhps2fpga_arvalid),                                           //   input,   width = 1,          .arvalid
		.s0_arready        (subsys_hps_lwhps2fpga_arready),                                           //  output,   width = 1,          .arready
		.s0_rid            (subsys_hps_lwhps2fpga_rid),                                               //  output,   width = 4,          .rid
		.s0_rdata          (subsys_hps_lwhps2fpga_rdata),                                             //  output,  width = 32,          .rdata
		.s0_rresp          (subsys_hps_lwhps2fpga_rresp),                                             //  output,   width = 2,          .rresp
		.s0_rlast          (subsys_hps_lwhps2fpga_rlast),                                             //  output,   width = 1,          .rlast
		.s0_rvalid         (subsys_hps_lwhps2fpga_rvalid),                                            //  output,   width = 1,          .rvalid
		.s0_rready         (subsys_hps_lwhps2fpga_rready),                                            //   input,   width = 1,          .rready
		.m0_awuser_addrchk (),                                                                        // (terminated),                        
		.m0_awuser_sai     (),                                                                        // (terminated),                        
		.m0_wuser_datachk  (),                                                                        // (terminated),                        
		.m0_wuser_data     (),                                                                        // (terminated),                        
		.m0_wuser_poison   (),                                                                        // (terminated),                        
		.m0_aruser_addrchk (),                                                                        // (terminated),                        
		.m0_aruser_sai     (),                                                                        // (terminated),                        
		.m0_ruser_datachk  (4'b0000),                                                                 // (terminated),                        
		.m0_ruser_data     (1'b0),                                                                    // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                                    // (terminated),                        
		.s0_awuser         (1'b0),                                                                    // (terminated),                        
		.s0_awuser_addrchk (1'b0),                                                                    // (terminated),                        
		.s0_awuser_sai     (1'b0),                                                                    // (terminated),                        
		.s0_awqos          (4'b0000),                                                                 // (terminated),                        
		.s0_awregion       (4'b0000),                                                                 // (terminated),                        
		.s0_wuser          (1'b0),                                                                    // (terminated),                        
		.s0_wuser_datachk  (4'b0000),                                                                 // (terminated),                        
		.s0_wuser_data     (1'b0),                                                                    // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                                    // (terminated),                        
		.s0_buser          (),                                                                        // (terminated),                        
		.s0_aruser         (1'b0),                                                                    // (terminated),                        
		.s0_aruser_addrchk (1'b0),                                                                    // (terminated),                        
		.s0_aruser_sai     (1'b0),                                                                    // (terminated),                        
		.s0_arqos          (4'b0000),                                                                 // (terminated),                        
		.s0_arregion       (4'b0000),                                                                 // (terminated),                        
		.s0_ruser          (),                                                                        // (terminated),                        
		.s0_ruser_datachk  (),                                                                        // (terminated),                        
		.s0_ruser_data     (),                                                                        // (terminated),                        
		.s0_ruser_poison   (),                                                                        // (terminated),                        
		.m0_wid            (),                                                                        // (terminated),                        
		.m0_arbar          (),                                                                        // (terminated),                        
		.m0_awbar          (),                                                                        // (terminated),                        
		.m0_awunique       (),                                                                        // (terminated),                        
		.m0_ardomain       (),                                                                        // (terminated),                        
		.m0_awdomain       (),                                                                        // (terminated),                        
		.m0_arsnoop        (),                                                                        // (terminated),                        
		.m0_awsnoop        (),                                                                        // (terminated),                        
		.s0_awakeup        (1'b0),                                                                    // (terminated),                        
		.s0_awtrace        (1'b0),                                                                    // (terminated),                        
		.s0_artrace        (1'b0),                                                                    // (terminated),                        
		.s0_wpoison        (1'b0),                                                                    // (terminated),                        
		.s0_wdatachk       (4'b0000),                                                                 // (terminated),                        
		.s0_wtrace         (1'b0),                                                                    // (terminated),                        
		.s0_btrace         (),                                                                        // (terminated),                        
		.s0_rpoison        (),                                                                        // (terminated),                        
		.s0_rdatachk       (),                                                                        // (terminated),                        
		.s0_rtrace         (),                                                                        // (terminated),                        
		.s0_awatop         (6'b000000),                                                               // (terminated),                        
		.s0_awstashnid     (11'b00000000000),                                                         // (terminated),                        
		.s0_awstashniden   (1'b0),                                                                    // (terminated),                        
		.s0_awstashlpid    (5'b00000),                                                                // (terminated),                        
		.s0_awstashlpiden  (1'b0),                                                                    // (terminated),                        
		.s0_awmmusecsid    (1'b0),                                                                    // (terminated),                        
		.s0_awmmusid       (16'b0000000000000000),                                                    // (terminated),                        
		.s0_armmusecsid    (1'b0),                                                                    // (terminated),                        
		.s0_armmusid       (16'b0000000000000000),                                                    // (terminated),                        
		.s0_awaddrchk      (1'b0),                                                                    // (terminated),                        
		.s0_araddrchk      (1'b0),                                                                    // (terminated),                        
		.m0_awakeup        (),                                                                        // (terminated),                        
		.m0_awtrace        (),                                                                        // (terminated),                        
		.m0_artrace        (),                                                                        // (terminated),                        
		.m0_wpoison        (),                                                                        // (terminated),                        
		.m0_wdatachk       (),                                                                        // (terminated),                        
		.m0_wtrace         (),                                                                        // (terminated),                        
		.m0_btrace         (1'b0),                                                                    // (terminated),                        
		.m0_rpoison        (1'b0),                                                                    // (terminated),                        
		.m0_rdatachk       (4'b0000),                                                                 // (terminated),                        
		.m0_rtrace         (1'b0),                                                                    // (terminated),                        
		.m0_awatop         (),                                                                        // (terminated),                        
		.m0_awstashnid     (),                                                                        // (terminated),                        
		.m0_awstashniden   (),                                                                        // (terminated),                        
		.m0_awstashlpid    (),                                                                        // (terminated),                        
		.m0_awstashlpiden  (),                                                                        // (terminated),                        
		.m0_awmmusecsid    (),                                                                        // (terminated),                        
		.m0_awmmusid       (),                                                                        // (terminated),                        
		.m0_armmusecsid    (),                                                                        // (terminated),                        
		.m0_armmusid       (),                                                                        // (terminated),                        
		.m0_awaddrchk      (),                                                                        // (terminated),                        
		.m0_araddrchk      (),                                                                        // (terminated),                        
		.s0_wid            (4'b0000),                                                                 // (terminated),                        
		.s0_arbar          (2'b00),                                                                   // (terminated),                        
		.s0_awbar          (2'b00),                                                                   // (terminated),                        
		.s0_awunique       (1'b0),                                                                    // (terminated),                        
		.s0_ardomain       (2'b00),                                                                   // (terminated),                        
		.s0_awdomain       (2'b00),                                                                   // (terminated),                        
		.s0_arsnoop        (4'b0000),                                                                 // (terminated),                        
		.s0_awsnoop        (3'b000)                                                                   // (terminated),                        
	);

	qsys_top_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (17),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (29),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) subsys_periph_pb_cpu_0_s0_translator (
		.clk                    (clk_100_out_clk_clk),                                                    //   input,   width = 1,                      clk.clk
		.reset                  (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (subsys_periph_pb_cpu_0_s0_agent_m0_address),                             //   input,  width = 29, avalon_universal_slave_0.address
		.uav_burstcount         (subsys_periph_pb_cpu_0_s0_agent_m0_burstcount),                          //   input,   width = 3,                         .burstcount
		.uav_read               (subsys_periph_pb_cpu_0_s0_agent_m0_read),                                //   input,   width = 1,                         .read
		.uav_write              (subsys_periph_pb_cpu_0_s0_agent_m0_write),                               //   input,   width = 1,                         .write
		.uav_waitrequest        (subsys_periph_pb_cpu_0_s0_agent_m0_waitrequest),                         //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (subsys_periph_pb_cpu_0_s0_agent_m0_readdatavalid),                       //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (subsys_periph_pb_cpu_0_s0_agent_m0_byteenable),                          //   input,   width = 4,                         .byteenable
		.uav_readdata           (subsys_periph_pb_cpu_0_s0_agent_m0_readdata),                            //  output,  width = 32,                         .readdata
		.uav_writedata          (subsys_periph_pb_cpu_0_s0_agent_m0_writedata),                           //   input,  width = 32,                         .writedata
		.uav_lock               (subsys_periph_pb_cpu_0_s0_agent_m0_lock),                                //   input,   width = 1,                         .lock
		.uav_debugaccess        (subsys_periph_pb_cpu_0_s0_agent_m0_debugaccess),                         //   input,   width = 1,                         .debugaccess
		.av_address             (subsys_periph_pb_cpu_0_s0_address),                                      //  output,  width = 17,      avalon_anti_slave_0.address
		.av_write               (subsys_periph_pb_cpu_0_s0_write),                                        //  output,   width = 1,                         .write
		.av_read                (subsys_periph_pb_cpu_0_s0_read),                                         //  output,   width = 1,                         .read
		.av_readdata            (subsys_periph_pb_cpu_0_s0_readdata),                                     //   input,  width = 32,                         .readdata
		.av_writedata           (subsys_periph_pb_cpu_0_s0_writedata),                                    //  output,  width = 32,                         .writedata
		.av_burstcount          (subsys_periph_pb_cpu_0_s0_burstcount),                                   //  output,   width = 1,                         .burstcount
		.av_byteenable          (subsys_periph_pb_cpu_0_s0_byteenable),                                   //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (subsys_periph_pb_cpu_0_s0_readdatavalid),                                //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (subsys_periph_pb_cpu_0_s0_waitrequest),                                  //   input,   width = 1,                         .waitrequest
		.av_debugaccess         (subsys_periph_pb_cpu_0_s0_debugaccess),                                  //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                                       // (terminated),                                       
		.av_beginbursttransfer  (),                                                                       // (terminated),                                       
		.av_writebyteenable     (),                                                                       // (terminated),                                       
		.av_lock                (),                                                                       // (terminated),                                       
		.av_chipselect          (),                                                                       // (terminated),                                       
		.av_clken               (),                                                                       // (terminated),                                       
		.uav_clken              (1'b0),                                                                   // (terminated),                                       
		.av_outputenable        (),                                                                       // (terminated),                                       
		.uav_response           (),                                                                       // (terminated),                                       
		.av_response            (2'b00),                                                                  // (terminated),                                       
		.uav_writeresponsevalid (),                                                                       // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                    // (terminated),                                       
	);

	qsys_top_altera_merlin_axi_master_ni_19116_f5viiry #(
		.ID_WIDTH                  (4),
		.ADDR_WIDTH                (29),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (8),
		.AXI_LOCK_WIDTH            (1),
		.SAI_WIDTH                 (1),
		.ADDRCHK_WIDTH             (1),
		.USER_DATA_WIDTH           (1),
		.AWSNOOP_WIDTH             (3),
		.SID_WIDTH                 (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (1),
		.AXI_VERSION               ("AXI4"),
		.ACE_LITE_SUPPORT          (0),
		.ACE5_LITE_SUPPORT         (0),
		.ROLE_BASED_USER           (0),
		.WRITE_ISSUING_CAPABILITY  (16),
		.READ_ISSUING_CAPABILITY   (16),
		.PKT_BEGIN_BURST           (96),
		.PKT_CACHE_H               (113),
		.PKT_CACHE_L               (110),
		.PKT_ADDR_SIDEBAND_H       (94),
		.PKT_ADDR_SIDEBAND_L       (94),
		.PKT_PROTECTION_H          (109),
		.PKT_PROTECTION_L          (107),
		.PKT_BURST_SIZE_H          (91),
		.PKT_BURST_SIZE_L          (89),
		.PKT_BURST_TYPE_H          (93),
		.PKT_BURST_TYPE_L          (92),
		.PKT_RESPONSE_STATUS_L     (114),
		.PKT_RESPONSE_STATUS_H     (115),
		.PKT_BURSTWRAP_H           (88),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (70),
		.PKT_TRANS_LOCK            (69),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (101),
		.PKT_SRC_ID_L              (101),
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (102),
		.PKT_THREAD_ID_H           (106),
		.PKT_THREAD_ID_L           (103),
		.PKT_QOS_L                 (97),
		.PKT_QOS_H                 (100),
		.PKT_ORI_BURST_SIZE_L      (116),
		.PKT_ORI_BURST_SIZE_H      (118),
		.PKT_DATA_SIDEBAND_H       (95),
		.PKT_DATA_SIDEBAND_L       (95),
		.PKT_DOMAIN_H              (126),
		.PKT_DOMAIN_L              (125),
		.PKT_SNOOP_H               (124),
		.PKT_SNOOP_L               (121),
		.PKT_BARRIER_H             (120),
		.PKT_BARRIER_L             (119),
		.PKT_WUNIQUE               (127),
		.PKT_EOP_OOO               (134),
		.PKT_SOP_OOO               (135),
		.PKT_ATRACE                (141),
		.PKT_TRACE                 (142),
		.PKT_AWAKEUP               (143),
		.PKT_POISON_H              (128),
		.PKT_POISON_L              (128),
		.PKT_DATACHK_H             (129),
		.PKT_DATACHK_L             (129),
		.PKT_ADDRCHK_H             (132),
		.PKT_ADDRCHK_L             (131),
		.PKT_SAI_H                 (133),
		.PKT_SAI_L                 (133),
		.PKT_USER_DATA_H           (130),
		.PKT_USER_DATA_L           (130),
		.PKT_AWATOP_L              (144),
		.PKT_AWATOP_H              (149),
		.PKT_AWSTASHNID_L          (150),
		.PKT_AWSTASHNID_H          (160),
		.PKT_AWSTASHNIDEN          (161),
		.PKT_AWSTASHLPID_L         (162),
		.PKT_AWSTASHLPID_H         (166),
		.PKT_AWSTASHLPIDEN         (167),
		.PKT_MMUSECSID             (169),
		.PKT_MMUSID_L              (168),
		.PKT_MMUSID_H              (168),
		.PKT_DATALESS              (170),
		.ST_DATA_W                 (171),
		.ST_CHANNEL_W              (2),
		.ID                        (0),
		.SYNC_RESET                (1),
		.DATA_USER_WIDTH           (1)
	) subsys_hps_lwhps2fpga_agent (
		.aclk                   (clk_100_out_clk_clk),                                                     //   input,    width = 1,              clk.clk
		.aresetn                (~subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,        clk_reset.reset_n
		.write_cp_valid         (subsys_hps_lwhps2fpga_agent_write_cp_valid),                              //  output,    width = 1,         write_cp.valid
		.write_cp_data          (subsys_hps_lwhps2fpga_agent_write_cp_data),                               //  output,  width = 171,                 .data
		.write_cp_startofpacket (subsys_hps_lwhps2fpga_agent_write_cp_startofpacket),                      //  output,    width = 1,                 .startofpacket
		.write_cp_endofpacket   (subsys_hps_lwhps2fpga_agent_write_cp_endofpacket),                        //  output,    width = 1,                 .endofpacket
		.write_cp_ready         (subsys_hps_lwhps2fpga_agent_write_cp_ready),                              //   input,    width = 1,                 .ready
		.write_rp_valid         (rsp_mux_src_valid),                                                       //   input,    width = 1,         write_rp.valid
		.write_rp_data          (rsp_mux_src_data),                                                        //   input,  width = 171,                 .data
		.write_rp_channel       (rsp_mux_src_channel),                                                     //   input,    width = 2,                 .channel
		.write_rp_startofpacket (rsp_mux_src_startofpacket),                                               //   input,    width = 1,                 .startofpacket
		.write_rp_endofpacket   (rsp_mux_src_endofpacket),                                                 //   input,    width = 1,                 .endofpacket
		.write_rp_ready         (rsp_mux_src_ready),                                                       //  output,    width = 1,                 .ready
		.read_cp_valid          (subsys_hps_lwhps2fpga_agent_read_cp_valid),                               //  output,    width = 1,          read_cp.valid
		.read_cp_data           (subsys_hps_lwhps2fpga_agent_read_cp_data),                                //  output,  width = 171,                 .data
		.read_cp_startofpacket  (subsys_hps_lwhps2fpga_agent_read_cp_startofpacket),                       //  output,    width = 1,                 .startofpacket
		.read_cp_endofpacket    (subsys_hps_lwhps2fpga_agent_read_cp_endofpacket),                         //  output,    width = 1,                 .endofpacket
		.read_cp_ready          (subsys_hps_lwhps2fpga_agent_read_cp_ready),                               //   input,    width = 1,                 .ready
		.read_rp_valid          (rsp_mux_001_src_valid),                                                   //   input,    width = 1,          read_rp.valid
		.read_rp_data           (rsp_mux_001_src_data),                                                    //   input,  width = 171,                 .data
		.read_rp_channel        (rsp_mux_001_src_channel),                                                 //   input,    width = 2,                 .channel
		.read_rp_startofpacket  (rsp_mux_001_src_startofpacket),                                           //   input,    width = 1,                 .startofpacket
		.read_rp_endofpacket    (rsp_mux_001_src_endofpacket),                                             //   input,    width = 1,                 .endofpacket
		.read_rp_ready          (rsp_mux_001_src_ready),                                                   //  output,    width = 1,                 .ready
		.awid                   (subsys_hps_lwhps2fpga_translator_m0_awid),                                //   input,    width = 4, altera_axi_slave.awid
		.awaddr                 (subsys_hps_lwhps2fpga_translator_m0_awaddr),                              //   input,   width = 29,                 .awaddr
		.awlen                  (subsys_hps_lwhps2fpga_translator_m0_awlen),                               //   input,    width = 8,                 .awlen
		.awsize                 (subsys_hps_lwhps2fpga_translator_m0_awsize),                              //   input,    width = 3,                 .awsize
		.awburst                (subsys_hps_lwhps2fpga_translator_m0_awburst),                             //   input,    width = 2,                 .awburst
		.awlock                 (subsys_hps_lwhps2fpga_translator_m0_awlock),                              //   input,    width = 1,                 .awlock
		.awcache                (subsys_hps_lwhps2fpga_translator_m0_awcache),                             //   input,    width = 4,                 .awcache
		.awprot                 (subsys_hps_lwhps2fpga_translator_m0_awprot),                              //   input,    width = 3,                 .awprot
		.awuser                 (subsys_hps_lwhps2fpga_translator_m0_awuser),                              //   input,    width = 1,                 .awuser
		.awqos                  (subsys_hps_lwhps2fpga_translator_m0_awqos),                               //   input,    width = 4,                 .awqos
		.awregion               (subsys_hps_lwhps2fpga_translator_m0_awregion),                            //   input,    width = 4,                 .awregion
		.awvalid                (subsys_hps_lwhps2fpga_translator_m0_awvalid),                             //   input,    width = 1,                 .awvalid
		.awready                (subsys_hps_lwhps2fpga_translator_m0_awready),                             //  output,    width = 1,                 .awready
		.wdata                  (subsys_hps_lwhps2fpga_translator_m0_wdata),                               //   input,   width = 32,                 .wdata
		.wstrb                  (subsys_hps_lwhps2fpga_translator_m0_wstrb),                               //   input,    width = 4,                 .wstrb
		.wlast                  (subsys_hps_lwhps2fpga_translator_m0_wlast),                               //   input,    width = 1,                 .wlast
		.wvalid                 (subsys_hps_lwhps2fpga_translator_m0_wvalid),                              //   input,    width = 1,                 .wvalid
		.wuser                  (subsys_hps_lwhps2fpga_translator_m0_wuser),                               //   input,    width = 1,                 .wuser
		.wready                 (subsys_hps_lwhps2fpga_translator_m0_wready),                              //  output,    width = 1,                 .wready
		.bid                    (subsys_hps_lwhps2fpga_translator_m0_bid),                                 //  output,    width = 4,                 .bid
		.bresp                  (subsys_hps_lwhps2fpga_translator_m0_bresp),                               //  output,    width = 2,                 .bresp
		.buser                  (subsys_hps_lwhps2fpga_translator_m0_buser),                               //  output,    width = 1,                 .buser
		.bvalid                 (subsys_hps_lwhps2fpga_translator_m0_bvalid),                              //  output,    width = 1,                 .bvalid
		.bready                 (subsys_hps_lwhps2fpga_translator_m0_bready),                              //   input,    width = 1,                 .bready
		.arid                   (subsys_hps_lwhps2fpga_translator_m0_arid),                                //   input,    width = 4,                 .arid
		.araddr                 (subsys_hps_lwhps2fpga_translator_m0_araddr),                              //   input,   width = 29,                 .araddr
		.arlen                  (subsys_hps_lwhps2fpga_translator_m0_arlen),                               //   input,    width = 8,                 .arlen
		.arsize                 (subsys_hps_lwhps2fpga_translator_m0_arsize),                              //   input,    width = 3,                 .arsize
		.arburst                (subsys_hps_lwhps2fpga_translator_m0_arburst),                             //   input,    width = 2,                 .arburst
		.arlock                 (subsys_hps_lwhps2fpga_translator_m0_arlock),                              //   input,    width = 1,                 .arlock
		.arcache                (subsys_hps_lwhps2fpga_translator_m0_arcache),                             //   input,    width = 4,                 .arcache
		.arprot                 (subsys_hps_lwhps2fpga_translator_m0_arprot),                              //   input,    width = 3,                 .arprot
		.aruser                 (subsys_hps_lwhps2fpga_translator_m0_aruser),                              //   input,    width = 1,                 .aruser
		.arqos                  (subsys_hps_lwhps2fpga_translator_m0_arqos),                               //   input,    width = 4,                 .arqos
		.arregion               (subsys_hps_lwhps2fpga_translator_m0_arregion),                            //   input,    width = 4,                 .arregion
		.arvalid                (subsys_hps_lwhps2fpga_translator_m0_arvalid),                             //   input,    width = 1,                 .arvalid
		.arready                (subsys_hps_lwhps2fpga_translator_m0_arready),                             //  output,    width = 1,                 .arready
		.rid                    (subsys_hps_lwhps2fpga_translator_m0_rid),                                 //  output,    width = 4,                 .rid
		.rdata                  (subsys_hps_lwhps2fpga_translator_m0_rdata),                               //  output,   width = 32,                 .rdata
		.rresp                  (subsys_hps_lwhps2fpga_translator_m0_rresp),                               //  output,    width = 2,                 .rresp
		.rlast                  (subsys_hps_lwhps2fpga_translator_m0_rlast),                               //  output,    width = 1,                 .rlast
		.rvalid                 (subsys_hps_lwhps2fpga_translator_m0_rvalid),                              //  output,    width = 1,                 .rvalid
		.rready                 (subsys_hps_lwhps2fpga_translator_m0_rready),                              //   input,    width = 1,                 .rready
		.ruser                  (subsys_hps_lwhps2fpga_translator_m0_ruser),                               //  output,    width = 1,                 .ruser
		.awuser_addrchk         (1'b0),                                                                    // (terminated),                                
		.awuser_sai             (1'b0),                                                                    // (terminated),                                
		.wuser_datachk          (4'b0000),                                                                 // (terminated),                                
		.wuser_data             (1'b0),                                                                    // (terminated),                                
		.wuser_poison           (1'b0),                                                                    // (terminated),                                
		.aruser_addrchk         (1'b0),                                                                    // (terminated),                                
		.aruser_sai             (1'b0),                                                                    // (terminated),                                
		.ruser_datachk          (),                                                                        // (terminated),                                
		.ruser_data             (),                                                                        // (terminated),                                
		.ruser_poison           (),                                                                        // (terminated),                                
		.awakeup                (1'b0),                                                                    // (terminated),                                
		.awtrace                (1'b0),                                                                    // (terminated),                                
		.artrace                (1'b0),                                                                    // (terminated),                                
		.wpoison                (1'b0),                                                                    // (terminated),                                
		.wdatachk               (4'b0000),                                                                 // (terminated),                                
		.wtrace                 (1'b0),                                                                    // (terminated),                                
		.btrace                 (),                                                                        // (terminated),                                
		.rpoison                (),                                                                        // (terminated),                                
		.rdatachk               (),                                                                        // (terminated),                                
		.rtrace                 (),                                                                        // (terminated),                                
		.wid                    (4'b0000),                                                                 // (terminated),                                
		.awatop                 (6'b000000),                                                               // (terminated),                                
		.awstashnid             (11'b00000000000),                                                         // (terminated),                                
		.awstashniden           (1'b0),                                                                    // (terminated),                                
		.awstashlpid            (5'b00000),                                                                // (terminated),                                
		.awstashlpiden          (1'b0),                                                                    // (terminated),                                
		.awmmusecsid            (1'b0),                                                                    // (terminated),                                
		.awmmusid               (1'b0),                                                                    // (terminated),                                
		.armmusecsid            (1'b0),                                                                    // (terminated),                                
		.armmusid               (1'b0),                                                                    // (terminated),                                
		.awaddrchk              (1'b0),                                                                    // (terminated),                                
		.araddrchk              (1'b0),                                                                    // (terminated),                                
		.arsnoop                (4'b0000),                                                                 // (terminated),                                
		.ardomain               (2'b00),                                                                   // (terminated),                                
		.arbar                  (2'b00),                                                                   // (terminated),                                
		.awsnoop                (3'b000),                                                                  // (terminated),                                
		.awdomain               (2'b00),                                                                   // (terminated),                                
		.awbar                  (2'b00),                                                                   // (terminated),                                
		.awunique               (1'b0)                                                                     // (terminated),                                
	);

	qsys_top_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (118),
		.PKT_ORI_BURST_SIZE_L      (116),
		.PKT_RESPONSE_STATUS_H     (115),
		.PKT_RESPONSE_STATUS_L     (114),
		.PKT_BURST_SIZE_H          (91),
		.PKT_BURST_SIZE_L          (89),
		.PKT_TRANS_LOCK            (69),
		.PKT_BEGIN_BURST           (96),
		.PKT_PROTECTION_H          (109),
		.PKT_PROTECTION_L          (107),
		.PKT_BURSTWRAP_H           (88),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (71),
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_POSTED          (66),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (101),
		.PKT_SRC_ID_L              (101),
		.PKT_DEST_ID_H             (102),
		.PKT_DEST_ID_L             (102),
		.PKT_POISON_H              (128),
		.PKT_POISON_L              (128),
		.PKT_DATACHK_H             (129),
		.PKT_DATACHK_L             (129),
		.PKT_SAI_H                 (133),
		.PKT_SAI_L                 (133),
		.PKT_ADDRCHK_H             (132),
		.PKT_ADDRCHK_L             (131),
		.PKT_USER_DATA_H           (130),
		.PKT_USER_DATA_L           (130),
		.PKT_ATRACE                (141),
		.PKT_TRACE                 (142),
		.PKT_AWAKEUP               (143),
		.PKT_AWATOP_H              (149),
		.PKT_AWATOP_L              (144),
		.PKT_AWSTASHNID_H          (160),
		.PKT_AWSTASHNID_L          (150),
		.PKT_AWSTASHNIDEN          (161),
		.PKT_AWSTASHLPID_H         (166),
		.PKT_AWSTASHLPID_L         (162),
		.PKT_AWSTASHLPIDEN         (167),
		.PKT_MMUSECSID             (169),
		.PKT_MMUSID_H              (168),
		.PKT_MMUSID_L              (168),
		.PKT_DATALESS              (170),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (171),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) subsys_periph_pb_cpu_0_s0_agent (
		.clk                     (clk_100_out_clk_clk),                                                    //   input,    width = 1,             clk.clk
		.reset                   (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (subsys_periph_pb_cpu_0_s0_agent_m0_address),                             //  output,   width = 29,              m0.address
		.m0_burstcount           (subsys_periph_pb_cpu_0_s0_agent_m0_burstcount),                          //  output,    width = 3,                .burstcount
		.m0_byteenable           (subsys_periph_pb_cpu_0_s0_agent_m0_byteenable),                          //  output,    width = 4,                .byteenable
		.m0_debugaccess          (subsys_periph_pb_cpu_0_s0_agent_m0_debugaccess),                         //  output,    width = 1,                .debugaccess
		.m0_lock                 (subsys_periph_pb_cpu_0_s0_agent_m0_lock),                                //  output,    width = 1,                .lock
		.m0_readdata             (subsys_periph_pb_cpu_0_s0_agent_m0_readdata),                            //   input,   width = 32,                .readdata
		.m0_readdatavalid        (subsys_periph_pb_cpu_0_s0_agent_m0_readdatavalid),                       //   input,    width = 1,                .readdatavalid
		.m0_read                 (subsys_periph_pb_cpu_0_s0_agent_m0_read),                                //  output,    width = 1,                .read
		.m0_waitrequest          (subsys_periph_pb_cpu_0_s0_agent_m0_waitrequest),                         //   input,    width = 1,                .waitrequest
		.m0_writedata            (subsys_periph_pb_cpu_0_s0_agent_m0_writedata),                           //  output,   width = 32,                .writedata
		.m0_write                (subsys_periph_pb_cpu_0_s0_agent_m0_write),                               //  output,    width = 1,                .write
		.rp_endofpacket          (subsys_periph_pb_cpu_0_s0_agent_rp_endofpacket),                         //  output,    width = 1,              rp.endofpacket
		.rp_ready                (subsys_periph_pb_cpu_0_s0_agent_rp_ready),                               //   input,    width = 1,                .ready
		.rp_valid                (subsys_periph_pb_cpu_0_s0_agent_rp_valid),                               //  output,    width = 1,                .valid
		.rp_data                 (subsys_periph_pb_cpu_0_s0_agent_rp_data),                                //  output,  width = 171,                .data
		.rp_startofpacket        (subsys_periph_pb_cpu_0_s0_agent_rp_startofpacket),                       //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_source0_ready),                                           //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_source0_valid),                                           //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_source0_data),                                            //   input,  width = 171,                .data
		.cp_startofpacket        (agent_pipeline_source0_startofpacket),                                   //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_source0_endofpacket),                                     //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_source0_channel),                                         //   input,    width = 2,                .channel
		.rf_sink_ready           (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_ready),                     //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_startofpacket),             //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_endofpacket),               //   input,    width = 1,                .endofpacket
		.rf_sink_data            (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_data),                      //   input,  width = 172,                .data
		.rf_source_ready         (subsys_periph_pb_cpu_0_s0_agent_rf_source_ready),                        //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (subsys_periph_pb_cpu_0_s0_agent_rf_source_valid),                        //  output,    width = 1,                .valid
		.rf_source_startofpacket (subsys_periph_pb_cpu_0_s0_agent_rf_source_startofpacket),                //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (subsys_periph_pb_cpu_0_s0_agent_rf_source_endofpacket),                  //  output,    width = 1,                .endofpacket
		.rf_source_data          (subsys_periph_pb_cpu_0_s0_agent_rf_source_data),                         //  output,  width = 172,                .data
		.rdata_fifo_sink_ready   (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_ready),                   //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_valid),                   //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_data),                    //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_ready),                   //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_valid),                   //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_data),                    //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                  // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                   // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                    // (terminated),                               
	);

	qsys_top_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (172),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) subsys_periph_pb_cpu_0_s0_agent_rsp_fifo (
		.clk               (clk_100_out_clk_clk),                                                            //   input,    width = 1,       clk.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_data           (subsys_periph_pb_cpu_0_s0_agent_rf_source_data),                                 //   input,  width = 172,        in.data
		.in_valid          (subsys_periph_pb_cpu_0_s0_agent_rf_source_valid),                                //   input,    width = 1,          .valid
		.in_ready          (subsys_periph_pb_cpu_0_s0_agent_rf_source_ready),                                //  output,    width = 1,          .ready
		.in_startofpacket  (subsys_periph_pb_cpu_0_s0_agent_rf_source_startofpacket),                        //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_periph_pb_cpu_0_s0_agent_rf_source_endofpacket),                          //   input,    width = 1,          .endofpacket
		.out_data          (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_data),                              //  output,  width = 172,       out.data
		.out_valid         (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_valid),                             //  output,    width = 1,          .valid
		.out_ready         (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_ready),                             //   input,    width = 1,          .ready
		.out_startofpacket (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_startofpacket),                     //  output,    width = 1,          .startofpacket
		.out_endofpacket   (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_endofpacket),                       //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                          // (terminated),                         
		.csr_read          (1'b0),                                                                           // (terminated),                         
		.csr_write         (1'b0),                                                                           // (terminated),                         
		.csr_readdata      (),                                                                               // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                           // (terminated),                         
		.almost_full_data  (),                                                                               // (terminated),                         
		.almost_empty_data (),                                                                               // (terminated),                         
		.in_empty          (1'b0),                                                                           // (terminated),                         
		.out_empty         (),                                                                               // (terminated),                         
		.in_error          (1'b0),                                                                           // (terminated),                         
		.out_error         (),                                                                               // (terminated),                         
		.in_channel        (1'b0),                                                                           // (terminated),                         
		.out_channel       ()                                                                                // (terminated),                         
	);

	qsys_top_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) subsys_periph_pb_cpu_0_s0_agent_rdata_fifo (
		.clk               (clk_100_out_clk_clk),                                                            //   input,   width = 1,       clk.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset
		.in_data           (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_data),                            //   input,  width = 34,        in.data
		.in_valid          (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_valid),                           //   input,   width = 1,          .valid
		.in_ready          (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_ready),                           //  output,   width = 1,          .ready
		.out_data          (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_data),                            //  output,  width = 34,       out.data
		.out_valid         (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_valid),                           //  output,   width = 1,          .valid
		.out_ready         (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_ready),                           //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                                          // (terminated),                        
		.csr_read          (1'b0),                                                                           // (terminated),                        
		.csr_write         (1'b0),                                                                           // (terminated),                        
		.csr_readdata      (),                                                                               // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                                           // (terminated),                        
		.almost_full_data  (),                                                                               // (terminated),                        
		.almost_empty_data (),                                                                               // (terminated),                        
		.in_startofpacket  (1'b0),                                                                           // (terminated),                        
		.in_endofpacket    (1'b0),                                                                           // (terminated),                        
		.out_startofpacket (),                                                                               // (terminated),                        
		.out_endofpacket   (),                                                                               // (terminated),                        
		.in_empty          (1'b0),                                                                           // (terminated),                        
		.out_empty         (),                                                                               // (terminated),                        
		.in_error          (1'b0),                                                                           // (terminated),                        
		.out_error         (),                                                                               // (terminated),                        
		.in_channel        (1'b0),                                                                           // (terminated),                        
		.out_channel       ()                                                                                // (terminated),                        
	);

	qsys_top_altera_merlin_router_1921_ox5xuhq router (
		.sink_ready         (subsys_hps_lwhps2fpga_agent_write_cp_ready),                             //  output,    width = 1,      sink.ready
		.sink_valid         (subsys_hps_lwhps2fpga_agent_write_cp_valid),                             //   input,    width = 1,          .valid
		.sink_data          (subsys_hps_lwhps2fpga_agent_write_cp_data),                              //   input,  width = 171,          .data
		.sink_startofpacket (subsys_hps_lwhps2fpga_agent_write_cp_startofpacket),                     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_lwhps2fpga_agent_write_cp_endofpacket),                       //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset              (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                                        //  output,  width = 171,          .data
		.src_channel        (router_src_channel),                                                     //  output,    width = 2,          .channel
		.src_startofpacket  (router_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_ox5xuhq router_001 (
		.sink_ready         (subsys_hps_lwhps2fpga_agent_read_cp_ready),                              //  output,    width = 1,      sink.ready
		.sink_valid         (subsys_hps_lwhps2fpga_agent_read_cp_valid),                              //   input,    width = 1,          .valid
		.sink_data          (subsys_hps_lwhps2fpga_agent_read_cp_data),                               //   input,  width = 171,          .data
		.sink_startofpacket (subsys_hps_lwhps2fpga_agent_read_cp_startofpacket),                      //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_lwhps2fpga_agent_read_cp_endofpacket),                        //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset              (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                                   //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                                   //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                                    //  output,  width = 171,          .data
		.src_channel        (router_001_src_channel),                                                 //  output,    width = 2,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                              //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_sxavatq router_002 (
		.sink_ready         (agent_pipeline_001_source0_ready),                                       //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_001_source0_valid),                                       //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_001_source0_data),                                        //   input,  width = 171,          .data
		.sink_startofpacket (agent_pipeline_001_source0_startofpacket),                               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_001_source0_endofpacket),                                 //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset              (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                                   //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                                   //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                                    //  output,  width = 171,          .data
		.src_channel        (router_002_src_channel),                                                 //  output,    width = 2,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                              //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy #(
		.PKT_ADDR_H                (64),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (96),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (71),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (91),
		.PKT_BURST_SIZE_L          (89),
		.PKT_BURST_TYPE_H          (93),
		.PKT_BURST_TYPE_L          (92),
		.PKT_BURSTWRAP_H           (88),
		.PKT_BURSTWRAP_L           (82),
		.PKT_SAI_H                 (133),
		.PKT_SAI_L                 (133),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.PKT_TRANS_COMPRESSED_READ (65),
		.PKT_TRANS_WRITE           (67),
		.PKT_TRANS_READ            (68),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (171),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (73),
		.OUT_BURSTWRAP_H           (88),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("new"),
		.SYNC_RESET                (1)
	) subsys_periph_pb_cpu_0_s0_burst_adapter (
		.clk                   (clk_100_out_clk_clk),                                                    //   input,    width = 1,       cr0.clk
		.reset                 (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_src_valid),                                                      //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_src_data),                                                       //   input,  width = 171,          .data
		.sink0_channel         (cmd_mux_src_channel),                                                    //   input,    width = 2,          .channel
		.sink0_startofpacket   (cmd_mux_src_startofpacket),                                              //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_src_endofpacket),                                                //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_src_ready),                                                      //  output,    width = 1,          .ready
		.source0_valid         (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_valid),                  //  output,    width = 1,   source0.valid
		.source0_data          (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_data),                   //  output,  width = 171,          .data
		.source0_channel       (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_channel),                //  output,    width = 2,          .channel
		.source0_startofpacket (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_startofpacket),          //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_endofpacket),            //  output,    width = 1,          .endofpacket
		.source0_ready         (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_ready)                   //   input,    width = 1,          .ready
	);

	qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q cmd_demux (
		.clk                (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset              (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_src_ready),                                                       //  output,    width = 1,      sink.ready
		.sink_channel       (router_src_channel),                                                     //   input,    width = 2,          .channel
		.sink_data          (router_src_data),                                                        //   input,  width = 171,          .data
		.sink_startofpacket (router_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink_valid         (router_src_valid),                                                       //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_src0_ready),                                                   //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                   //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_src0_data),                                                    //  output,  width = 171,          .data
		.src0_channel       (cmd_demux_src0_channel),                                                 //  output,    width = 2,          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                              //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q cmd_demux_001 (
		.clk                (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset              (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                                                   //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                                                 //   input,    width = 2,          .channel
		.sink_data          (router_001_src_data),                                                    //   input,  width = 171,          .data
		.sink_startofpacket (router_001_src_startofpacket),                                           //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                             //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                                                   //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                                               //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                                               //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_001_src0_data),                                                //  output,  width = 171,          .data
		.src0_channel       (cmd_demux_001_src0_channel),                                             //  output,    width = 2,          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                                       //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                                          //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_666s25q cmd_mux (
		.clk                 (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset               (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                      //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                                      //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                                       //  output,  width = 171,          .data
		.src_channel         (cmd_mux_src_channel),                                                    //  output,    width = 2,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                                //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_source0_ready),                                             //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_source0_valid),                                             //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_source0_channel),                                           //   input,    width = 2,          .channel
		.sink0_data          (mux_pipeline_source0_data),                                              //   input,  width = 171,          .data
		.sink0_startofpacket (mux_pipeline_source0_startofpacket),                                     //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_source0_endofpacket),                                       //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_001_source0_ready),                                         //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_001_source0_valid),                                         //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_001_source0_channel),                                       //   input,    width = 2,          .channel
		.sink1_data          (mux_pipeline_001_source0_data),                                          //   input,  width = 171,          .data
		.sink1_startofpacket (mux_pipeline_001_source0_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_001_source0_endofpacket)                                    //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_qyizksq rsp_demux (
		.clk                (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset              (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_002_src_ready),                                                   //  output,    width = 1,      sink.ready
		.sink_channel       (router_002_src_channel),                                                 //   input,    width = 2,          .channel
		.sink_data          (router_002_src_data),                                                    //   input,  width = 171,          .data
		.sink_startofpacket (router_002_src_startofpacket),                                           //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                                             //   input,    width = 1,          .endofpacket
		.sink_valid         (router_002_src_valid),                                                   //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                                   //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                                   //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                                    //  output,  width = 171,          .data
		.src0_channel       (rsp_demux_src0_channel),                                                 //  output,    width = 2,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                                             //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                                   //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                                   //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_src1_data),                                                    //  output,  width = 171,          .data
		.src1_channel       (rsp_demux_src1_channel),                                                 //  output,    width = 2,          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                                              //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_yjgptii rsp_mux (
		.clk                 (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset               (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                      //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                                      //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                                       //  output,  width = 171,          .data
		.src_channel         (rsp_mux_src_channel),                                                    //  output,    width = 2,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                                //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_002_source0_ready),                                         //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_002_source0_valid),                                         //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_002_source0_channel),                                       //   input,    width = 2,          .channel
		.sink0_data          (mux_pipeline_002_source0_data),                                          //   input,  width = 171,          .data
		.sink0_startofpacket (mux_pipeline_002_source0_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_002_source0_endofpacket)                                    //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_yjgptii rsp_mux_001 (
		.clk                 (clk_100_out_clk_clk),                                                    //   input,    width = 1,       clk.clk
		.reset               (subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                                                  //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_001_src_valid),                                                  //  output,    width = 1,          .valid
		.src_data            (rsp_mux_001_src_data),                                                   //  output,  width = 171,          .data
		.src_channel         (rsp_mux_001_src_channel),                                                //  output,    width = 2,          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                                          //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                                            //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_003_source0_ready),                                         //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_003_source0_valid),                                         //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_003_source0_channel),                                       //   input,    width = 2,          .channel
		.sink0_data          (mux_pipeline_003_source0_data),                                          //   input,  width = 171,          .data
		.sink0_startofpacket (mux_pipeline_003_source0_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_003_source0_endofpacket)                                    //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (171),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline (
		.clk               (clk_100_out_clk_clk),                                                            //   input,    width = 1,       cr0.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_ready),                          //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_valid),                          //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_startofpacket),                  //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_endofpacket),                    //   input,    width = 1,          .endofpacket
		.in_data           (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_data),                           //   input,  width = 171,          .data
		.in_channel        (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_channel),                        //   input,    width = 2,          .channel
		.out_ready         (agent_pipeline_source0_ready),                                                   //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_source0_valid),                                                   //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),                                             //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_source0_data),                                                    //  output,  width = 171,          .data
		.out_channel       (agent_pipeline_source0_channel),                                                 //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                           // (terminated),                         
		.out_empty         (),                                                                               // (terminated),                         
		.out_error         (),                                                                               // (terminated),                         
		.in_error          (1'b0)                                                                            // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (171),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                                                            //   input,    width = 1,       cr0.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_periph_pb_cpu_0_s0_agent_rp_ready),                                       //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_periph_pb_cpu_0_s0_agent_rp_valid),                                       //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_periph_pb_cpu_0_s0_agent_rp_startofpacket),                               //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_periph_pb_cpu_0_s0_agent_rp_endofpacket),                                 //   input,    width = 1,          .endofpacket
		.in_data           (subsys_periph_pb_cpu_0_s0_agent_rp_data),                                        //   input,  width = 171,          .data
		.out_ready         (agent_pipeline_001_source0_ready),                                               //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),                                               //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),                                       //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),                                         //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),                                                //  output,  width = 171,          .data
		.in_empty          (1'b0),                                                                           // (terminated),                         
		.out_empty         (),                                                                               // (terminated),                         
		.out_error         (),                                                                               // (terminated),                         
		.in_error          (1'b0),                                                                           // (terminated),                         
		.out_channel       (),                                                                               // (terminated),                         
		.in_channel        (1'b0)                                                                            // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (171),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline (
		.clk               (clk_100_out_clk_clk),                                                            //   input,    width = 1,       cr0.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_src0_ready),                                                           //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_src0_valid),                                                           //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_src0_data),                                                            //   input,  width = 171,          .data
		.in_channel        (cmd_demux_src0_channel),                                                         //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_source0_ready),                                                     //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_source0_valid),                                                     //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_source0_startofpacket),                                             //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_source0_endofpacket),                                               //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_source0_data),                                                      //  output,  width = 171,          .data
		.out_channel       (mux_pipeline_source0_channel),                                                   //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                           // (terminated),                         
		.out_empty         (),                                                                               // (terminated),                         
		.out_error         (),                                                                               // (terminated),                         
		.in_error          (1'b0)                                                                            // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (171),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                                                            //   input,    width = 1,       cr0.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_001_src0_ready),                                                       //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_001_src0_valid),                                                       //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_001_src0_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_001_src0_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_001_src0_data),                                                        //   input,  width = 171,          .data
		.in_channel        (cmd_demux_001_src0_channel),                                                     //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_001_source0_ready),                                                 //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_001_source0_valid),                                                 //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_001_source0_startofpacket),                                         //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_001_source0_endofpacket),                                           //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_001_source0_data),                                                  //  output,  width = 171,          .data
		.out_channel       (mux_pipeline_001_source0_channel),                                               //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                           // (terminated),                         
		.out_empty         (),                                                                               // (terminated),                         
		.out_error         (),                                                                               // (terminated),                         
		.in_error          (1'b0)                                                                            // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (171),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_002 (
		.clk               (clk_100_out_clk_clk),                                                            //   input,    width = 1,       cr0.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_src0_ready),                                                           //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_src0_valid),                                                           //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_src0_data),                                                            //   input,  width = 171,          .data
		.in_channel        (rsp_demux_src0_channel),                                                         //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_002_source0_ready),                                                 //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_002_source0_valid),                                                 //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_002_source0_startofpacket),                                         //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_002_source0_endofpacket),                                           //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_002_source0_data),                                                  //  output,  width = 171,          .data
		.out_channel       (mux_pipeline_002_source0_channel),                                               //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                           // (terminated),                         
		.out_empty         (),                                                                               // (terminated),                         
		.out_error         (),                                                                               // (terminated),                         
		.in_error          (1'b0)                                                                            // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (171),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_003 (
		.clk               (clk_100_out_clk_clk),                                                            //   input,    width = 1,       cr0.clk
		.reset             (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_src1_ready),                                                           //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_src1_valid),                                                           //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_src1_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_src1_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_src1_data),                                                            //   input,  width = 171,          .data
		.in_channel        (rsp_demux_src1_channel),                                                         //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_003_source0_ready),                                                 //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_003_source0_valid),                                                 //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_003_source0_startofpacket),                                         //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_003_source0_endofpacket),                                           //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_003_source0_data),                                                  //  output,  width = 171,          .data
		.out_channel       (mux_pipeline_003_source0_channel),                                               //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                           // (terminated),                         
		.out_empty         (),                                                                               // (terminated),                         
		.out_error         (),                                                                               // (terminated),                         
		.in_error          (1'b0)                                                                            // (terminated),                         
	);

endmodule
