# datasheet for qsys_top

qsys_top |

2026.05.11.21:03:53 | Datasheet

Overview

Processor
subsys_hps_agilex_hps sm_hps 13.0.0
All Components
subsys_periph peripheral_subsys 1.0
subsys_periph_button_pio altera_avalon_pio 19.2.3
subsys_periph_dipsw_pio altera_avalon_pio 19.2.3
subsys_periph_led_pio altera_avalon_pio 19.2.3
subsys_periph_pb_cpu_0 altera_avalon_mm_bridge 20.1.0
subsys_periph_sysid altera_avalon_sysid_qsys 19.1.7
Memory Map

| subsys_hps | subsys_hps_agilex_hps | subsys_periph_pb_cpu_0
hps2fpga | lwhps2fpga | hps2fpga | lwhps2fpga | m0
subsys_hps |  |  |  |  |
f2sdram |  |  |  |  |
subsys_hps_agilex_hps |  |  |  |  |
f2sdram |  |  |  |  |
subsys_periph |  |  |  |  |
pb_cpu_0_s0 |  |  |  |  |
subsys_periph_button_pio |  |  |  |  |
s1 |  | 0x0001_0060 - 0x0001_006f |  | 0x0001_0060 - 0x0001_006f | 0x0001_0060 - 0x0001_006f
subsys_periph_dipsw_pio |  |  |  |  |
s1 |  | 0x0001_0070 - 0x0001_007f |  | 0x0001_0070 - 0x0001_007f | 0x0001_0070 - 0x0001_007f
subsys_periph_led_pio |  |  |  |  |
s1 |  | 0x0001_0080 - 0x0001_008f |  | 0x0001_0080 - 0x0001_008f | 0x0001_0080 - 0x0001_008f
subsys_periph_pb_cpu_0 |  |  |  |  |
s0 |  | 0x0000_0000 - 0x0001_ffff |  | 0x0000_0000 - 0x0001_ffff |
subsys_periph_sysid |  |  |  |  |
control_slave |  | 0x0001_0000 - 0x0001_0007 |  | 0x0001_0000 - 0x0001_0007 | 0x0001_0000 - 0x0001_0007

## clk_100

altera_clock_bridge v19.2.0

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## rst_in

altera_reset_bridge v19.2.0

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## user_rst_clkgate_0

intel_user_rst_clkgate v1.0.1

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## subsys_hps

hps_subsys v1.0

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## subsys_hps_agilex_hps

intel_agilex_5_soc v13.0.0

subsys_hps_emif_hps | io96b0_to_hps | subsys_hps_agilex_hps
io96b0_to_hps
clk_100 | out_clk
f2sdram_axi_clock
out_clk
hps2fpga_axi_clock
out_clk
lwhps2fpga_axi_clock
rst_in | out_reset
f2sdram_axi_reset
out_reset
hps2fpga_axi_reset
out_reset
lwhps2fpga_axi_reset
|  | lwhps2fpga | subsys_periph_pb_cpu_0
|  | s0
|  | fpga2hps_interrupt_irq0 | subsys_periph_button_pio
|  | irq
|  | fpga2hps_interrupt_irq0 | subsys_periph_dipsw_pio
|  | irq

## Parameters

generateLegacySim | false

## Software Assignments

CPU_FREQ | 50000000u

## subsys_hps_emif_hps

emif_io96b_hps v4.0.0

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## subsys_periph

peripheral_subsys v1.0

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## subsys_periph_button_pio

altera_avalon_pio v19.2.3

subsys_periph_pb_cpu_0 | m0 | subsys_periph_button_pio
s1
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset
subsys_hps_agilex_hps | fpga2hps_interrupt_irq0
irq

## Parameters

generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 1
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | FALLING
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## subsys_periph_dipsw_pio

altera_avalon_pio v19.2.3

subsys_periph_pb_cpu_0 | m0 | subsys_periph_dipsw_pio
s1
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset
subsys_hps_agilex_hps | fpga2hps_interrupt_irq0
irq

## Parameters

generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 1
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | FALLING
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## subsys_periph_led_pio

altera_avalon_pio v19.2.3

subsys_periph_pb_cpu_0 | m0 | subsys_periph_led_pio
s1
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset

## Parameters

generateLegacySim | false

## Software Assignments

BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 3
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 7

## subsys_periph_pb_cpu_0

altera_avalon_mm_bridge v20.1.0

subsys_periph_periph_clk | out_clk | subsys_periph_pb_cpu_0
clk
subsys_periph_periph_rst_in | out_reset
reset
subsys_hps_agilex_hps | lwhps2fpga
s0
|  | m0 | subsys_periph_sysid
|  | control_slave
|  | m0 | subsys_periph_led_pio
|  | s1
|  | m0 | subsys_periph_dipsw_pio
|  | s1
|  | m0 | subsys_periph_button_pio
|  | s1

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## subsys_periph_periph_clk

altera_clock_bridge v19.2.0

clk_100 | out_clk | subsys_periph_periph_clk
in_clk
|  | out_clk | subsys_periph_sysid
|  | clk
|  | out_clk | subsys_periph_pb_cpu_0
|  | clk
|  | out_clk | subsys_periph_led_pio
|  | clk
|  | out_clk | subsys_periph_dipsw_pio
|  | clk
|  | out_clk | subsys_periph_button_pio
|  | clk

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## subsys_periph_periph_rst_in

altera_reset_bridge v19.2.0

rst_in | out_reset | subsys_periph_periph_rst_in
in_reset
|  | out_reset | subsys_periph_sysid
|  | reset
|  | out_reset | subsys_periph_led_pio
|  | reset
|  | out_reset | subsys_periph_dipsw_pio
|  | reset
|  | out_reset | subsys_periph_button_pio
|  | reset
|  | out_reset | subsys_periph_pb_cpu_0
|  | reset

## Parameters

generateLegacySim | false

## Software Assignments

(none)

## subsys_periph_sysid

altera_avalon_sysid_qsys v19.1.7

subsys_periph_pb_cpu_0 | m0 | subsys_periph_sysid
control_slave
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset

## Parameters

generateLegacySim | false

## Software Assignments

ID | -1395275010
TIMESTAMP | 0

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