// EMIF_Qsys_emif_io96b_lpddr4_0.v

// Generated using ACDS version 25.3.1 100

`timescale 1 ps / 1 ps
module EMIF_Qsys_emif_io96b_lpddr4_0 (
		input  wire         s0_axi4_clock_in,    //    s0_axi4_clock_in.clk,         User clock for mainband axi. Input clock to the EMIF IP, no relationship to PHY clock.
		input  wire         core_init_n,         //         core_init_n.reset_n,     Core init signal going into EMIF. Used to generate the reset signal on the core-EMIF interface in fabric modes. When high, indicates core initialization is complete. The Reset Release IP should be used to generate the core initialization complete signal.
		output wire         s0_axi4_reset_n,     //  s0_axi4_ctrl_ready.reset_n,     Output signal from EMIF IP (primary I/O bank), indicating that Calibration of the channels in this I/O bank is complete, and controllers in this I/O bank are ready for use.
		input  wire [29:0]  s0_axi4_awaddr,      //             s0_axi4.awaddr,      Write Address , channel 0.
		input  wire [1:0]   s0_axi4_awburst,     //                    .awburst,     Write Burst Type, channel 0.
		input  wire [6:0]   s0_axi4_awid,        //                    .awid,        Write Address ID, channel 0.
		input  wire [7:0]   s0_axi4_awlen,       //                    .awlen,       Write Burst Length, channel 0.
		input  wire         s0_axi4_awlock,      //                    .awlock,      Write Lock Type, channel 0.
		input  wire [3:0]   s0_axi4_awqos,       //                    .awqos,       Write Quality of Service, channel 0.
		input  wire [2:0]   s0_axi4_awsize,      //                    .awsize,      Write Burst Size, channel 0.
		input  wire         s0_axi4_awvalid,     //                    .awvalid,     Write Address Valid, channel 0.
		input  wire [13:0]  s0_axi4_awuser,      //                    .awuser,      Write Address User Signal, channel 0.
		input  wire [2:0]   s0_axi4_awprot,      //                    .awprot,      Write Protection Type, channel 0.
		output wire         s0_axi4_awready,     //                    .awready,     Write Address Ready, channel 0.
		input  wire [29:0]  s0_axi4_araddr,      //                    .araddr,      Read Address , channel 0.
		input  wire [1:0]   s0_axi4_arburst,     //                    .arburst,     Read Burst Type, channel 0.
		input  wire [6:0]   s0_axi4_arid,        //                    .arid,        Read Address ID, channel 0.
		input  wire [7:0]   s0_axi4_arlen,       //                    .arlen,       Read Burst Length, channel 0.
		input  wire         s0_axi4_arlock,      //                    .arlock,      Read Lock Type, channel 0.
		input  wire [3:0]   s0_axi4_arqos,       //                    .arqos,       Read Quality of Service, channel 0.
		input  wire [2:0]   s0_axi4_arsize,      //                    .arsize,      Read Burst Size, channel 0.
		input  wire         s0_axi4_arvalid,     //                    .arvalid,     Read Address Valid, channel 0.
		input  wire [13:0]  s0_axi4_aruser,      //                    .aruser,      Read Address User Signal, channel 0.
		input  wire [2:0]   s0_axi4_arprot,      //                    .arprot,      Read Protection Type, channel 0.
		output wire         s0_axi4_arready,     //                    .arready,     Read Address Ready, channel 0.
		input  wire [255:0] s0_axi4_wdata,       //                    .wdata,       Write Data , channel 0.
		input  wire [31:0]  s0_axi4_wstrb,       //                    .wstrb,       Write Strobes, channel 0.
		input  wire         s0_axi4_wlast,       //                    .wlast,       Write Last, channel 0.
		input  wire         s0_axi4_wvalid,      //                    .wvalid,      Write Valid, channel 0.
		output wire         s0_axi4_wready,      //                    .wready,      Write Ready, channel 0.
		input  wire         s0_axi4_bready,      //                    .bready,      Write Response Ready, channel 0.
		output wire [6:0]   s0_axi4_bid,         //                    .bid,         Write Response ID, channel 0.
		output wire [1:0]   s0_axi4_bresp,       //                    .bresp,       Write Response , channel 0.
		output wire         s0_axi4_bvalid,      //                    .bvalid,      Write Response Valid, channel 0.
		input  wire         s0_axi4_rready,      //                    .rready,      Read Ready, channel 0.
		output wire [255:0] s0_axi4_rdata,       //                    .rdata,       Read Data, channel 0.
		output wire [6:0]   s0_axi4_rid,         //                    .rid,         Read ID , channel 0.
		output wire         s0_axi4_rlast,       //                    .rlast,       Read Last, channel 0.
		output wire [1:0]   s0_axi4_rresp,       //                    .rresp,       Read Response, channel 0.
		output wire         s0_axi4_rvalid,      //                    .rvalid,      Read Valid, channel 0.
		input  wire         s0_axi4lite_clock,   //   s0_axi4lite_clock.clk,         Axi-Lite clock, to primary IOSSM.
		input  wire         s0_axi4lite_reset_n, // s0_axi4lite_reset_n.reset_n,     Axi-Lite reset_n, to primary IOSSM.
		input  wire [26:0]  s0_axi4lite_awaddr,  //         s0_axi4lite.awaddr,      Axi-Lite Write Address, to primary IOSSM.
		input  wire [2:0]   s0_axi4lite_awprot,  //                    .awprot,      Axi-Lite Write Address Protection Signal, to primary IOSSM.
		input  wire         s0_axi4lite_awvalid, //                    .awvalid,     Axi-Lite Write Address Valid, to primary IOSSM.
		output wire         s0_axi4lite_awready, //                    .awready,     Axi-Lite Write Address Ready, to primary IOSSM.
		input  wire [26:0]  s0_axi4lite_araddr,  //                    .araddr,      Axi-Lite Read Address, to primary IOSSM.
		input  wire [2:0]   s0_axi4lite_arprot,  //                    .arprot,      Axi-Lite Read Address Protection Signal, to primary IOSSM.
		input  wire         s0_axi4lite_arvalid, //                    .arvalid,     Axi-Lite Read Address Valid, to primary IOSSM.
		output wire         s0_axi4lite_arready, //                    .arready,     Axi-Lite Read Address Ready, to primary IOSSM.
		input  wire [31:0]  s0_axi4lite_wdata,   //                    .wdata,       Axi-Lite Write Data, to primary IOSSM.
		input  wire [3:0]   s0_axi4lite_wstrb,   //                    .wstrb,       Axi-Lite Write Strobe, to primary IOSSM.
		input  wire         s0_axi4lite_wvalid,  //                    .wvalid,      Axi-Lite Write Valid, to primary IOSSM.
		output wire         s0_axi4lite_wready,  //                    .wready,      Axi-Lite Write Ready, to primary IOSSM.
		input  wire         s0_axi4lite_bready,  //                    .bready,      Axi-Lite Write Response Ready, to primary IOSSM.
		output wire [1:0]   s0_axi4lite_bresp,   //                    .bresp,       Axi-Lite Write Response, to primary IOSSM.
		output wire         s0_axi4lite_bvalid,  //                    .bvalid,      Axi-Lite Write Response Valid, to primary IOSSM.
		input  wire         s0_axi4lite_rready,  //                    .rready,      Axi-Lite Read Ready, to primary IOSSM.
		output wire [31:0]  s0_axi4lite_rdata,   //                    .rdata,       Axi-Lite Read Data, to primary IOSSM.
		output wire [1:0]   s0_axi4lite_rresp,   //                    .rresp,       Axi-Lite Read Response, to primary IOSSM.
		output wire         s0_axi4lite_rvalid,  //                    .rvalid,      Axi-Lite Read Valid, to primary IOSSM.
		output wire [0:0]   mem_0_cs,            //               mem_0.mem_cs,      Chip Select channel 0.
		output wire [5:0]   mem_0_ca,            //                    .mem_ca,      Command/Address Bus channel 0.
		output wire [0:0]   mem_0_cke,           //                    .mem_cke,     Clock Enable channel 0.
		inout  wire [31:0]  mem_0_dq,            //                    .mem_dq,      Data (read/write) channel 0.
		inout  wire [3:0]   mem_0_dqs_t,         //                    .mem_dqs_t,   Data Strobe (true) channel 0.
		inout  wire [3:0]   mem_0_dqs_c,         //                    .mem_dqs_c,   Data Strobe (complement) channel 0.
		inout  wire [3:0]   mem_0_dmi,           //                    .mem_dmi,     Data Mask/Data Inversion channel 0.
		output wire [0:0]   mem_0_ck_t,          //            mem_ck_0.mem_ck_t,    CK Clock (true) channel 0.
		output wire [0:0]   mem_0_ck_c,          //                    .mem_ck_c,    CK Clock (complement) channel 0.
		output wire         mem_0_reset_n,       //         mem_reset_n.mem_reset_n, Asynchronous Reset channel 0.
		input  wire         oct_rzqin_0,         //               oct_0.oct_rzqin,   Calibrated On-Chip Termination (OCT) input pin channel 0.
		input  wire         ref_clk              //             ref_clk.clk,         PLL reference clock input.
	);

	EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry emif_io96b_lpddr4_0 (
		.s0_axi4_clock_in    (s0_axi4_clock_in),    //   input,    width = 1,    s0_axi4_clock_in.clk
		.core_init_n         (core_init_n),         //   input,    width = 1,         core_init_n.reset_n
		.s0_axi4_reset_n     (s0_axi4_reset_n),     //  output,    width = 1,  s0_axi4_ctrl_ready.reset_n
		.s0_axi4_awaddr      (s0_axi4_awaddr),      //   input,   width = 30,             s0_axi4.awaddr
		.s0_axi4_awburst     (s0_axi4_awburst),     //   input,    width = 2,                    .awburst
		.s0_axi4_awid        (s0_axi4_awid),        //   input,    width = 7,                    .awid
		.s0_axi4_awlen       (s0_axi4_awlen),       //   input,    width = 8,                    .awlen
		.s0_axi4_awlock      (s0_axi4_awlock),      //   input,    width = 1,                    .awlock
		.s0_axi4_awqos       (s0_axi4_awqos),       //   input,    width = 4,                    .awqos
		.s0_axi4_awsize      (s0_axi4_awsize),      //   input,    width = 3,                    .awsize
		.s0_axi4_awvalid     (s0_axi4_awvalid),     //   input,    width = 1,                    .awvalid
		.s0_axi4_awuser      (s0_axi4_awuser),      //   input,   width = 14,                    .awuser
		.s0_axi4_awprot      (s0_axi4_awprot),      //   input,    width = 3,                    .awprot
		.s0_axi4_awready     (s0_axi4_awready),     //  output,    width = 1,                    .awready
		.s0_axi4_araddr      (s0_axi4_araddr),      //   input,   width = 30,                    .araddr
		.s0_axi4_arburst     (s0_axi4_arburst),     //   input,    width = 2,                    .arburst
		.s0_axi4_arid        (s0_axi4_arid),        //   input,    width = 7,                    .arid
		.s0_axi4_arlen       (s0_axi4_arlen),       //   input,    width = 8,                    .arlen
		.s0_axi4_arlock      (s0_axi4_arlock),      //   input,    width = 1,                    .arlock
		.s0_axi4_arqos       (s0_axi4_arqos),       //   input,    width = 4,                    .arqos
		.s0_axi4_arsize      (s0_axi4_arsize),      //   input,    width = 3,                    .arsize
		.s0_axi4_arvalid     (s0_axi4_arvalid),     //   input,    width = 1,                    .arvalid
		.s0_axi4_aruser      (s0_axi4_aruser),      //   input,   width = 14,                    .aruser
		.s0_axi4_arprot      (s0_axi4_arprot),      //   input,    width = 3,                    .arprot
		.s0_axi4_arready     (s0_axi4_arready),     //  output,    width = 1,                    .arready
		.s0_axi4_wdata       (s0_axi4_wdata),       //   input,  width = 256,                    .wdata
		.s0_axi4_wstrb       (s0_axi4_wstrb),       //   input,   width = 32,                    .wstrb
		.s0_axi4_wlast       (s0_axi4_wlast),       //   input,    width = 1,                    .wlast
		.s0_axi4_wvalid      (s0_axi4_wvalid),      //   input,    width = 1,                    .wvalid
		.s0_axi4_wready      (s0_axi4_wready),      //  output,    width = 1,                    .wready
		.s0_axi4_bready      (s0_axi4_bready),      //   input,    width = 1,                    .bready
		.s0_axi4_bid         (s0_axi4_bid),         //  output,    width = 7,                    .bid
		.s0_axi4_bresp       (s0_axi4_bresp),       //  output,    width = 2,                    .bresp
		.s0_axi4_bvalid      (s0_axi4_bvalid),      //  output,    width = 1,                    .bvalid
		.s0_axi4_rready      (s0_axi4_rready),      //   input,    width = 1,                    .rready
		.s0_axi4_rdata       (s0_axi4_rdata),       //  output,  width = 256,                    .rdata
		.s0_axi4_rid         (s0_axi4_rid),         //  output,    width = 7,                    .rid
		.s0_axi4_rlast       (s0_axi4_rlast),       //  output,    width = 1,                    .rlast
		.s0_axi4_rresp       (s0_axi4_rresp),       //  output,    width = 2,                    .rresp
		.s0_axi4_rvalid      (s0_axi4_rvalid),      //  output,    width = 1,                    .rvalid
		.s0_axi4lite_clock   (s0_axi4lite_clock),   //   input,    width = 1,   s0_axi4lite_clock.clk
		.s0_axi4lite_reset_n (s0_axi4lite_reset_n), //   input,    width = 1, s0_axi4lite_reset_n.reset_n
		.s0_axi4lite_awaddr  (s0_axi4lite_awaddr),  //   input,   width = 27,         s0_axi4lite.awaddr
		.s0_axi4lite_awprot  (s0_axi4lite_awprot),  //   input,    width = 3,                    .awprot
		.s0_axi4lite_awvalid (s0_axi4lite_awvalid), //   input,    width = 1,                    .awvalid
		.s0_axi4lite_awready (s0_axi4lite_awready), //  output,    width = 1,                    .awready
		.s0_axi4lite_araddr  (s0_axi4lite_araddr),  //   input,   width = 27,                    .araddr
		.s0_axi4lite_arprot  (s0_axi4lite_arprot),  //   input,    width = 3,                    .arprot
		.s0_axi4lite_arvalid (s0_axi4lite_arvalid), //   input,    width = 1,                    .arvalid
		.s0_axi4lite_arready (s0_axi4lite_arready), //  output,    width = 1,                    .arready
		.s0_axi4lite_wdata   (s0_axi4lite_wdata),   //   input,   width = 32,                    .wdata
		.s0_axi4lite_wstrb   (s0_axi4lite_wstrb),   //   input,    width = 4,                    .wstrb
		.s0_axi4lite_wvalid  (s0_axi4lite_wvalid),  //   input,    width = 1,                    .wvalid
		.s0_axi4lite_wready  (s0_axi4lite_wready),  //  output,    width = 1,                    .wready
		.s0_axi4lite_bready  (s0_axi4lite_bready),  //   input,    width = 1,                    .bready
		.s0_axi4lite_bresp   (s0_axi4lite_bresp),   //  output,    width = 2,                    .bresp
		.s0_axi4lite_bvalid  (s0_axi4lite_bvalid),  //  output,    width = 1,                    .bvalid
		.s0_axi4lite_rready  (s0_axi4lite_rready),  //   input,    width = 1,                    .rready
		.s0_axi4lite_rdata   (s0_axi4lite_rdata),   //  output,   width = 32,                    .rdata
		.s0_axi4lite_rresp   (s0_axi4lite_rresp),   //  output,    width = 2,                    .rresp
		.s0_axi4lite_rvalid  (s0_axi4lite_rvalid),  //  output,    width = 1,                    .rvalid
		.mem_0_cs            (mem_0_cs),            //  output,    width = 1,               mem_0.mem_cs
		.mem_0_ca            (mem_0_ca),            //  output,    width = 6,                    .mem_ca
		.mem_0_cke           (mem_0_cke),           //  output,    width = 1,                    .mem_cke
		.mem_0_dq            (mem_0_dq),            //   inout,   width = 32,                    .mem_dq
		.mem_0_dqs_t         (mem_0_dqs_t),         //   inout,    width = 4,                    .mem_dqs_t
		.mem_0_dqs_c         (mem_0_dqs_c),         //   inout,    width = 4,                    .mem_dqs_c
		.mem_0_dmi           (mem_0_dmi),           //   inout,    width = 4,                    .mem_dmi
		.mem_0_ck_t          (mem_0_ck_t),          //  output,    width = 1,            mem_ck_0.mem_ck_t
		.mem_0_ck_c          (mem_0_ck_c),          //  output,    width = 1,                    .mem_ck_c
		.mem_0_reset_n       (mem_0_reset_n),       //  output,    width = 1,         mem_reset_n.mem_reset_n
		.oct_rzqin_0         (oct_rzqin_0),         //   input,    width = 1,               oct_0.oct_rzqin
		.ref_clk             (ref_clk)              //   input,    width = 1,             ref_clk.clk
	);

endmodule
