<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2026.05.11.21:04:03"
 outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Agilex 5"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="A5EB013BB23BE4SCS"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="4"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_BOARD"
     type="String"
     defaultValue="default"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_HPS2FPGA_AXI_CLOCK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_HPS2FPGA_AXI_CLOCK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_HPS2FPGA_AXI_CLOCK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_HPS2FPGA_ADDRESS_MAP"
     type="AddressMap"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_HPS2FPGA_ADDRESS_WIDTH"
     type="AddressWidthType"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_LWHPS2FPGA_AXI_CLOCK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_LWHPS2FPGA_AXI_CLOCK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_LWHPS2FPGA_AXI_CLOCK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_LWHPS2FPGA_ADDRESS_MAP"
     type="AddressMap"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_LWHPS2FPGA_ADDRESS_WIDTH"
     type="AddressWidthType"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_FPGA2HPS_INTERRUPT_IRQ1_INTERRUPTS_USED"
     type="BigInteger"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_FPGA2HPS_INTERRUPT_IRQ0_INTERRUPTS_USED"
     type="BigInteger"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_F2SDRAM_AXI_CLOCK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_F2SDRAM_AXI_CLOCK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_F2SDRAM_AXI_CLOCK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_F2SDRAM_CPU_INFO_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <interface name="h2f_reset" kind="reset" start="1">
   <property name="associatedClock" value="" />
   <property name="associatedDirectReset" value="" />
   <property name="associatedResetSinks" value="none" />
   <property name="synchronousEdges" value="NONE" />
   <port name="h2f_reset_reset" direction="output" role="reset" width="1" />
  </interface>
  <interface name="hps2fpga_axi_clock" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="hps2fpga_axi_clock_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="hps2fpga_axi_reset" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port
       name="hps2fpga_axi_reset_reset"
       direction="input"
       role="reset"
       width="1" />
  </interface>
  <interface name="hps2fpga" kind="axi4" start="1">
   <property name="associatedClock" value="hps2fpga_axi_clock" />
   <property name="associatedReset" value="hps2fpga_axi_reset" />
   <property name="optionalAssociatedReset" value="false" />
   <property name="trustzoneAware" value="true" />
   <property name="wakeupSignals" value="false" />
   <property name="uniqueIdSupport" value="false" />
   <property name="poison" value="false" />
   <property name="traceSignals" value="false" />
   <property name="isTranslator" value="false" />
   <property name="maximumOutstandingReads" value="1" />
   <property name="maximumOutstandingWrites" value="1" />
   <property name="maximumOutstandingTransactions" value="1" />
   <property name="dataCheck" value="false" />
   <property name="addressCheck" value="false" />
   <property name="securityAttribute" value="false" />
   <property name="userData" value="false" />
   <property name="readIssuingCapability" value="16" />
   <property name="writeIssuingCapability" value="16" />
   <property name="combinedIssuingCapability" value="16" />
   <property name="enableConcurrentSubordinateAccess" value="0" />
   <property name="noRepeatedIdsBetweenSubordinates" value="0" />
   <property name="issuesINCRBursts" value="true" />
   <property name="issuesWRAPBursts" value="true" />
   <property name="issuesFIXEDBursts" value="true" />
   <port name="hps2fpga_awid" direction="output" role="awid" width="4" />
   <port name="hps2fpga_awaddr" direction="output" role="awaddr" width="38" />
   <port name="hps2fpga_awlen" direction="output" role="awlen" width="8" />
   <port name="hps2fpga_awsize" direction="output" role="awsize" width="3" />
   <port name="hps2fpga_awburst" direction="output" role="awburst" width="2" />
   <port name="hps2fpga_awlock" direction="output" role="awlock" width="1" />
   <port name="hps2fpga_awcache" direction="output" role="awcache" width="4" />
   <port name="hps2fpga_awprot" direction="output" role="awprot" width="3" />
   <port name="hps2fpga_awvalid" direction="output" role="awvalid" width="1" />
   <port name="hps2fpga_awready" direction="input" role="awready" width="1" />
   <port name="hps2fpga_wdata" direction="output" role="wdata" width="128" />
   <port name="hps2fpga_wstrb" direction="output" role="wstrb" width="16" />
   <port name="hps2fpga_wlast" direction="output" role="wlast" width="1" />
   <port name="hps2fpga_wvalid" direction="output" role="wvalid" width="1" />
   <port name="hps2fpga_wready" direction="input" role="wready" width="1" />
   <port name="hps2fpga_bid" direction="input" role="bid" width="4" />
   <port name="hps2fpga_bresp" direction="input" role="bresp" width="2" />
   <port name="hps2fpga_bvalid" direction="input" role="bvalid" width="1" />
   <port name="hps2fpga_bready" direction="output" role="bready" width="1" />
   <port name="hps2fpga_arid" direction="output" role="arid" width="4" />
   <port name="hps2fpga_araddr" direction="output" role="araddr" width="38" />
   <port name="hps2fpga_arlen" direction="output" role="arlen" width="8" />
   <port name="hps2fpga_arsize" direction="output" role="arsize" width="3" />
   <port name="hps2fpga_arburst" direction="output" role="arburst" width="2" />
   <port name="hps2fpga_arlock" direction="output" role="arlock" width="1" />
   <port name="hps2fpga_arcache" direction="output" role="arcache" width="4" />
   <port name="hps2fpga_arprot" direction="output" role="arprot" width="3" />
   <port name="hps2fpga_arvalid" direction="output" role="arvalid" width="1" />
   <port name="hps2fpga_arready" direction="input" role="arready" width="1" />
   <port name="hps2fpga_rid" direction="input" role="rid" width="4" />
   <port name="hps2fpga_rdata" direction="input" role="rdata" width="128" />
   <port name="hps2fpga_rresp" direction="input" role="rresp" width="2" />
   <port name="hps2fpga_rlast" direction="input" role="rlast" width="1" />
   <port name="hps2fpga_rvalid" direction="input" role="rvalid" width="1" />
   <port name="hps2fpga_rready" direction="output" role="rready" width="1" />
  </interface>
  <interface name="lwhps2fpga_axi_clock" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port
       name="lwhps2fpga_axi_clock_clk"
       direction="input"
       role="clk"
       width="1" />
  </interface>
  <interface name="lwhps2fpga_axi_reset" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port
       name="lwhps2fpga_axi_reset_reset"
       direction="input"
       role="reset"
       width="1" />
  </interface>
  <interface name="lwhps2fpga" kind="axi4" start="1">
   <property name="associatedClock" value="lwhps2fpga_axi_clock" />
   <property name="associatedReset" value="lwhps2fpga_axi_reset" />
   <property name="optionalAssociatedReset" value="false" />
   <property name="trustzoneAware" value="true" />
   <property name="wakeupSignals" value="false" />
   <property name="uniqueIdSupport" value="false" />
   <property name="poison" value="false" />
   <property name="traceSignals" value="false" />
   <property name="isTranslator" value="false" />
   <property name="maximumOutstandingReads" value="1" />
   <property name="maximumOutstandingWrites" value="1" />
   <property name="maximumOutstandingTransactions" value="1" />
   <property name="dataCheck" value="false" />
   <property name="addressCheck" value="false" />
   <property name="securityAttribute" value="false" />
   <property name="userData" value="false" />
   <property name="readIssuingCapability" value="16" />
   <property name="writeIssuingCapability" value="16" />
   <property name="combinedIssuingCapability" value="16" />
   <property name="enableConcurrentSubordinateAccess" value="0" />
   <property name="noRepeatedIdsBetweenSubordinates" value="0" />
   <property name="issuesINCRBursts" value="true" />
   <property name="issuesWRAPBursts" value="true" />
   <property name="issuesFIXEDBursts" value="true" />
   <port name="lwhps2fpga_awid" direction="output" role="awid" width="4" />
   <port name="lwhps2fpga_awaddr" direction="output" role="awaddr" width="29" />
   <port name="lwhps2fpga_awlen" direction="output" role="awlen" width="8" />
   <port name="lwhps2fpga_awsize" direction="output" role="awsize" width="3" />
   <port name="lwhps2fpga_awburst" direction="output" role="awburst" width="2" />
   <port name="lwhps2fpga_awlock" direction="output" role="awlock" width="1" />
   <port name="lwhps2fpga_awcache" direction="output" role="awcache" width="4" />
   <port name="lwhps2fpga_awprot" direction="output" role="awprot" width="3" />
   <port name="lwhps2fpga_awvalid" direction="output" role="awvalid" width="1" />
   <port name="lwhps2fpga_awready" direction="input" role="awready" width="1" />
   <port name="lwhps2fpga_wdata" direction="output" role="wdata" width="32" />
   <port name="lwhps2fpga_wstrb" direction="output" role="wstrb" width="4" />
   <port name="lwhps2fpga_wlast" direction="output" role="wlast" width="1" />
   <port name="lwhps2fpga_wvalid" direction="output" role="wvalid" width="1" />
   <port name="lwhps2fpga_wready" direction="input" role="wready" width="1" />
   <port name="lwhps2fpga_bid" direction="input" role="bid" width="4" />
   <port name="lwhps2fpga_bresp" direction="input" role="bresp" width="2" />
   <port name="lwhps2fpga_bvalid" direction="input" role="bvalid" width="1" />
   <port name="lwhps2fpga_bready" direction="output" role="bready" width="1" />
   <port name="lwhps2fpga_arid" direction="output" role="arid" width="4" />
   <port name="lwhps2fpga_araddr" direction="output" role="araddr" width="29" />
   <port name="lwhps2fpga_arlen" direction="output" role="arlen" width="8" />
   <port name="lwhps2fpga_arsize" direction="output" role="arsize" width="3" />
   <port name="lwhps2fpga_arburst" direction="output" role="arburst" width="2" />
   <port name="lwhps2fpga_arlock" direction="output" role="arlock" width="1" />
   <port name="lwhps2fpga_arcache" direction="output" role="arcache" width="4" />
   <port name="lwhps2fpga_arprot" direction="output" role="arprot" width="3" />
   <port name="lwhps2fpga_arvalid" direction="output" role="arvalid" width="1" />
   <port name="lwhps2fpga_arready" direction="input" role="arready" width="1" />
   <port name="lwhps2fpga_rid" direction="input" role="rid" width="4" />
   <port name="lwhps2fpga_rdata" direction="input" role="rdata" width="32" />
   <port name="lwhps2fpga_rresp" direction="input" role="rresp" width="2" />
   <port name="lwhps2fpga_rlast" direction="input" role="rlast" width="1" />
   <port name="lwhps2fpga_rvalid" direction="input" role="rvalid" width="1" />
   <port name="lwhps2fpga_rready" direction="output" role="rready" width="1" />
  </interface>
  <interface name="emac0_app_rst" kind="reset" start="1">
   <property name="associatedClock" value="" />
   <property name="associatedDirectReset" value="" />
   <property name="associatedResetSinks" value="none" />
   <property name="synchronousEdges" value="NONE" />
   <port
       name="emac0_app_rst_reset_n"
       direction="output"
       role="reset_n"
       width="1" />
  </interface>
  <interface name="h2f_warm_reset_handshake" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="h2f_warm_reset_handshake_reset_req"
       direction="output"
       role="reset_req"
       width="1" />
   <port
       name="h2f_warm_reset_handshake_reset_ack"
       direction="input"
       role="reset_ack"
       width="1" />
  </interface>
  <interface name="hps_io" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="hps_io_hps_osc_clk"
       direction="input"
       role="hps_osc_clk"
       width="1" />
   <port
       name="hps_io_sdmmc_data0"
       direction="bidir"
       role="sdmmc_data0"
       width="1" />
   <port
       name="hps_io_sdmmc_data1"
       direction="bidir"
       role="sdmmc_data1"
       width="1" />
   <port
       name="hps_io_sdmmc_cclk"
       direction="output"
       role="sdmmc_cclk"
       width="1" />
   <port
       name="hps_io_sdmmc_data2"
       direction="bidir"
       role="sdmmc_data2"
       width="1" />
   <port
       name="hps_io_sdmmc_data3"
       direction="bidir"
       role="sdmmc_data3"
       width="1" />
   <port name="hps_io_sdmmc_cmd" direction="bidir" role="sdmmc_cmd" width="1" />
   <port name="hps_io_usb0_clk" direction="input" role="usb0_clk" width="1" />
   <port name="hps_io_usb0_stp" direction="output" role="usb0_stp" width="1" />
   <port name="hps_io_usb0_dir" direction="input" role="usb0_dir" width="1" />
   <port
       name="hps_io_usb0_data0"
       direction="bidir"
       role="usb0_data0"
       width="1" />
   <port
       name="hps_io_usb0_data1"
       direction="bidir"
       role="usb0_data1"
       width="1" />
   <port name="hps_io_usb0_nxt" direction="input" role="usb0_nxt" width="1" />
   <port
       name="hps_io_usb0_data2"
       direction="bidir"
       role="usb0_data2"
       width="1" />
   <port
       name="hps_io_usb0_data3"
       direction="bidir"
       role="usb0_data3"
       width="1" />
   <port
       name="hps_io_usb0_data4"
       direction="bidir"
       role="usb0_data4"
       width="1" />
   <port
       name="hps_io_usb0_data5"
       direction="bidir"
       role="usb0_data5"
       width="1" />
   <port
       name="hps_io_usb0_data6"
       direction="bidir"
       role="usb0_data6"
       width="1" />
   <port
       name="hps_io_usb0_data7"
       direction="bidir"
       role="usb0_data7"
       width="1" />
   <port
       name="hps_io_emac0_tx_clk"
       direction="output"
       role="emac0_tx_clk"
       width="1" />
   <port
       name="hps_io_emac0_tx_ctl"
       direction="output"
       role="emac0_tx_ctl"
       width="1" />
   <port
       name="hps_io_emac0_rx_clk"
       direction="input"
       role="emac0_rx_clk"
       width="1" />
   <port
       name="hps_io_emac0_rx_ctl"
       direction="input"
       role="emac0_rx_ctl"
       width="1" />
   <port
       name="hps_io_emac0_txd0"
       direction="output"
       role="emac0_txd0"
       width="1" />
   <port
       name="hps_io_emac0_txd1"
       direction="output"
       role="emac0_txd1"
       width="1" />
   <port
       name="hps_io_emac0_rxd0"
       direction="input"
       role="emac0_rxd0"
       width="1" />
   <port
       name="hps_io_emac0_rxd1"
       direction="input"
       role="emac0_rxd1"
       width="1" />
   <port
       name="hps_io_emac0_txd2"
       direction="output"
       role="emac0_txd2"
       width="1" />
   <port
       name="hps_io_emac0_txd3"
       direction="output"
       role="emac0_txd3"
       width="1" />
   <port
       name="hps_io_emac0_rxd2"
       direction="input"
       role="emac0_rxd2"
       width="1" />
   <port
       name="hps_io_emac0_rxd3"
       direction="input"
       role="emac0_rxd3"
       width="1" />
   <port
       name="hps_io_mdio0_mdio"
       direction="bidir"
       role="mdio0_mdio"
       width="1" />
   <port name="hps_io_mdio0_mdc" direction="output" role="mdio0_mdc" width="1" />
   <port name="hps_io_uart1_tx" direction="output" role="uart1_tx" width="1" />
   <port name="hps_io_uart1_rx" direction="input" role="uart1_rx" width="1" />
   <port name="hps_io_i2c1_sda" direction="bidir" role="i2c1_sda" width="1" />
   <port name="hps_io_i2c1_scl" direction="bidir" role="i2c1_scl" width="1" />
   <port name="hps_io_gpio28" direction="bidir" role="gpio28" width="1" />
   <port name="hps_io_gpio34" direction="bidir" role="gpio34" width="1" />
   <port name="hps_io_gpio40" direction="bidir" role="gpio40" width="1" />
   <port name="hps_io_gpio41" direction="bidir" role="gpio41" width="1" />
  </interface>
  <interface name="fpga2hps_interrupt_irq1" kind="interrupt" start="1">
   <property name="associatedAddressablePoint" value="" />
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="irqMap" value="" />
   <property name="irqScheme" value="INDIVIDUAL_REQUESTS" />
   <port
       name="fpga2hps_interrupt_irq1_irq"
       direction="input"
       role="irq"
       width="32" />
  </interface>
  <interface name="fpga2hps_interrupt_irq0" kind="interrupt" start="1">
   <property name="associatedAddressablePoint" value="" />
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="irqMap" value="" />
   <property name="irqScheme" value="INDIVIDUAL_REQUESTS" />
   <port
       name="fpga2hps_interrupt_irq0_irq"
       direction="input"
       role="irq"
       width="32" />
  </interface>
  <interface name="f2sdram_axi_clock" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="f2sdram_axi_clock_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="f2sdram_axi_reset" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port
       name="f2sdram_axi_reset_reset"
       direction="input"
       role="reset"
       width="1" />
  </interface>
  <interface name="f2sdram" kind="axi4" start="0">
   <property name="associatedClock" value="f2sdram_axi_clock" />
   <property name="associatedReset" value="f2sdram_axi_reset" />
   <property name="optionalAssociatedReset" value="false" />
   <property name="trustzoneAware" value="true" />
   <property name="wakeupSignals" value="false" />
   <property name="uniqueIdSupport" value="false" />
   <property name="poison" value="false" />
   <property name="traceSignals" value="false" />
   <property name="isTranslator" value="false" />
   <property name="maximumOutstandingReads" value="1" />
   <property name="maximumOutstandingWrites" value="1" />
   <property name="maximumOutstandingTransactions" value="1" />
   <property name="dataCheck" value="false" />
   <property name="addressCheck" value="false" />
   <property name="securityAttribute" value="false" />
   <property name="userData" value="false" />
   <property name="readAcceptanceCapability" value="16" />
   <property name="writeAcceptanceCapability" value="16" />
   <property name="combinedAcceptanceCapability" value="16" />
   <property name="readDataReorderingDepth" value="1" />
   <property name="bridgesToMaster" value="" />
   <property name="dfhFeatureGuid" value="0" />
   <property name="dfhGroupId" value="0" />
   <property name="dfhParameterId" value="" />
   <property name="dfhParameterName" value="" />
   <property name="dfhParameterVersion" value="" />
   <property name="dfhParameterData" value="" />
   <property name="dfhParameterDataLength" value="" />
   <property name="dfhFeatureMajorVersion" value="0" />
   <property name="dfhFeatureMinorVersion" value="0" />
   <property name="dfhFeatureId" value="35" />
   <property name="dfhFeatureType" value="3" />
   <property name="noNarrowTransfer" value="false" />
   <port name="f2sdram_araddr" direction="input" role="araddr" width="32" />
   <port name="f2sdram_arburst" direction="input" role="arburst" width="2" />
   <port name="f2sdram_arcache" direction="input" role="arcache" width="4" />
   <port name="f2sdram_arid" direction="input" role="arid" width="5" />
   <port name="f2sdram_arlen" direction="input" role="arlen" width="8" />
   <port name="f2sdram_arlock" direction="input" role="arlock" width="1" />
   <port name="f2sdram_arprot" direction="input" role="arprot" width="3" />
   <port name="f2sdram_arqos" direction="input" role="arqos" width="4" />
   <port name="f2sdram_arready" direction="output" role="arready" width="1" />
   <port name="f2sdram_arsize" direction="input" role="arsize" width="3" />
   <port name="f2sdram_arvalid" direction="input" role="arvalid" width="1" />
   <port name="f2sdram_awaddr" direction="input" role="awaddr" width="32" />
   <port name="f2sdram_awburst" direction="input" role="awburst" width="2" />
   <port name="f2sdram_awcache" direction="input" role="awcache" width="4" />
   <port name="f2sdram_awid" direction="input" role="awid" width="5" />
   <port name="f2sdram_awlen" direction="input" role="awlen" width="8" />
   <port name="f2sdram_awlock" direction="input" role="awlock" width="1" />
   <port name="f2sdram_awprot" direction="input" role="awprot" width="3" />
   <port name="f2sdram_awqos" direction="input" role="awqos" width="4" />
   <port name="f2sdram_awready" direction="output" role="awready" width="1" />
   <port name="f2sdram_awsize" direction="input" role="awsize" width="3" />
   <port name="f2sdram_awvalid" direction="input" role="awvalid" width="1" />
   <port name="f2sdram_bid" direction="output" role="bid" width="5" />
   <port name="f2sdram_bready" direction="input" role="bready" width="1" />
   <port name="f2sdram_bresp" direction="output" role="bresp" width="2" />
   <port name="f2sdram_bvalid" direction="output" role="bvalid" width="1" />
   <port name="f2sdram_rdata" direction="output" role="rdata" width="256" />
   <port name="f2sdram_rid" direction="output" role="rid" width="5" />
   <port name="f2sdram_rlast" direction="output" role="rlast" width="1" />
   <port name="f2sdram_rready" direction="input" role="rready" width="1" />
   <port name="f2sdram_rresp" direction="output" role="rresp" width="2" />
   <port name="f2sdram_rvalid" direction="output" role="rvalid" width="1" />
   <port name="f2sdram_wdata" direction="input" role="wdata" width="256" />
   <port name="f2sdram_wlast" direction="input" role="wlast" width="1" />
   <port name="f2sdram_wready" direction="output" role="wready" width="1" />
   <port name="f2sdram_wstrb" direction="input" role="wstrb" width="32" />
   <port name="f2sdram_wvalid" direction="input" role="wvalid" width="1" />
   <port name="f2sdram_aruser" direction="input" role="aruser" width="8" />
   <port name="f2sdram_awuser" direction="input" role="awuser" width="8" />
   <port name="f2sdram_wuser" direction="input" role="wuser" width="8" />
   <port name="f2sdram_buser" direction="output" role="buser" width="8" />
   <port name="f2sdram_arregion" direction="input" role="arregion" width="4" />
   <port name="f2sdram_ruser" direction="output" role="ruser" width="8" />
   <port name="f2sdram_awregion" direction="input" role="awregion" width="4" />
  </interface>
  <interface name="io96b0_to_hps" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="io96b0_to_hps_ch0_axil_clk"
       direction="input"
       role="ch0_axil_clk"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_reset_n"
       direction="input"
       role="ch0_axil_reset_n"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_arready"
       direction="input"
       role="ch0_axil_arready"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_awready"
       direction="input"
       role="ch0_axil_awready"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_bresp"
       direction="input"
       role="ch0_axil_bresp"
       width="2" />
   <port
       name="io96b0_to_hps_ch0_axil_bvalid"
       direction="input"
       role="ch0_axil_bvalid"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_rdata"
       direction="input"
       role="ch0_axil_rdata"
       width="32" />
   <port
       name="io96b0_to_hps_ch0_axil_rresp"
       direction="input"
       role="ch0_axil_rresp"
       width="2" />
   <port
       name="io96b0_to_hps_ch0_axil_rvalid"
       direction="input"
       role="ch0_axil_rvalid"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_wready"
       direction="input"
       role="ch0_axil_wready"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_araddr"
       direction="output"
       role="ch0_axil_araddr"
       width="27" />
   <port
       name="io96b0_to_hps_ch0_axil_arvalid"
       direction="output"
       role="ch0_axil_arvalid"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_awaddr"
       direction="output"
       role="ch0_axil_awaddr"
       width="27" />
   <port
       name="io96b0_to_hps_ch0_axil_awvalid"
       direction="output"
       role="ch0_axil_awvalid"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_bready"
       direction="output"
       role="ch0_axil_bready"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_rready"
       direction="output"
       role="ch0_axil_rready"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_wdata"
       direction="output"
       role="ch0_axil_wdata"
       width="32" />
   <port
       name="io96b0_to_hps_ch0_axil_wstrb"
       direction="output"
       role="ch0_axil_wstrb"
       width="4" />
   <port
       name="io96b0_to_hps_ch0_axil_wvalid"
       direction="output"
       role="ch0_axil_wvalid"
       width="1" />
   <port
       name="io96b0_to_hps_ch0_axil_arprot"
       direction="output"
       role="ch0_axil_arprot"
       width="3" />
   <port
       name="io96b0_to_hps_ch0_axil_awprot"
       direction="output"
       role="ch0_axil_awprot"
       width="3" />
   <port
       name="io96b0_to_hps_axi4_ch0_clk"
       direction="input"
       role="axi4_ch0_clk"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_reset_n"
       direction="input"
       role="axi4_ch0_reset_n"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_arready"
       direction="input"
       role="axi4_ch0_arready"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_awready"
       direction="input"
       role="axi4_ch0_awready"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_bid"
       direction="input"
       role="axi4_ch0_bid"
       width="7" />
   <port
       name="io96b0_to_hps_axi4_ch0_bresp"
       direction="input"
       role="axi4_ch0_bresp"
       width="2" />
   <port
       name="io96b0_to_hps_axi4_ch0_bvalid"
       direction="input"
       role="axi4_ch0_bvalid"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_rdata"
       direction="input"
       role="axi4_ch0_rdata"
       width="256" />
   <port
       name="io96b0_to_hps_axi4_ch0_rid"
       direction="input"
       role="axi4_ch0_rid"
       width="7" />
   <port
       name="io96b0_to_hps_axi4_ch0_rlast"
       direction="input"
       role="axi4_ch0_rlast"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_rresp"
       direction="input"
       role="axi4_ch0_rresp"
       width="2" />
   <port
       name="io96b0_to_hps_axi4_ch0_ruser"
       direction="input"
       role="axi4_ch0_ruser"
       width="32" />
   <port
       name="io96b0_to_hps_axi4_ch0_rvalid"
       direction="input"
       role="axi4_ch0_rvalid"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_wready"
       direction="input"
       role="axi4_ch0_wready"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_araddr"
       direction="output"
       role="axi4_ch0_araddr"
       width="40" />
   <port
       name="io96b0_to_hps_axi4_ch0_arburst"
       direction="output"
       role="axi4_ch0_arburst"
       width="2" />
   <port
       name="io96b0_to_hps_axi4_ch0_arid"
       direction="output"
       role="axi4_ch0_arid"
       width="7" />
   <port
       name="io96b0_to_hps_axi4_ch0_arlen"
       direction="output"
       role="axi4_ch0_arlen"
       width="8" />
   <port
       name="io96b0_to_hps_axi4_ch0_arlock"
       direction="output"
       role="axi4_ch0_arlock"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_arqos"
       direction="output"
       role="axi4_ch0_arqos"
       width="4" />
   <port
       name="io96b0_to_hps_axi4_ch0_arsize"
       direction="output"
       role="axi4_ch0_arsize"
       width="3" />
   <port
       name="io96b0_to_hps_axi4_ch0_aruser"
       direction="output"
       role="axi4_ch0_aruser"
       width="14" />
   <port
       name="io96b0_to_hps_axi4_ch0_arvalid"
       direction="output"
       role="axi4_ch0_arvalid"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_awaddr"
       direction="output"
       role="axi4_ch0_awaddr"
       width="40" />
   <port
       name="io96b0_to_hps_axi4_ch0_awburst"
       direction="output"
       role="axi4_ch0_awburst"
       width="2" />
   <port
       name="io96b0_to_hps_axi4_ch0_awid"
       direction="output"
       role="axi4_ch0_awid"
       width="7" />
   <port
       name="io96b0_to_hps_axi4_ch0_awlen"
       direction="output"
       role="axi4_ch0_awlen"
       width="8" />
   <port
       name="io96b0_to_hps_axi4_ch0_awlock"
       direction="output"
       role="axi4_ch0_awlock"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_awqos"
       direction="output"
       role="axi4_ch0_awqos"
       width="4" />
   <port
       name="io96b0_to_hps_axi4_ch0_awsize"
       direction="output"
       role="axi4_ch0_awsize"
       width="3" />
   <port
       name="io96b0_to_hps_axi4_ch0_awuser"
       direction="output"
       role="axi4_ch0_awuser"
       width="14" />
   <port
       name="io96b0_to_hps_axi4_ch0_awvalid"
       direction="output"
       role="axi4_ch0_awvalid"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_bready"
       direction="output"
       role="axi4_ch0_bready"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_rready"
       direction="output"
       role="axi4_ch0_rready"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_wdata"
       direction="output"
       role="axi4_ch0_wdata"
       width="256" />
   <port
       name="io96b0_to_hps_axi4_ch0_wlast"
       direction="output"
       role="axi4_ch0_wlast"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_wstrb"
       direction="output"
       role="axi4_ch0_wstrb"
       width="32" />
   <port
       name="io96b0_to_hps_axi4_ch0_wuser"
       direction="output"
       role="axi4_ch0_wuser"
       width="32" />
   <port
       name="io96b0_to_hps_axi4_ch0_wvalid"
       direction="output"
       role="axi4_ch0_wvalid"
       width="1" />
   <port
       name="io96b0_to_hps_axi4_ch0_arprot"
       direction="output"
       role="axi4_ch0_arprot"
       width="3" />
   <port
       name="io96b0_to_hps_axi4_ch0_awprot"
       direction="output"
       role="axi4_ch0_awprot"
       width="3" />
  </interface>
 </perimeter>
 <entity kind="agilex_hps" version="1.0" name="agilex_hps">
  <parameter name="AUTO_F2SDRAM_AXI_CLOCK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_HPS2FPGA_ADDRESS_MAP" value="" />
  <parameter name="AUTO_LWHPS2FPGA_AXI_CLOCK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_LWHPS2FPGA_ADDRESS_MAP" value="" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_HPS2FPGA_AXI_CLOCK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_F2SDRAM_CPU_INFO_ID" value="" />
  <parameter name="AUTO_LWHPS2FPGA_ADDRESS_WIDTH" value="-1" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="AUTO_HPS2FPGA_AXI_CLOCK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_FPGA2HPS_INTERRUPT_IRQ0_INTERRUPTS_USED" value="-1" />
  <parameter name="AUTO_HPS2FPGA_AXI_CLOCK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_HPS2FPGA_ADDRESS_WIDTH" value="-1" />
  <parameter name="AUTO_F2SDRAM_AXI_CLOCK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_F2SDRAM_AXI_CLOCK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_FPGA2HPS_INTERRUPT_IRQ1_INTERRUPTS_USED" value="-1" />
  <parameter name="AUTO_LWHPS2FPGA_AXI_CLOCK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_LWHPS2FPGA_AXI_CLOCK_RESET_DOMAIN" value="-1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/synth/agilex_hps.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/synth/agilex_hps.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps.ip" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/intel_hps/sm/intel_soc_sundancemesa/intel_soc_sundancemesa_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.tclelement.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.generator.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.ddmwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcdocument.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.ngpd.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.shared.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jacl1.3.2a.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-text-1.10.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-lang3-3.12.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/guava-32.0.1-jre.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jfreechart-1.5.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-swing-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-common-1.1.2_20c.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/bare-bones-browser-launch-3.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-jxc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-xjc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/codemodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/dtd-parser.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/FastInfoset.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-tools.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/javax.activation-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/relaxng-datatype.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/rngom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/stax-ex.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/txw2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/xsom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/failureaccess-1.0.1.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/listenablefuture-9999.0-empty-to-avoid-conflict-with-guava.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jsr305-3.0.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/checker-qual-3.33.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/j2objc-annotations-2.8.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-core-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-core-1.1.2_20c.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-io-2.13.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.model.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.privateinterfaces.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/antlr4-runtime-4.7.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopclibrary.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.module.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.dni.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.build.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.hypericonnect.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.cmsis.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlcomponent.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/intel_hps/sm/hps/intel_hps_sundancemesa_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.tclelement.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.generator.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.ddmwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcdocument.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.ngpd.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.shared.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jacl1.3.2a.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-text-1.10.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-lang3-3.12.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/guava-32.0.1-jre.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jfreechart-1.5.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-swing-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-common-1.1.2_20c.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/bare-bones-browser-launch-3.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-jxc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-xjc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/codemodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/dtd-parser.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/FastInfoset.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-tools.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/javax.activation-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/relaxng-datatype.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/rngom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/stax-ex.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/txw2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/xsom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/failureaccess-1.0.1.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/listenablefuture-9999.0-empty-to-avoid-conflict-with-guava.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jsr305-3.0.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/checker-qual-3.33.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/j2objc-annotations-2.8.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-core-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-core-1.1.2_20c.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-io-2.13.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.model.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.privateinterfaces.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/antlr4-runtime-4.7.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopclibrary.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.module.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.dni.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.build.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.hypericonnect.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.cmsis.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlcomponent.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/intel_hps/sm/mpfe/intel_mpfe_sundancemesa_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps"</message>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps_intel_agilex_5_soc_1400_kdgjumq"</message>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps_intel_sundancemesa_hps_100_soonmgi"</message>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps_intel_sundancemesa_mpfe_100_d7hziti"</message>
  </messages>
 </entity>
 <entity
   kind="intel_agilex_5_soc"
   version="14.0.0"
   name="agilex_hps_intel_agilex_5_soc_1400_kdgjumq">
  <parameter
     name="HPS_HANDOFF_OPTION_STRING"
     value="    HPS_PRESENT: true
    HPS_DDR_PRESENT: true
    hps_wachdog_expiration: COLD_RESET
    cores_power_state: 15
    boot_core: 0
    l3_cache_size: HALF_ON
    f2soc_intfcsel: DISABLE
    f2sdram_intfcsel: ENABLE" />
  <parameter name="REG_pin33_sel" value="8" />
  <parameter name="REG_pin25_sel" value="3" />
  <parameter name="ED_h2f_packet_size" value="1" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="REG_nocdiv_l4mpclk" value="1" />
  <parameter name="NOC_clk_periph_l4_div" value="2" />
  <parameter name="REG_io41_output_delay" value="0" />
  <parameter
     name="Periph_clk_frequencies"
     value="250,250,250,400.00,200.00,100.00,500.00,20.00" />
  <parameter name="IO_OUTPUT_DELAY47" value="-1" />
  <parameter name="REG_mfdbck_fdiv" value="0" />
  <parameter name="IO_OUTPUT_DELAY46" value="-1" />
  <parameter name="REG_pin9_sel" value="1" />
  <parameter name="MPLL_VCO_M" value="128" />
  <parameter name="MPLL_VCO_N" value="1" />
  <parameter name="SPIS1_Mode" value="N/A" />
  <parameter name="IO_INPUT_DELAY47" value="-1" />
  <parameter name="MPU_clk_periph_div" value="4" />
  <parameter name="IO_INPUT_DELAY42" value="-1" />
  <parameter name="REG_pin17_sel" value="0" />
  <parameter name="IO_INPUT_DELAY41" value="-1" />
  <parameter name="DMA_PeriphID" value="0,1,2,3,4,5,6,7" />
  <parameter name="IO_INPUT_DELAY40" value="-1" />
  <parameter name="IO_INPUT_DELAY46" value="-1" />
  <parameter name="IO_INPUT_DELAY45" value="-1" />
  <parameter name="IO_INPUT_DELAY44" value="-1" />
  <parameter name="Periph_usb_src_override" value="3" />
  <parameter name="IO_INPUT_DELAY43" value="-1" />
  <parameter name="REG_pin2_sel" value="1" />
  <parameter name="REG_mpllm_mdiv" value="128" />
  <parameter name="IO_OUTPUT_DELAY39" value="-1" />
  <parameter name="IO_OUTPUT_DELAY38" value="-1" />
  <parameter name="REG_mpllglob_arefclkdiv" value="1" />
  <parameter name="IO_OUTPUT_DELAY37" value="-1" />
  <parameter name="IO_OUTPUT_DELAY36" value="-1" />
  <parameter name="IO_OUTPUT_DELAY35" value="-1" />
  <parameter name="IO_INPUT_DELAY39" value="-1" />
  <parameter name="IO_OUTPUT_DELAY45" value="-1" />
  <parameter
     name="Periph_clk_sources"
     value="PeriphC3,PeriphC3,PeriphC3,MainC3,MainC3,GDB Free,PeriphC3,MainC3" />
  <parameter name="IO_INPUT_DELAY38" value="-1" />
  <parameter name="IO_OUTPUT_DELAY44" value="-1" />
  <parameter name="IO_INPUT_DELAY37" value="-1" />
  <parameter name="IO_OUTPUT_DELAY43" value="-1" />
  <parameter name="H2F_IRQ_SPIM0_Enable" value="false" />
  <parameter name="IO_INPUT_DELAY36" value="-1" />
  <parameter name="IO_OUTPUT_DELAY42" value="-1" />
  <parameter name="FPGA_EMAC1_md_clk_mhz" value="2.5" />
  <parameter name="UART1_Mode" value="No_flow_control" />
  <parameter name="IO_OUTPUT_DELAY41" value="-1" />
  <parameter name="REG_pin10_sel" value="1" />
  <parameter name="REG_io2_output_delay" value="0" />
  <parameter name="IO_OUTPUT_DELAY40" value="-1" />
  <parameter name="REG_io40_output_delay" value="0" />
  <parameter name="IO_INPUT_DELAY31" value="-1" />
  <parameter name="IO_INPUT_DELAY30" value="-1" />
  <parameter name="IO_INPUT_DELAY35" value="-1" />
  <parameter name="IO_INPUT_DELAY34" value="-1" />
  <parameter name="REG_io1_output_delay" value="0" />
  <parameter name="IO_INPUT_DELAY33" value="-1" />
  <parameter name="IO_INPUT_DELAY32" value="-1" />
  <parameter name="REG_pin41_sel" value="8" />
  <parameter name="REG_emacbctr_cnt" value="9" />
  <parameter name="I2C0_Mode" value="N/A" />
  <parameter name="Rst_hps_warm_en" value="false" />
  <parameter name="ED_lwh2f_packet_size" value="1" />
  <parameter name="EMAC2_PTP" value="false" />
  <parameter name="I3C1_Mode" value="N/A" />
  <parameter name="H2F_IRQ_USB1_Enable" value="false" />
  <parameter name="Periph_usb_freq_override" value="20.0" />
  <parameter name="REG_emacctl_emac0sel" value="0" />
  <parameter name="MPFE_f2s_data_width" value="0" />
  <parameter name="H2F_IRQ_DMA_Enable1" value="false" />
  <parameter name="H2F_IRQ_DMA_Enable0" value="false" />
  <parameter name="H2F_IRQ_SDMMC_Enable" value="false" />
  <parameter name="ED_en_synth_gen" value="false" />
  <parameter name="USB0_PinMuxing" value="IO" />
  <parameter name="MPU_clk_ccu_div" value="2" />
  <parameter name="MPFE_f2s_mode" value="ace5lite" />
  <parameter name="hps_ioa10_opd_en" value="false" />
  <parameter name="hps_ioa14_opd_en" value="false" />
  <parameter name="hps_ioa18_opd_en" value="false" />
  <parameter name="REG_pinmux_spim0_usefpga_sel" value="0" />
  <parameter name="hps_iob18_opd_en" value="false" />
  <parameter name="H2F_IRQ_SPIS0_Enable" value="false" />
  <parameter name="TPIU_Select" value="HPS Clock Manager" />
  <parameter name="REG_gpiodiv_val" value="1" />
  <parameter name="REG_pinmux_i2c_emac1_usefpga_sel" value="0" />
  <parameter name="hps_iob9_opd_en" value="false" />
  <parameter name="device_trait_iobank_rev" value="IO96B_REVB1" />
  <parameter name="REG_pin34_sel" value="8" />
  <parameter name="FPGA_SPIM1_sclk_mhz" value="125.0" />
  <parameter name="REG_io31_output_delay" value="0" />
  <parameter name="hps_iob10_opd_en" value="false" />
  <parameter name="hps_iob13_opd_en" value="false" />
  <parameter name="f2s_data_width" value="0" />
  <parameter name="SPIS1_PinMuxing" value="Unused" />
  <parameter name="Periph_gpio_freq_override" value="400.0" />
  <parameter name="JAVA_ERROR_MSG" value="" />
  <parameter name="REG_pinmux_uart1_usefpga_sel" value="0" />
  <parameter name="hps_iob1_opd_en" value="false" />
  <parameter name="ED_f2sdram_connectivity" value="1" />
  <parameter name="Pwr_override_cache_size" value="false" />
  <parameter name="H2F_IRQ_I2CEMAC2_Enable" value="false" />
  <parameter name="MPU_core3_freq_override_mhz" value="800.0" />
  <parameter name="User0_clk_src_select" value="7" />
  <parameter
     name="MPU_clk_outputs"
     value="MPU,MPU CCU,MPU Periph,Core0|Core1,Core2,Core3" />
  <parameter name="SPIM0_PinMuxing" value="Unused" />
  <parameter name="REG_pin18_sel" value="0" />
  <parameter name="H2F_IRQ_I3C0_Enable" value="false" />
  <parameter name="REG_pin40_sel" value="8" />
  <parameter name="H2F_IRQ_L4Timer_Enable" value="false" />
  <parameter name="REG_io4_output_delay" value="0" />
  <parameter name="MPU_core01_freq_override_mhz" value="800.0" />
  <parameter name="REG_nocdiv_cspdbgclk" value="2" />
  <parameter name="REG_pin3_sel" value="1" />
  <parameter name="REG_io3_output_delay" value="0" />
  <parameter name="FPGA_SPIM0_sclk_mhz" value="125.0" />
  <parameter name="REG_emacbctr_src" value="1" />
  <parameter name="REG_io0_output_delay" value="0" />
  <parameter name="REG_pin24_sel" value="3" />
  <parameter name="REG_ppllglob_psrc" value="0" />
  <parameter name="hps_ioa15_opd_en" value="false" />
  <parameter name="FPGA_EMAC_PTP_clk_en" value="true" />
  <parameter name="hps_iob24_opd_en" value="false" />
  <parameter name="NOC_clk_cs_trace_div" value="4" />
  <parameter name="REG_io44_output_delay" value="0" />
  <parameter name="ED_f2sdram_data_width" value="256" />
  <parameter name="I2C0_PinMuxing" value="Unused" />
  <parameter name="hps_iob21_opd_en" value="false" />
  <parameter name="REG_pin39_sel" value="5" />
  <parameter name="REG_io30_output_delay" value="0" />
  <parameter name="OPT_coreboot_sel" value="0" />
  <parameter name="REG_mpllc0_div" value="4" />
  <parameter name="ED_lwh2f_traffic_pattern" value="0" />
  <parameter name="FPGA_EMAC2_tx_clk_en" value="true" />
  <parameter name="ED_h2f_data_width" value="128" />
  <parameter name="hps_iob4_opd_en" value="false" />
  <parameter name="ED_en_sim_gen" value="true" />
  <parameter name="REG_pinmux_mdio0_usefpga_sel" value="0" />
  <parameter
     name="NOC_clk_sources"
     value="MainC3,NOC,NOC,NOC,L4Periph,NOC,NOC,NOC" />
  <parameter name="Rst_watchdog_en" value="false" />
  <parameter name="REG_ppllglob_arefclkdiv" value="1" />
  <parameter name="H2F_IRQ_UART1_Enable" value="false" />
  <parameter name="Periph_psi_freq_override" value="500.0" />
  <parameter name="hps_ioa3_opd_en" value="false" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="REG_pinmux_mdio2_usefpga_sel" value="0" />
  <parameter name="REG_nocdiv_l4spclk" value="2" />
  <parameter name="LWH2F_Address_Width" value="29" />
  <parameter name="H2F_Address_Width" value="38" />
  <parameter name="REG_pin8_sel" value="1" />
  <parameter name="FPGA_EMAC1_gtx_clk_mhz" value="125.0" />
  <parameter name="REG_io20_output_delay" value="0" />
  <parameter
     name="HPS_HANDOFF_STRING"
     value="pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 9
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 4
}
pinmux_select {
  value: 4
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 5
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 117
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 117
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocclk.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.cspdbgclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.cstraceclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.csclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.mpuperiphdiv&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.ccudiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.softphydiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4spclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4mpclk&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4sysfreeclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.modclkdiv&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.fastrefclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.psrc&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.drefclkdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.arefclkdiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.fdbck.fdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllc0.div&quot;
  reg_value: 4
}
reg {
  reg_name: &quot;mainpllgrp.pllc1.div&quot;
  reg_value: 4
}
reg {
  reg_name: &quot;mainpllgrp.pllc2.div&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;mainpllgrp.pllc3.div&quot;
  reg_value: 8
}
reg {
  reg_name: &quot;mainpllgrp.pllm.mdiv&quot;
  reg_value: 128
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac0sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac1sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac2sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.modclkdiv&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllglob.fstrefclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.psrc&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.drefclkdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.arefclkdiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;perpllgrp.fdbck.fdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllc0.div&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllc1.div&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllc2.div&quot;
  reg_value: 125
}
reg {
  reg_name: &quot;perpllgrp.pllc3.div&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;perpllgrp.pllm.mdiv&quot;
  reg_value: 120
}
reg {
  reg_name: &quot;ctl.emacactr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacactr.cnt&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacbctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacbctr.cnt&quot;
  reg_value: 9
}
reg {
  reg_name: &quot;ctl.emacptpctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.emacptpctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.gpiodbctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.gpiodbctr.cnt&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;perpllgrp.gpiodiv.gpiodbclk&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser0ctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser0ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.s2fuser1ctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser1ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.psirefctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.psirefctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.usb31ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.usb31ctr.cnt&quot;
  reg_value: 19
}
reg {
  reg_name: &quot;ctl.dsuctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.dsuctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core01ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core01ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core23ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core2ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core3ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;hps_osc_clk_hz&quot;
  reg_value: 25000000
}
reg {
  reg_name: &quot;fpga_clk_hz&quot;
  reg_value: 125000000
}
" />
  <parameter name="REG_io45_output_delay" value="0" />
  <parameter name="NAND_Mode" value="N/A" />
  <parameter name="TRACE_Mode" value="N/A" />
  <parameter name="REG_io0_input_delay" value="0" />
  <parameter name="REG_ppllglob_fastrefclk" value="0" />
  <parameter name="ED_f2sdram_packet_size" value="1" />
  <parameter name="REG_pin43_sel" value="8" />
  <parameter name="MPFE_f2sdram_data_width" value="256" />
  <parameter name="SDMMC_PinMuxing" value="IO" />
  <parameter name="hps_ioa4_opd_en" value="false" />
  <parameter name="REG_io8_input_delay" value="0" />
  <parameter name="REG_psirefctr_src" value="1" />
  <parameter name="REG_pin35_sel" value="8" />
  <parameter name="REG_pin23_sel" value="0" />
  <parameter name="REG_pinmux_emac2_usefpga_sel" value="0" />
  <parameter name="SPIS0_Mode" value="N/A" />
  <parameter name="REG_pinmux_sdmmc_usefpga_sel" value="0" />
  <parameter name="REG_io1_input_delay" value="0" />
  <parameter name="REG_io9_input_delay" value="0" />
  <parameter name="EMIF_AXI_Enable" value="true" />
  <parameter name="REG_io4_input_delay" value="0" />
  <parameter name="EMAC2_PPS_Enable" value="false" />
  <parameter name="REG_pin4_sel" value="1" />
  <parameter name="MPLL_Override" value="true" />
  <parameter name="REG_io5_input_delay" value="0" />
  <parameter name="REG_s2fuser1ctr_src" value="1" />
  <parameter name="REG_pin38_sel" value="5" />
  <parameter name="REG_nocdiv_softphydiv" value="0" />
  <parameter name="PLL_CLK3" value="Unused" />
  <parameter name="PLL_CLK4" value="Unused" />
  <parameter name="REG_pin20_sel" value="0" />
  <parameter name="hps_iob22_opd_en" value="false" />
  <parameter name="MPU_core23_src_override" value="0" />
  <parameter name="Rst_sdm_wd_config" value="0" />
  <parameter name="STM_Enable" value="false" />
  <parameter name="REG_ppllglob_modclkdiv" value="5" />
  <parameter name="REG_pin7_sel" value="1" />
  <parameter name="MPFE_f2s_address_width" value="32" />
  <parameter
     name="NOC_clk_frequencies"
     value="400.0,100.0,200.0,100.0,200.0,400.0,100.0,100.0" />
  <parameter name="REG_io35_output_delay" value="0" />
  <parameter name="f2s_address_width" value="32" />
  <parameter name="Periph_emaca_src_override" value="7" />
  <parameter
     name="NOC_clk_outputs"
     value="NOC,L4 Free,L4 Peripheral,L4 Slow Peripheral,SoftPHY,CoreSight,CoreSight Debug APB,CoreSight Trace IO" />
  <parameter name="EMAC0_PTP" value="false" />
  <parameter name="UART0_Mode" value="N/A" />
  <parameter name="H2F_IRQ_EMAC0_Enable" value="false" />
  <parameter name="Periph_clk_override" value="false" />
  <parameter name="CM_Mode" value="N/A" />
  <parameter name="MPLL_VCO_fdiv" value="0" />
  <parameter name="I2CEMAC1_Mode" value="N/A" />
  <parameter name="REG_io42_input_delay" value="0" />
  <parameter name="REG_io47_output_delay" value="0" />
  <parameter name="ED_f2h_addr_width" value="38" />
  <parameter name="hps_iob17_opd_en" value="false" />
  <parameter name="SPIM1_PinMuxing" value="Unused" />
  <parameter name="REG_pin42_sel" value="8" />
  <parameter name="REG_io46_input_delay" value="0" />
  <parameter name="USB0_Mode" value="default" />
  <parameter name="REG_pinmux_i2c_emac2_usefpga_sel" value="0" />
  <parameter name="REG_pin16_sel" value="0" />
  <parameter name="REG_io16_output_delay" value="0" />
  <parameter name="H2F_IRQ_I3C1_Enable" value="false" />
  <parameter name="EMAC1_Mode" value="N/A" />
  <parameter name="hps_iob11_opd_en" value="false" />
  <parameter name="hps_iob12_opd_en" value="false" />
  <parameter name="MPU_Events_Enable" value="false" />
  <parameter name="REG_hps_osc_hz" value="25000000" />
  <parameter name="REG_core01ctr_src" value="0" />
  <parameter name="REG_pinmux_uart0_usefpga_sel" value="0" />
  <parameter name="MPU_core2_freq_override_mhz" value="800.0" />
  <parameter name="JTAG_Enable" value="false" />
  <parameter name="MPFE_f2s_SMMU" value="0" />
  <parameter name="REG_pin22_sel" value="0" />
  <parameter name="FPGA_I2CEMAC0_clk_mhz" value="125.0" />
  <parameter name="REG_pin36_sel" value="4" />
  <parameter name="Pwr_cpu_app_select" value="0" />
  <parameter name="hps_iob5_opd_en" value="false" />
  <parameter name="REG_mpllglob_modclkdiv" value="6" />
  <parameter name="H2F_IRQ_GPIO1_Enable" value="false" />
  <parameter
     name="MPU_clk_frequencies"
     value="533.33,266.665,133.3325,800.00,800.00,800.00" />
  <parameter name="ED_f2sdram_traffic_pattern" value="0" />
  <parameter name="hps_ioa24_opd_en" value="false" />
  <parameter name="ED_h2f_traffic_pattern" value="0" />
  <parameter name="NOC_clk_phy_div" value="1" />
  <parameter name="REG_psirefctr_cnt" value="0" />
  <parameter name="PLL_CLK1" value="Unused" />
  <parameter name="H2F_IRQ_NAND_Enable" value="false" />
  <parameter name="PLL_CLK2" value="Unused" />
  <parameter name="hps_ioa19_opd_en" value="false" />
  <parameter name="REG_io32_input_delay" value="0" />
  <parameter name="PLL_CLK0" value="Unused" />
  <parameter name="hps_ioa13_opd_en" value="false" />
  <parameter name="REG_io46_output_delay" value="0" />
  <parameter name="ED_lwh2f_connectivity" value="1" />
  <parameter name="REG_pin21_sel" value="0" />
  <parameter name="NOC_clk_cs_debug_div" value="4" />
  <parameter
     name="Periph_clk_outputs"
     value="EMAC0,EMAC1,EMAC2,EMAC PTP,GDB Free,GPIO Debounce,PSI Ref,USB 3.1" />
  <parameter name="REG_pin6_sel" value="1" />
  <parameter name="EMAC1_PTP" value="false" />
  <parameter name="Periph_psi_src_override" value="7" />
  <parameter name="ED_f2h_data_width" value="256" />
  <parameter name="REG_pinmux_jtag_usefpga_sel" value="0" />
  <parameter name="REG_io36_output_delay" value="0" />
  <parameter name="F2H_IRQ_Enable" value="true" />
  <parameter name="REG_pinmux_mdio1_usefpga_sel" value="0" />
  <parameter name="FPGA_I2C0_sclk_mhz" value="125.0" />
  <parameter name="MPLL_C1_Override_mhz" value="800.0" />
  <parameter name="f2sdram_SMMU" value="false" />
  <parameter name="ED_en_questa" value="true" />
  <parameter name="Pwr_default_mpu_l3_cache_size" value="1MB" />
  <parameter name="H2F_IRQ_SYSTimer_Enable" value="false" />
  <parameter name="FPGA_EMAC2_gtx_clk_mhz" value="125.0" />
  <parameter name="REG_pin15_sel" value="0" />
  <parameter name="REG_io20_input_delay" value="0" />
  <parameter name="User0_clk_freq" value="500.0" />
  <parameter name="ED_en_vcsmx" value="true" />
  <parameter name="REG_io22_input_delay" value="0" />
  <parameter name="REG_io23_input_delay" value="0" />
  <parameter name="REG_io24_input_delay" value="0" />
  <parameter name="REG_pinmux_spis1_usefpga_sel" value="0" />
  <parameter name="PPLL_C1_Override_mhz" value="600.0" />
  <parameter name="REG_io25_input_delay" value="0" />
  <parameter name="IO_INPUT_DELAY5" value="-1" />
  <parameter name="REG_io28_input_delay" value="0" />
  <parameter name="IO_INPUT_DELAY6" value="-1" />
  <parameter name="IO_INPUT_DELAY7" value="-1" />
  <parameter name="REG_io26_output_delay" value="0" />
  <parameter name="IO_INPUT_DELAY8" value="-1" />
  <parameter name="IO_INPUT_DELAY9" value="-1" />
  <parameter name="REG_io26_input_delay" value="0" />
  <parameter name="REG_io9_output_delay" value="0" />
  <parameter name="REG_io27_input_delay" value="0" />
  <parameter name="REG_io14_output_delay" value="0" />
  <parameter name="REG_core23ctr_src" value="0" />
  <parameter name="Pwr_a76_core3_on" value="true" />
  <parameter name="REG_pinmux_spis0_usefpga_sel" value="0" />
  <parameter name="REG_pinmux_i2c1_usefpga_sel" value="0" />
  <parameter name="NOC_clk_free_l4_div" value="4" />
  <parameter name="REG_io29_input_delay" value="0" />
  <parameter name="NOC_clk_cs_div" value="1" />
  <parameter name="REG_pinmux_i2c0_usefpga_sel" value="0" />
  <parameter name="REG_core01ctr_cnt" value="0" />
  <parameter name="FPGA_EMAC0_md_clk_mhz" value="2.5" />
  <parameter name="f2sdram_address_width" value="32" />
  <parameter name="IO_INPUT_DELAY0" value="-1" />
  <parameter name="IO_INPUT_DELAY1" value="-1" />
  <parameter name="IO_INPUT_DELAY2" value="-1" />
  <parameter name="IO_INPUT_DELAY3" value="-1" />
  <parameter name="IO_INPUT_DELAY4" value="-1" />
  <parameter name="REG_dsuctr_cnt" value="0" />
  <parameter name="H2F_IRQ_UART0_Enable" value="false" />
  <parameter name="REG_pin37_sel" value="4" />
  <parameter name="SPIM1_Mode" value="N/A" />
  <parameter name="H2F_IRQ_EMAC1_Enable" value="false" />
  <parameter name="REG_io21_input_delay" value="0" />
  <parameter name="REG_io10_input_delay" value="0" />
  <parameter name="MPFE_ATB_Enable" value="false" />
  <parameter name="REG_io11_input_delay" value="0" />
  <parameter name="REG_io33_input_delay" value="0" />
  <parameter name="REG_io34_input_delay" value="0" />
  <parameter name="REG_io12_input_delay" value="0" />
  <parameter name="REG_pin29_sel" value="3" />
  <parameter name="device_family" value="Agilex 5" />
  <parameter name="MPLL_Outputs" value="VCO,C0,C1,C2,C3" />
  <parameter name="PPLL_C0_Override_mhz" value="600.0" />
  <parameter name="REG_io35_input_delay" value="0" />
  <parameter name="hps_iob23_opd_en" value="false" />
  <parameter name="REG_pin5_sel" value="1" />
  <parameter name="REG_io13_input_delay" value="0" />
  <parameter name="REG_io15_input_delay" value="0" />
  <parameter name="REG_io15_output_delay" value="0" />
  <parameter name="REG_io36_input_delay" value="0" />
  <parameter name="PPLL_C2_Override_mhz" value="24.0" />
  <parameter name="REG_io14_input_delay" value="117" />
  <parameter name="REG_io25_output_delay" value="0" />
  <parameter name="PPLL_VCO_Fref_mhz" value="25.0" />
  <parameter name="REG_io38_input_delay" value="0" />
  <parameter name="REG_io39_input_delay" value="0" />
  <parameter name="ED_f2h_connectivity" value="1" />
  <parameter name="REG_io17_input_delay" value="0" />
  <parameter name="REG_io19_input_delay" value="0" />
  <parameter name="REG_io27_output_delay" value="0" />
  <parameter name="REG_ppllc1_div" value="5" />
  <parameter name="ED_en_xcelium" value="true" />
  <parameter name="REG_io37_input_delay" value="0" />
  <parameter name="REG_io16_input_delay" value="0" />
  <parameter name="REG_io8_output_delay" value="0" />
  <parameter name="REG_io13_output_delay" value="0" />
  <parameter name="MPFE_f2sdram_address_width" value="32" />
  <parameter name="MPLL_VCO_Fref_mhz" value="25.0" />
  <parameter name="EMIF_Topology" value="1" />
  <parameter name="REG_io18_input_delay" value="0" />
  <parameter name="REG_pin14_sel" value="0" />
  <parameter name="REG_pin44_sel" value="8" />
  <parameter name="hps_iob2_opd_en" value="false" />
  <parameter name="USB1_Mode" value="N/A" />
  <parameter name="hps_iob6_opd_en" value="false" />
  <parameter name="hps_ioa1_opd_en" value="false" />
  <parameter name="Periph_clk_emac0_sel" value="250" />
  <parameter name="MPLL_C2_Override_mhz" value="533.33" />
  <parameter name="hps_ioa5_opd_en" value="false" />
  <parameter name="hps_ioa9_opd_en" value="false" />
  <parameter name="REG_mpllc3_div" value="8" />
  <parameter name="REG_pinmux_i3c1_usefpga_sel" value="0" />
  <parameter name="MPLL_C0_Override_mhz" value="800.0" />
  <parameter name="REG_pinmux_i3c0_usefpga_sel" value="0" />
  <parameter name="H2F_IRQ_I2CEMAC1_Enable" value="false" />
  <parameter name="User0_clk_enable" value="false" />
  <parameter name="FPGA_I3C1_sclk_mhz" value="125.0" />
  <parameter name="REG_io37_output_delay" value="0" />
  <parameter name="Pwr_a76_core2_on" value="true" />
  <parameter name="REG_io39_output_delay" value="0" />
  <parameter name="REG_s2fuser0ctr_src" value="1" />
  <parameter name="REG_s2fuser1ctr_cnt" value="0" />
  <parameter name="REG_io41_input_delay" value="0" />
  <parameter name="REG_io96b_csr" value="0" />
  <parameter name="hps_iob16_opd_en" value="false" />
  <parameter name="MPFE_Lite_is_present" value="false" />
  <parameter name="REG_io45_input_delay" value="0" />
  <parameter name="PPLL_VCO_fdiv" value="0" />
  <parameter name="OPT_HPS_DDR_PRESENT" value="1" />
  <parameter name="REG_io47_input_delay" value="0" />
  <parameter name="REG_fpga_clk_hz" value="125000000" />
  <parameter name="EMAC0_PPS_Enable" value="false" />
  <parameter name="REG_io7_output_delay" value="0" />
  <parameter name="PPLL_C3_Override_mhz" value="500.0" />
  <parameter name="REG_io28_output_delay" value="0" />
  <parameter name="hps_iob15_opd_en" value="false" />
  <parameter name="SDMMC_Mode" value="4-bit" />
  <parameter name="REG_core3ctr_cnt" value="0" />
  <parameter name="Periph_emac_ptp_src_override" value="7" />
  <parameter name="FPGA_I3C0_sclk_mhz" value="125.0" />
  <parameter name="FPGA_EMAC1_tx_clk_en" value="true" />
  <parameter name="REG_periph_pwrgate" value="186" />
  <parameter name="PPLL_VCO_Override_mhz" value="3000.0" />
  <parameter name="REG_ppllglob_drefclkdiv" value="0" />
  <parameter name="OPT_corepwr_state" value="15" />
  <parameter name="hps_iob7_opd_en" value="false" />
  <parameter name="NOC_clk_slow_l4_div" value="4" />
  <parameter name="Pwr_a55_core0_1_on" value="true" />
  <parameter name="I2C1_PinMuxing" value="IO" />
  <parameter name="REG_dsuctr_src" value="0" />
  <parameter name="OPT_watchdog_reset" value="COLD" />
  <parameter name="REG_io17_output_delay" value="0" />
  <parameter name="SPIS0_PinMuxing" value="Unused" />
  <parameter name="hps_ioa20_opd_en" value="false" />
  <parameter name="REG_io43_input_delay" value="0" />
  <parameter name="REG_nocdiv_ccudiv" value="1" />
  <parameter name="ED_f2sdram_addr_width" value="40" />
  <parameter name="hps_ioa17_opd_en" value="false" />
  <parameter name="REG_pfdbck_fdiv" value="0" />
  <parameter name="REG_io31_input_delay" value="0" />
  <parameter name="I3C0_Mode" value="N/A" />
  <parameter name="REG_nocclk_src" value="0" />
  <parameter name="OPT_f2sdram_sel" value="1" />
  <parameter
     name="HPS_IO_Enable"
     value="USB0:CLK,USB0:STP,USB0:DIR,USB0:DATA0,USB0:DATA1,USB0:NXT,USB0:DATA2,USB0:DATA3,USB0:DATA4,USB0:DATA5,USB0:DATA6,USB0:DATA7,EMAC0:TX_CLK,EMAC0:TX_CTL,EMAC0:RX_CLK,EMAC0:RX_CTL,EMAC0:TXD0,EMAC0:TXD1,EMAC0:RXD0,EMAC0:RXD1,EMAC0:TXD2,EMAC0:TXD3,EMAC0:RXD2,EMAC0:RXD3,SDMMC:DATA0,SDMMC:DATA1,SDMMC:CCLK,HCLK:HPS_OSC_CLK,GPIO1:IO4,SDMMC:DATA2,SDMMC:DATA3,SDMMC:CMD,NONE,NONE,GPIO1:IO10,NONE,I2C1:SDA,I2C1:SCL,UART1:TX,UART1:RX,GPIO1:IO16,GPIO1:IO17,NONE,NONE,NONE,NONE,MDIO0:MDIO,MDIO0:MDC" />
  <parameter name="MPU_clk_override" value="true" />
  <parameter name="REG_gpiodbctr_cnt" value="1" />
  <parameter name="JAVA_WARNING_MSG" value="" />
  <parameter name="device_name" value="A5EB013BB23BE4SCS" />
  <parameter name="MPLL_C3_Override_mhz" value="400.0" />
  <parameter name="REG_pin30_sel" value="3" />
  <parameter name="USB1_PinMuxing" value="Unused" />
  <parameter name="PPLL_Frequencies" value="3000.00,600.00,600.00,24.00,500.00" />
  <parameter name="REG_ppllc0_div" value="5" />
  <parameter name="REG_nocdiv_mpuperiphdiv" value="2" />
  <parameter name="H2F_IRQ_USB0_Enable" value="false" />
  <parameter name="REG_pin13_sel" value="0" />
  <parameter name="REG_ppllm_mdiv" value="120" />
  <parameter name="REG_mpllglob_drefclkdiv" value="0" />
  <parameter name="UART1_PinMuxing" value="IO" />
  <parameter name="H2F_IRQ_GPIO0_Enable" value="false" />
  <parameter name="ED_h2f_addr_width" value="26" />
  <parameter name="REG_io34_output_delay" value="0" />
  <parameter name="H2F_IRQ_EMAC2_Enable" value="false" />
  <parameter name="Periph_emacb_src_override" value="7" />
  <parameter name="REG_io24_output_delay" value="0" />
  <parameter name="REG_pin45_sel" value="8" />
  <parameter name="hps_ioa23_opd_en" value="false" />
  <parameter name="User1_clk_freq" value="500.0" />
  <parameter name="FPGA_I2CEMAC1_clk_mhz" value="125.0" />
  <parameter name="REG_io38_output_delay" value="0" />
  <parameter name="MPU_clk_freq_override_mhz" value="533.33" />
  <parameter name="f2sdram_data_width" value="256" />
  <parameter name="REG_pin28_sel" value="8" />
  <parameter name="hps_ioa12_opd_en" value="false" />
  <parameter name="H2F_Width" value="128" />
  <parameter name="REG_pin0_sel" value="1" />
  <parameter name="Debug_APB_Enable" value="false" />
  <parameter name="CM_PinMuxing" value="Unused" />
  <parameter name="EMAC1_PinMuxing" value="Unused" />
  <parameter name="f2s_SMMU" value="false" />
  <parameter name="F2H_free_clock_enable" value="false" />
  <parameter name="OPT_f2soc_sel" value="0" />
  <parameter name="PPLL_Clock_Source" value="0" />
  <parameter name="REG_io10_output_delay" value="0" />
  <parameter name="MPLL_Clock_Source" value="0" />
  <parameter name="SPIM0_Mode" value="N/A" />
  <parameter name="REG_emacctl_emac2sel" value="0" />
  <parameter name="MPU_clk_sources" value="MainC2,MPU,MPU,MainC1,MainC0,MainC0" />
  <parameter name="f2s_mode" value="ace5lite" />
  <parameter name="REG_io7_input_delay" value="0" />
  <parameter name="REG_ppllc2_div" value="125" />
  <parameter name="REG_pin19_sel" value="0" />
  <parameter name="REG_pinmux_emac0_usefpga_sel" value="0" />
  <parameter name="REG_io6_input_delay" value="0" />
  <parameter name="TRACE_PinMuxing" value="Unused" />
  <parameter
     name="PIN_TO_BALL_MAP"
     value="HPS_IOA_24,AJ75,HPS_IOB_5,Y75,HPS_IOB_6,AN64,HPS_IOB_7,Y74,HPS_IOB_8,AK69,HPS_IOB_9,U74,HPS_IOB_10,AK67,HPS_IOB_11,P75,HPS_IOB_12,P74,HPS_IOB_13,L75,HPS_IOB_14,N72,HPS_IOB_15,N71,HPS_IOB_16,AD72,HPS_IOB_17,F75,HPS_IOB_18,AD71,HPS_IOB_19,K71,HPS_IOB_20,AK71,HPS_IOB_21,F74,HPS_IOB_22,AA71,HPS_IOB_23,C74,HPS_IOB_24,D71,HPS_IOA_1,BC64,HPS_IOA_2,BC67,HPS_IOA_3,AY67,HPS_IOA_4,AN72,HPS_IOA_5,AY69,HPS_IOA_6,BA75,HPS_IOA_7,BC71,HPS_IOA_8,AU74,HPS_IOA_10,AU75,HPS_IOA_9,AY71,HPS_IOA_11,BC72,HPS_IOA_12,BP74,HPS_IOA_13,BP75,HPS_IOA_14,BL74,HPS_IOA_15,BL75,HPS_IOA_16,AP74,HPS_IOA_17,BG74,HPS_IOA_18,AP75,HPS_IOA_19,BD74,HPS_IOA_20,AN71,HPS_IOB_1,AF75,HPS_IOA_21,BD75,HPS_IOB_2,AC75,HPS_IOA_22,AM74,HPS_IOB_3,AC74,HPS_IOA_23,AJ74,HPS_IOB_4,AN67" />
  <parameter name="REG_usb31ctr_cnt" value="19" />
  <parameter name="EMAC1_PPS_Enable" value="false" />
  <parameter name="hps_ioa6_opd_en" value="false" />
  <parameter name="hps_ioa2_opd_en" value="false" />
  <parameter name="hps_ioa8_opd_en" value="false" />
  <parameter name="REG_pinmux_emac1_usefpga_sel" value="0" />
  <parameter name="REG_io19_output_delay" value="0" />
  <parameter name="ED_f2h_traffic_pattern" value="0" />
  <parameter name="REG_io5_output_delay" value="0" />
  <parameter name="REG_io18_output_delay" value="0" />
  <parameter name="REG_nocdiv_csclk" value="0" />
  <parameter name="PPLL_Override" value="true" />
  <parameter name="MPFE_is_present" value="true" />
  <parameter name="REG_io2_input_delay" value="0" />
  <parameter name="LWH2F_Width" value="32" />
  <parameter name="FPGA_I2CEMAC2_clk_mhz" value="125.0" />
  <parameter name="REG_io3_input_delay" value="0" />
  <parameter name="MPU_core01_src_override" value="1" />
  <parameter name="REG_nocdiv_l4sysfreeclk" value="2" />
  <parameter name="Pwr_mpu_l3_cache_size" value="1" />
  <parameter name="UART0_PinMuxing" value="Unused" />
  <parameter name="I2CEMAC2_PinMuxing" value="Unused" />
  <parameter name="REG_pin46_sel" value="5" />
  <parameter name="DMA_Enable" value="No,No,No,No,No,No,No,No" />
  <parameter name="H2F_IRQ_I2C1_Enable" value="false" />
  <parameter name="FPGA_I2C1_sclk_mhz" value="125.0" />
  <parameter name="PPLL_Outputs" value="VCO,C0,C1,C2,C3" />
  <parameter name="ED_en_riviera" value="false" />
  <parameter name="REG_pin12_sel" value="0" />
  <parameter name="REG_emacptpctr_src" value="0" />
  <parameter name="Pwr_boot_core_sel" value="0" />
  <parameter name="ED_lwh2f_data_width" value="32" />
  <parameter name="EMAC2_PinMuxing" value="Unused" />
  <parameter name="REG_io6_output_delay" value="0" />
  <parameter name="REG_mpllglob_fastrefclk" value="0" />
  <parameter name="I2C1_Mode" value="default" />
  <parameter name="F2H_free_clk_mhz" value="125" />
  <parameter name="User1_clk_enable" value="false" />
  <parameter name="REG_io29_output_delay" value="0" />
  <parameter name="REG_gpiodbctr_src" value="0" />
  <parameter name="User1_clk_src_select" value="7" />
  <parameter name="ED_lwh2f_addr_width" value="26" />
  <parameter name="REG_io11_output_delay" value="0" />
  <parameter name="MPLL_VCO_Override_mhz" value="3200.0" />
  <parameter name="NAND_PinMuxing" value="Unused" />
  <parameter name="OPT_l3cache_size" value="1" />
  <parameter name="REG_pin31_sel" value="3" />
  <parameter name="REG_io33_output_delay" value="0" />
  <parameter name="REG_pin27_sel" value="9" />
  <parameter name="REG_mpllc1_div" value="4" />
  <parameter name="ED_f2h_packet_size" value="1" />
  <parameter name="REG_io23_output_delay" value="0" />
  <parameter name="MPLL_Frequencies" value="3200.00,800.00,800.00,533.33,400.00" />
  <parameter name="Periph_clk_emac2_sel" value="250" />
  <parameter name="hps_ioa21_opd_en" value="false" />
  <parameter name="EMAC2_Mode" value="N/A" />
  <parameter name="REG_emacactr_src" value="1" />
  <parameter name="GP_Enable" value="false" />
  <parameter name="REG_io21_output_delay" value="0" />
  <parameter name="hps_iob19_opd_en" value="false" />
  <parameter name="REG_pinmux_spim1_usefpga_sel" value="0" />
  <parameter name="REG_s2fuser0ctr_cnt" value="0" />
  <parameter name="FPGA_EMAC0_tx_clk_en" value="true" />
  <parameter name="REG_io40_input_delay" value="0" />
  <parameter name="REG_io44_input_delay" value="0" />
  <parameter name="CTI_Enable" value="false" />
  <parameter name="FPGA_EMAC2_md_clk_mhz" value="2.5" />
  <parameter name="H2F_IRQ_SPIS1_Enable" value="false" />
  <parameter name="H2F_IRQ_ECC_SERR_Enable" value="false" />
  <parameter name="REG_io43_output_delay" value="0" />
  <parameter name="IO_OUTPUT_DELAY12" value="21" />
  <parameter name="REG_pin26_sel" value="3" />
  <parameter name="PPLL_VCO_M" value="120" />
  <parameter name="IO_OUTPUT_DELAY11" value="-1" />
  <parameter name="PPLL_VCO_N" value="1" />
  <parameter name="IO_OUTPUT_DELAY10" value="-1" />
  <parameter name="hps_iob8_opd_en" value="false" />
  <parameter name="I2CEMAC0_Mode" value="N/A" />
  <parameter name="REG_pinmux_i2c_emac0_usefpga_sel" value="0" />
  <parameter name="hps_iob14_opd_en" value="false" />
  <parameter name="REG_pin1_sel" value="1" />
  <parameter name="I2CEMAC0_PinMuxing" value="Unused" />
  <parameter name="REG_io12_output_delay" value="117" />
  <parameter name="REG_core2ctr_cnt" value="0" />
  <parameter name="hps_iob3_opd_en" value="false" />
  <parameter name="Rst_h2f_cold_en" value="false" />
  <parameter name="ED_h2f_connectivity" value="1" />
  <parameter name="EMAC0_Mode" value="RGMII_with_MDIO" />
  <parameter name="REG_mpllglob_psrc" value="0" />
  <parameter name="NOC_clk_src_select" value="3" />
  <parameter name="H2F_IRQ_I2CEMAC0_Enable" value="false" />
  <parameter name="eosc1_clk_mhz" value="25.0" />
  <parameter name="REG_ppllc3_div" value="6" />
  <parameter name="hps_ioa22_opd_en" value="false" />
  <parameter name="REG_pin11_sel" value="1" />
  <parameter name="hps_ioa11_opd_en" value="false" />
  <parameter name="REG_usb31ctr_src" value="0" />
  <parameter name="Periph_emac_ptp_freq_override" value="400.0" />
  <parameter name="I2CEMAC2_Mode" value="N/A" />
  <parameter name="REG_emacctl_emac1sel" value="0" />
  <parameter name="H2F_IRQ_Watchdog_Enable" value="false" />
  <parameter name="Periph_gpio_src_override" value="3" />
  <parameter name="REG_io30_input_delay" value="0" />
  <parameter name="H2F_IRQ_I2C0_Enable" value="false" />
  <parameter name="REG_nocdiv_cstraceclk" value="2" />
  <parameter name="REG_io42_output_delay" value="0" />
  <parameter name="IO_OUTPUT_DELAY29" value="-1" />
  <parameter name="IO_OUTPUT_DELAY28" value="-1" />
  <parameter name="I3C0_PinMuxing" value="Unused" />
  <parameter name="IO_OUTPUT_DELAY27" value="-1" />
  <parameter name="IO_OUTPUT_DELAY26" value="-1" />
  <parameter name="IO_OUTPUT_DELAY25" value="-1" />
  <parameter name="IO_OUTPUT_DELAY24" value="-1" />
  <parameter name="IO_OUTPUT_DELAY7" value="-1" />
  <parameter name="IO_INPUT_DELAY28" value="-1" />
  <parameter name="IO_OUTPUT_DELAY34" value="-1" />
  <parameter name="hps_iob20_opd_en" value="false" />
  <parameter name="REG_emacptpctr_cnt" value="0" />
  <parameter name="IO_OUTPUT_DELAY6" value="-1" />
  <parameter name="IO_INPUT_DELAY27" value="-1" />
  <parameter name="IO_OUTPUT_DELAY33" value="-1" />
  <parameter name="IO_OUTPUT_DELAY9" value="-1" />
  <parameter name="IO_INPUT_DELAY26" value="-1" />
  <parameter name="IO_OUTPUT_DELAY32" value="-1" />
  <parameter name="IO_OUTPUT_DELAY8" value="-1" />
  <parameter name="IO_INPUT_DELAY25" value="-1" />
  <parameter name="IO_OUTPUT_DELAY31" value="-1" />
  <parameter name="IO_OUTPUT_DELAY30" value="-1" />
  <parameter name="REG_io32_output_delay" value="0" />
  <parameter name="I3C1_PinMuxing" value="Unused" />
  <parameter name="IO_INPUT_DELAY29" value="-1" />
  <parameter name="IO_INPUT_DELAY20" value="-1" />
  <parameter name="REG_pin47_sel" value="5" />
  <parameter name="IO_OUTPUT_DELAY1" value="-1" />
  <parameter name="IO_OUTPUT_DELAY0" value="-1" />
  <parameter name="IO_OUTPUT_DELAY3" value="-1" />
  <parameter name="IO_INPUT_DELAY24" value="-1" />
  <parameter name="IO_OUTPUT_DELAY2" value="-1" />
  <parameter name="IO_INPUT_DELAY23" value="-1" />
  <parameter name="IO_OUTPUT_DELAY5" value="-1" />
  <parameter name="IO_INPUT_DELAY22" value="-1" />
  <parameter name="IO_OUTPUT_DELAY4" value="-1" />
  <parameter name="IO_INPUT_DELAY21" value="-1" />
  <parameter name="ATB_Enable" value="false" />
  <parameter name="I2CEMAC1_PinMuxing" value="Unused" />
  <parameter name="H2F_IRQ_PeriphClock_Enable" value="false" />
  <parameter name="MPU_clk_src_override" value="2" />
  <parameter name="IO_OUTPUT_DELAY19" value="-1" />
  <parameter name="IO_OUTPUT_DELAY18" value="-1" />
  <parameter name="IO_OUTPUT_DELAY17" value="-1" />
  <parameter name="IO_OUTPUT_DELAY16" value="-1" />
  <parameter name="IO_OUTPUT_DELAY15" value="-1" />
  <parameter name="IO_OUTPUT_DELAY14" value="-1" />
  <parameter name="hps_ioa7_opd_en" value="false" />
  <parameter name="IO_OUTPUT_DELAY13" value="-1" />
  <parameter name="IO_INPUT_DELAY17" value="-1" />
  <parameter name="IO_OUTPUT_DELAY23" value="-1" />
  <parameter name="IO_INPUT_DELAY16" value="-1" />
  <parameter name="IO_OUTPUT_DELAY22" value="-1" />
  <parameter name="IO_INPUT_DELAY15" value="-1" />
  <parameter name="IO_OUTPUT_DELAY21" value="-1" />
  <parameter name="REG_pin32_sel" value="8" />
  <parameter name="H2F_IRQ_SPIM1_Enable" value="false" />
  <parameter name="IO_INPUT_DELAY14" value="21" />
  <parameter name="IO_OUTPUT_DELAY20" value="-1" />
  <parameter name="EMAC0_PinMuxing" value="IO" />
  <parameter name="IO_INPUT_DELAY19" value="-1" />
  <parameter name="REG_io22_output_delay" value="0" />
  <parameter name="IO_INPUT_DELAY18" value="-1" />
  <parameter name="REG_pinmux_nand_usefpga_sel" value="0" />
  <parameter name="Periph_clk_emac1_sel" value="250" />
  <parameter name="FPGA_EMAC0_gtx_clk_mhz" value="125.0" />
  <parameter name="IO_INPUT_DELAY13" value="-1" />
  <parameter name="IO_INPUT_DELAY12" value="-1" />
  <parameter name="IO_INPUT_DELAY11" value="-1" />
  <parameter name="REG_mpllc2_div" value="6" />
  <parameter name="IO_INPUT_DELAY10" value="-1" />
  <parameter name="hps_ioa16_opd_en" value="false" />
  <parameter name="REG_emacactr_cnt" value="1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_agilex_5_soc_1400/synth/agilex_hps_intel_agilex_5_soc_1400_kdgjumq.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_agilex_5_soc_1400/synth/agilex_hps_intel_agilex_5_soc_1400_kdgjumq.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/intel_hps/sm/intel_soc_sundancemesa/intel_soc_sundancemesa_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.tclelement.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.generator.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.ddmwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcdocument.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.ngpd.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.shared.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jacl1.3.2a.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-text-1.10.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-lang3-3.12.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/guava-32.0.1-jre.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jfreechart-1.5.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-swing-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-common-1.1.2_20c.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/bare-bones-browser-launch-3.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-jxc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-xjc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/codemodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/dtd-parser.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/FastInfoset.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-tools.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/javax.activation-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/relaxng-datatype.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/rngom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/stax-ex.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/txw2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/xsom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/failureaccess-1.0.1.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/listenablefuture-9999.0-empty-to-avoid-conflict-with-guava.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jsr305-3.0.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/checker-qual-3.33.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/j2objc-annotations-2.8.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-core-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-core-1.1.2_20c.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-io-2.13.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.model.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.privateinterfaces.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/antlr4-runtime-4.7.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopclibrary.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.module.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.dni.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.build.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.hypericonnect.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.cmsis.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlcomponent.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.tcl.interpreter.jar" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/intel_hps/sm/hps/intel_hps_sundancemesa_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.components.tclelement.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.generator.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.ddmwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcdocument.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlwriter.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.ngpd.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.shared.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jacl1.3.2a.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-text-1.10.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-lang3-3.12.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/guava-32.0.1-jre.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jfreechart-1.5.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-swing-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-common-1.1.2_20c.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/bare-bones-browser-launch-3.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-jxc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jaxb-xjc.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/codemodel.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/dtd-parser.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/FastInfoset.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-runtime.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/istack-commons-tools.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/javax.activation-api.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/relaxng-datatype.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/rngom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/stax-ex.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/txw2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/xsom.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/failureaccess-1.0.1.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/listenablefuture-9999.0-empty-to-avoid-conflict-with-guava.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/jsr305-3.0.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/checker-qual-3.33.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/j2objc-annotations-2.8.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/miglayout-core-5.2.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/docking-frames-core-1.1.2_20c.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/commons-io-2.13.0.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.model.common.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.privateinterfaces.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/antlr4-runtime-4.7.2.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopclibrary.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.ipxact.module.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.intel.quartus.dni.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.build.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcreport.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.hypericonnect.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.qsys.cmsis.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.hdlcomponent.jar" />
   <file path="/opt/altera_pro/26.1/qsys/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/intel_hps/sm/mpfe/intel_mpfe_sundancemesa_hw.tcl" />
  </childSourceFiles>
  <instantiator instantiator="agilex_hps" as="intel_agilex_5_soc_inst" />
  <messages>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps_intel_agilex_5_soc_1400_kdgjumq"</message>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps_intel_sundancemesa_hps_100_soonmgi"</message>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps_intel_sundancemesa_mpfe_100_d7hziti"</message>
  </messages>
 </entity>
 <entity
   kind="intel_sundancemesa_hps"
   version="1.0.0"
   name="agilex_hps_intel_sundancemesa_hps_100_soonmgi">
  <parameter
     name="HPS_HANDOFF_OPTION_STRING"
     value="    HPS_PRESENT: true
    HPS_DDR_PRESENT: true
    hps_wachdog_expiration: COLD_RESET
    cores_power_state: 15
    boot_core: 0
    l3_cache_size: HALF_ON
    f2soc_intfcsel: DISABLE
    f2sdram_intfcsel: ENABLE" />
  <parameter name="User0_clk_freq" value="500.0" />
  <parameter name="NOC_clk_periph_l4_div" value="2" />
  <parameter name="PPLL_C1_Override_mhz" value="600.0" />
  <parameter
     name="Periph_clk_frequencies"
     value="250,250,250,400.00,200.00,100.00,500.00,20.00" />
  <parameter name="IO_OUTPUT_DELAY47" value="-1" />
  <parameter name="IO_OUTPUT_DELAY46" value="-1" />
  <parameter name="MPLL_VCO_M" value="128" />
  <parameter name="IO_INPUT_DELAY5" value="-1" />
  <parameter name="MPLL_VCO_N" value="1" />
  <parameter name="IO_INPUT_DELAY6" value="-1" />
  <parameter name="SPIS1_Mode" value="N/A" />
  <parameter name="IO_INPUT_DELAY7" value="-1" />
  <parameter name="IO_INPUT_DELAY8" value="-1" />
  <parameter name="IO_INPUT_DELAY47" value="-1" />
  <parameter name="IO_INPUT_DELAY9" value="-1" />
  <parameter name="MPU_clk_periph_div" value="4" />
  <parameter name="IO_INPUT_DELAY42" value="-1" />
  <parameter name="Pwr_a76_core3_on" value="true" />
  <parameter name="IO_INPUT_DELAY41" value="-1" />
  <parameter name="DMA_PeriphID" value="0,1,2,3,4,5,6,7" />
  <parameter name="IO_INPUT_DELAY40" value="-1" />
  <parameter name="NOC_clk_free_l4_div" value="4" />
  <parameter name="IO_INPUT_DELAY46" value="-1" />
  <parameter name="IO_INPUT_DELAY45" value="-1" />
  <parameter name="IO_INPUT_DELAY44" value="-1" />
  <parameter name="NOC_clk_cs_div" value="1" />
  <parameter name="Periph_usb_src_override" value="3" />
  <parameter name="IO_INPUT_DELAY43" value="-1" />
  <parameter name="FPGA_EMAC0_md_clk_mhz" value="2.5" />
  <parameter name="IO_INPUT_DELAY0" value="-1" />
  <parameter name="IO_OUTPUT_DELAY39" value="-1" />
  <parameter name="IO_INPUT_DELAY1" value="-1" />
  <parameter name="IO_OUTPUT_DELAY38" value="-1" />
  <parameter name="IO_INPUT_DELAY2" value="-1" />
  <parameter name="IO_OUTPUT_DELAY37" value="-1" />
  <parameter name="IO_INPUT_DELAY3" value="-1" />
  <parameter name="IO_OUTPUT_DELAY36" value="-1" />
  <parameter name="IO_INPUT_DELAY4" value="-1" />
  <parameter name="IO_OUTPUT_DELAY35" value="-1" />
  <parameter name="IO_INPUT_DELAY39" value="-1" />
  <parameter name="IO_OUTPUT_DELAY45" value="-1" />
  <parameter
     name="Periph_clk_sources"
     value="PeriphC3,PeriphC3,PeriphC3,MainC3,MainC3,GDB Free,PeriphC3,MainC3" />
  <parameter name="IO_INPUT_DELAY38" value="-1" />
  <parameter name="IO_OUTPUT_DELAY44" value="-1" />
  <parameter name="IO_INPUT_DELAY37" value="-1" />
  <parameter name="IO_OUTPUT_DELAY43" value="-1" />
  <parameter name="H2F_IRQ_SPIM0_Enable" value="false" />
  <parameter name="IO_INPUT_DELAY36" value="-1" />
  <parameter name="IO_OUTPUT_DELAY42" value="-1" />
  <parameter name="FPGA_EMAC1_md_clk_mhz" value="2.5" />
  <parameter name="UART1_Mode" value="No_flow_control" />
  <parameter name="IO_OUTPUT_DELAY41" value="-1" />
  <parameter name="H2F_IRQ_UART0_Enable" value="false" />
  <parameter name="IO_OUTPUT_DELAY40" value="-1" />
  <parameter name="SPIM1_Mode" value="N/A" />
  <parameter name="H2F_IRQ_EMAC1_Enable" value="false" />
  <parameter name="IO_INPUT_DELAY31" value="-1" />
  <parameter name="IO_INPUT_DELAY30" value="-1" />
  <parameter name="IO_INPUT_DELAY35" value="-1" />
  <parameter name="IO_INPUT_DELAY34" value="-1" />
  <parameter name="IO_INPUT_DELAY33" value="-1" />
  <parameter name="IO_INPUT_DELAY32" value="-1" />
  <parameter name="MPFE_ATB_Enable" value="false" />
  <parameter name="device_family" value="Agilex 5" />
  <parameter name="MPLL_Outputs" value="VCO,C0,C1,C2,C3" />
  <parameter name="PPLL_C0_Override_mhz" value="600.0" />
  <parameter name="hps_iob23_opd_en" value="false" />
  <parameter name="I2C0_Mode" value="N/A" />
  <parameter name="PPLL_C2_Override_mhz" value="24.0" />
  <parameter name="PPLL_VCO_Fref_mhz" value="25.0" />
  <parameter name="Rst_hps_warm_en" value="false" />
  <parameter name="EMAC2_PTP" value="false" />
  <parameter name="I3C1_Mode" value="N/A" />
  <parameter name="H2F_IRQ_USB1_Enable" value="false" />
  <parameter name="Periph_usb_freq_override" value="20.0" />
  <parameter name="MPFE_f2sdram_address_width" value="32" />
  <parameter name="MPLL_VCO_Fref_mhz" value="25.0" />
  <parameter name="MPFE_f2s_data_width" value="0" />
  <parameter name="hps_iob2_opd_en" value="false" />
  <parameter name="H2F_IRQ_DMA_Enable1" value="false" />
  <parameter name="H2F_IRQ_DMA_Enable0" value="false" />
  <parameter name="USB1_Mode" value="N/A" />
  <parameter name="H2F_IRQ_SDMMC_Enable" value="false" />
  <parameter name="hps_iob6_opd_en" value="false" />
  <parameter name="hps_ioa1_opd_en" value="false" />
  <parameter name="Periph_clk_emac0_sel" value="250" />
  <parameter name="MPLL_C2_Override_mhz" value="533.33" />
  <parameter name="hps_ioa5_opd_en" value="false" />
  <parameter name="hps_ioa9_opd_en" value="false" />
  <parameter name="MPLL_C0_Override_mhz" value="800.0" />
  <parameter name="USB0_PinMuxing" value="IO" />
  <parameter name="H2F_IRQ_I2CEMAC1_Enable" value="false" />
  <parameter name="User0_clk_enable" value="false" />
  <parameter name="MPU_clk_ccu_div" value="2" />
  <parameter name="FPGA_I3C1_sclk_mhz" value="125.0" />
  <parameter name="MPFE_f2s_mode" value="ace5lite" />
  <parameter name="Pwr_a76_core2_on" value="true" />
  <parameter name="hps_ioa10_opd_en" value="false" />
  <parameter name="hps_ioa14_opd_en" value="false" />
  <parameter name="hps_ioa18_opd_en" value="false" />
  <parameter name="hps_iob16_opd_en" value="false" />
  <parameter name="hps_iob18_opd_en" value="false" />
  <parameter name="MPFE_Lite_is_present" value="false" />
  <parameter name="H2F_IRQ_SPIS0_Enable" value="false" />
  <parameter name="PPLL_VCO_fdiv" value="0" />
  <parameter name="TPIU_Select" value="HPS Clock Manager" />
  <parameter name="EMAC0_PPS_Enable" value="false" />
  <parameter name="hps_iob9_opd_en" value="false" />
  <parameter name="device_trait_iobank_rev" value="IO96B_REVB1" />
  <parameter name="PPLL_C3_Override_mhz" value="500.0" />
  <parameter name="FPGA_SPIM1_sclk_mhz" value="125.0" />
  <parameter name="hps_iob10_opd_en" value="false" />
  <parameter name="hps_iob13_opd_en" value="false" />
  <parameter name="hps_iob15_opd_en" value="false" />
  <parameter name="SPIS1_PinMuxing" value="Unused" />
  <parameter name="SDMMC_Mode" value="4-bit" />
  <parameter name="Periph_gpio_freq_override" value="400.0" />
  <parameter name="JAVA_ERROR_MSG" value="" />
  <parameter name="Periph_emac_ptp_src_override" value="7" />
  <parameter name="FPGA_I3C0_sclk_mhz" value="125.0" />
  <parameter name="FPGA_EMAC1_tx_clk_en" value="true" />
  <parameter name="hps_iob1_opd_en" value="false" />
  <parameter name="Pwr_override_cache_size" value="false" />
  <parameter name="PPLL_VCO_Override_mhz" value="3000.0" />
  <parameter name="H2F_IRQ_I2CEMAC2_Enable" value="false" />
  <parameter name="MPU_core3_freq_override_mhz" value="800.0" />
  <parameter name="User0_clk_src_select" value="7" />
  <parameter name="hps_iob7_opd_en" value="false" />
  <parameter name="NOC_clk_slow_l4_div" value="4" />
  <parameter name="Pwr_a55_core0_1_on" value="true" />
  <parameter name="I2C1_PinMuxing" value="IO" />
  <parameter
     name="MPU_clk_outputs"
     value="MPU,MPU CCU,MPU Periph,Core0|Core1,Core2,Core3" />
  <parameter name="SPIM0_PinMuxing" value="Unused" />
  <parameter name="H2F_IRQ_I3C0_Enable" value="false" />
  <parameter name="H2F_IRQ_L4Timer_Enable" value="false" />
  <parameter name="MPU_core01_freq_override_mhz" value="800.0" />
  <parameter name="SPIS0_PinMuxing" value="Unused" />
  <parameter name="FPGA_SPIM0_sclk_mhz" value="125.0" />
  <parameter name="hps_ioa20_opd_en" value="false" />
  <parameter name="hps_ioa15_opd_en" value="false" />
  <parameter name="hps_ioa17_opd_en" value="false" />
  <parameter name="I3C0_Mode" value="N/A" />
  <parameter
     name="HPS_IO_Enable"
     value="USB0:CLK,USB0:STP,USB0:DIR,USB0:DATA0,USB0:DATA1,USB0:NXT,USB0:DATA2,USB0:DATA3,USB0:DATA4,USB0:DATA5,USB0:DATA6,USB0:DATA7,EMAC0:TX_CLK,EMAC0:TX_CTL,EMAC0:RX_CLK,EMAC0:RX_CTL,EMAC0:TXD0,EMAC0:TXD1,EMAC0:RXD0,EMAC0:RXD1,EMAC0:TXD2,EMAC0:TXD3,EMAC0:RXD2,EMAC0:RXD3,SDMMC:DATA0,SDMMC:DATA1,SDMMC:CCLK,HCLK:HPS_OSC_CLK,GPIO1:IO4,SDMMC:DATA2,SDMMC:DATA3,SDMMC:CMD,NONE,NONE,GPIO1:IO10,NONE,I2C1:SDA,I2C1:SCL,UART1:TX,UART1:RX,GPIO1:IO16,GPIO1:IO17,NONE,NONE,NONE,NONE,MDIO0:MDIO,MDIO0:MDC" />
  <parameter name="MPU_clk_override" value="true" />
  <parameter name="FPGA_EMAC_PTP_clk_en" value="true" />
  <parameter name="hps_iob24_opd_en" value="false" />
  <parameter name="NOC_clk_cs_trace_div" value="4" />
  <parameter name="I2C0_PinMuxing" value="Unused" />
  <parameter name="JAVA_WARNING_MSG" value="" />
  <parameter name="device_name" value="A5EB013BB23BE4SCS" />
  <parameter name="hps_iob21_opd_en" value="false" />
  <parameter name="MPLL_C3_Override_mhz" value="400.0" />
  <parameter name="USB1_PinMuxing" value="Unused" />
  <parameter name="PPLL_Frequencies" value="3000.00,600.00,600.00,24.00,500.00" />
  <parameter name="H2F_IRQ_USB0_Enable" value="false" />
  <parameter name="FPGA_EMAC2_tx_clk_en" value="true" />
  <parameter name="hps_iob4_opd_en" value="false" />
  <parameter name="UART1_PinMuxing" value="IO" />
  <parameter name="H2F_IRQ_GPIO0_Enable" value="false" />
  <parameter
     name="NOC_clk_sources"
     value="MainC3,NOC,NOC,NOC,L4Periph,NOC,NOC,NOC" />
  <parameter name="Rst_watchdog_en" value="false" />
  <parameter name="H2F_IRQ_UART1_Enable" value="false" />
  <parameter name="Periph_psi_freq_override" value="500.0" />
  <parameter name="hps_ioa3_opd_en" value="false" />
  <parameter name="H2F_IRQ_EMAC2_Enable" value="false" />
  <parameter name="Periph_emacb_src_override" value="7" />
  <parameter name="hps_ioa23_opd_en" value="false" />
  <parameter name="LWH2F_Address_Width" value="29" />
  <parameter name="User1_clk_freq" value="500.0" />
  <parameter name="H2F_Address_Width" value="38" />
  <parameter name="FPGA_I2CEMAC1_clk_mhz" value="125.0" />
  <parameter name="MPU_clk_freq_override_mhz" value="533.33" />
  <parameter name="hps_ioa12_opd_en" value="false" />
  <parameter name="FPGA_EMAC1_gtx_clk_mhz" value="125.0" />
  <parameter
     name="HPS_HANDOFF_STRING"
     value="pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 9
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 4
}
pinmux_select {
  value: 4
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 5
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 117
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 117
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocclk.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.cspdbgclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.cstraceclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.csclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.mpuperiphdiv&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.ccudiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.softphydiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4spclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4mpclk&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4sysfreeclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.modclkdiv&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.fastrefclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.psrc&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.drefclkdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.arefclkdiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.fdbck.fdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllc0.div&quot;
  reg_value: 4
}
reg {
  reg_name: &quot;mainpllgrp.pllc1.div&quot;
  reg_value: 4
}
reg {
  reg_name: &quot;mainpllgrp.pllc2.div&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;mainpllgrp.pllc3.div&quot;
  reg_value: 8
}
reg {
  reg_name: &quot;mainpllgrp.pllm.mdiv&quot;
  reg_value: 128
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac0sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac1sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac2sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.modclkdiv&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllglob.fstrefclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.psrc&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.drefclkdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.arefclkdiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;perpllgrp.fdbck.fdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllc0.div&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllc1.div&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllc2.div&quot;
  reg_value: 125
}
reg {
  reg_name: &quot;perpllgrp.pllc3.div&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;perpllgrp.pllm.mdiv&quot;
  reg_value: 120
}
reg {
  reg_name: &quot;ctl.emacactr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacactr.cnt&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacbctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacbctr.cnt&quot;
  reg_value: 9
}
reg {
  reg_name: &quot;ctl.emacptpctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.emacptpctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.gpiodbctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.gpiodbctr.cnt&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;perpllgrp.gpiodiv.gpiodbclk&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser0ctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser0ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.s2fuser1ctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser1ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.psirefctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.psirefctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.usb31ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.usb31ctr.cnt&quot;
  reg_value: 19
}
reg {
  reg_name: &quot;ctl.dsuctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.dsuctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core01ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core01ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core23ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core2ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core3ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;hps_osc_clk_hz&quot;
  reg_value: 25000000
}
reg {
  reg_name: &quot;fpga_clk_hz&quot;
  reg_value: 125000000
}
" />
  <parameter name="H2F_Width" value="128" />
  <parameter name="Debug_APB_Enable" value="false" />
  <parameter name="NAND_Mode" value="N/A" />
  <parameter name="TRACE_Mode" value="N/A" />
  <parameter name="CM_PinMuxing" value="Unused" />
  <parameter name="EMAC1_PinMuxing" value="Unused" />
  <parameter name="F2H_free_clock_enable" value="false" />
  <parameter name="PPLL_Clock_Source" value="0" />
  <parameter name="MPLL_Clock_Source" value="0" />
  <parameter name="SPIM0_Mode" value="N/A" />
  <parameter name="MPFE_f2sdram_data_width" value="256" />
  <parameter name="MPU_clk_sources" value="MainC2,MPU,MPU,MainC1,MainC0,MainC0" />
  <parameter name="SDMMC_PinMuxing" value="IO" />
  <parameter name="hps_ioa4_opd_en" value="false" />
  <parameter name="TRACE_PinMuxing" value="Unused" />
  <parameter name="PIN_TO_BALL_MAP" value="" />
  <parameter name="EMAC1_PPS_Enable" value="false" />
  <parameter name="SPIS0_Mode" value="N/A" />
  <parameter name="hps_ioa6_opd_en" value="false" />
  <parameter name="hps_ioa2_opd_en" value="false" />
  <parameter name="hps_ioa8_opd_en" value="false" />
  <parameter name="PPLL_Override" value="true" />
  <parameter name="MPFE_is_present" value="true" />
  <parameter name="LWH2F_Width" value="32" />
  <parameter name="FPGA_I2CEMAC2_clk_mhz" value="125.0" />
  <parameter name="EMAC2_PPS_Enable" value="false" />
  <parameter name="MPU_core01_src_override" value="1" />
  <parameter name="MPLL_Override" value="true" />
  <parameter name="Pwr_mpu_l3_cache_size" value="1" />
  <parameter name="UART0_PinMuxing" value="Unused" />
  <parameter name="PLL_CLK3" value="Unused" />
  <parameter name="I2CEMAC2_PinMuxing" value="Unused" />
  <parameter name="PLL_CLK4" value="Unused" />
  <parameter name="DMA_Enable" value="No,No,No,No,No,No,No,No" />
  <parameter name="H2F_IRQ_I2C1_Enable" value="false" />
  <parameter name="FPGA_I2C1_sclk_mhz" value="125.0" />
  <parameter name="PPLL_Outputs" value="VCO,C0,C1,C2,C3" />
  <parameter name="Pwr_boot_core_sel" value="0" />
  <parameter name="hps_iob22_opd_en" value="false" />
  <parameter name="MPU_core23_src_override" value="0" />
  <parameter name="EMAC2_PinMuxing" value="Unused" />
  <parameter name="I2C1_Mode" value="default" />
  <parameter name="F2H_free_clk_mhz" value="125" />
  <parameter name="User1_clk_enable" value="false" />
  <parameter name="Rst_sdm_wd_config" value="0" />
  <parameter name="User1_clk_src_select" value="7" />
  <parameter name="STM_Enable" value="false" />
  <parameter name="MPLL_VCO_Override_mhz" value="3200.0" />
  <parameter name="NAND_PinMuxing" value="Unused" />
  <parameter name="MPFE_f2s_address_width" value="32" />
  <parameter
     name="NOC_clk_frequencies"
     value="400.0,100.0,200.0,100.0,200.0,400.0,100.0,100.0" />
  <parameter name="Periph_emaca_src_override" value="7" />
  <parameter name="MPLL_Frequencies" value="3200.00,800.00,800.00,533.33,400.00" />
  <parameter
     name="NOC_clk_outputs"
     value="NOC,L4 Free,L4 Peripheral,L4 Slow Peripheral,SoftPHY,CoreSight,CoreSight Debug APB,CoreSight Trace IO" />
  <parameter name="Periph_clk_emac2_sel" value="250" />
  <parameter name="EMAC0_PTP" value="false" />
  <parameter name="UART0_Mode" value="N/A" />
  <parameter name="H2F_IRQ_EMAC0_Enable" value="false" />
  <parameter name="hps_ioa21_opd_en" value="false" />
  <parameter name="EMAC2_Mode" value="N/A" />
  <parameter name="GP_Enable" value="false" />
  <parameter name="Periph_clk_override" value="false" />
  <parameter name="CM_Mode" value="N/A" />
  <parameter name="MPLL_VCO_fdiv" value="0" />
  <parameter name="I2CEMAC1_Mode" value="N/A" />
  <parameter name="hps_iob19_opd_en" value="false" />
  <parameter name="FPGA_EMAC0_tx_clk_en" value="true" />
  <parameter name="hps_iob17_opd_en" value="false" />
  <parameter name="CTI_Enable" value="false" />
  <parameter name="SPIM1_PinMuxing" value="Unused" />
  <parameter name="FPGA_EMAC2_md_clk_mhz" value="2.5" />
  <parameter name="H2F_IRQ_SPIS1_Enable" value="false" />
  <parameter name="USB0_Mode" value="default" />
  <parameter name="H2F_IRQ_ECC_SERR_Enable" value="false" />
  <parameter name="H2F_IRQ_I3C1_Enable" value="false" />
  <parameter name="EMAC1_Mode" value="N/A" />
  <parameter name="IO_OUTPUT_DELAY12" value="21" />
  <parameter name="PPLL_VCO_M" value="120" />
  <parameter name="IO_OUTPUT_DELAY11" value="-1" />
  <parameter name="PPLL_VCO_N" value="1" />
  <parameter name="IO_OUTPUT_DELAY10" value="-1" />
  <parameter name="hps_iob8_opd_en" value="false" />
  <parameter name="I2CEMAC0_Mode" value="N/A" />
  <parameter name="hps_iob11_opd_en" value="false" />
  <parameter name="hps_iob12_opd_en" value="false" />
  <parameter name="hps_iob14_opd_en" value="false" />
  <parameter name="MPU_Events_Enable" value="false" />
  <parameter name="I2CEMAC0_PinMuxing" value="Unused" />
  <parameter name="MPU_core2_freq_override_mhz" value="800.0" />
  <parameter name="JTAG_Enable" value="false" />
  <parameter name="MPFE_f2s_SMMU" value="0" />
  <parameter name="hps_iob3_opd_en" value="false" />
  <parameter name="FPGA_I2CEMAC0_clk_mhz" value="125.0" />
  <parameter name="Rst_h2f_cold_en" value="false" />
  <parameter name="Pwr_cpu_app_select" value="0" />
  <parameter name="EMAC0_Mode" value="RGMII_with_MDIO" />
  <parameter name="hps_iob5_opd_en" value="false" />
  <parameter name="NOC_clk_src_select" value="3" />
  <parameter name="H2F_IRQ_GPIO1_Enable" value="false" />
  <parameter
     name="MPU_clk_frequencies"
     value="533.33,266.665,133.3325,800.00,800.00,800.00" />
  <parameter name="H2F_IRQ_I2CEMAC0_Enable" value="false" />
  <parameter name="hps_ioa24_opd_en" value="false" />
  <parameter name="eosc1_clk_mhz" value="25.0" />
  <parameter name="NOC_clk_phy_div" value="1" />
  <parameter name="hps_ioa22_opd_en" value="false" />
  <parameter name="PLL_CLK1" value="Unused" />
  <parameter name="hps_ioa11_opd_en" value="false" />
  <parameter name="H2F_IRQ_NAND_Enable" value="false" />
  <parameter name="Periph_emac_ptp_freq_override" value="400.0" />
  <parameter name="PLL_CLK2" value="Unused" />
  <parameter name="I2CEMAC2_Mode" value="N/A" />
  <parameter name="hps_ioa19_opd_en" value="false" />
  <parameter name="PLL_CLK0" value="Unused" />
  <parameter name="hps_ioa13_opd_en" value="false" />
  <parameter name="H2F_IRQ_Watchdog_Enable" value="false" />
  <parameter name="Periph_gpio_src_override" value="3" />
  <parameter name="H2F_IRQ_I2C0_Enable" value="false" />
  <parameter name="IO_OUTPUT_DELAY29" value="-1" />
  <parameter name="IO_OUTPUT_DELAY28" value="-1" />
  <parameter name="I3C0_PinMuxing" value="Unused" />
  <parameter name="IO_OUTPUT_DELAY27" value="-1" />
  <parameter name="IO_OUTPUT_DELAY26" value="-1" />
  <parameter name="IO_OUTPUT_DELAY25" value="-1" />
  <parameter name="IO_OUTPUT_DELAY24" value="-1" />
  <parameter name="IO_OUTPUT_DELAY7" value="-1" />
  <parameter name="IO_INPUT_DELAY28" value="-1" />
  <parameter name="IO_OUTPUT_DELAY34" value="-1" />
  <parameter name="hps_iob20_opd_en" value="false" />
  <parameter name="IO_OUTPUT_DELAY6" value="-1" />
  <parameter name="IO_INPUT_DELAY27" value="-1" />
  <parameter name="IO_OUTPUT_DELAY33" value="-1" />
  <parameter name="IO_OUTPUT_DELAY9" value="-1" />
  <parameter name="IO_INPUT_DELAY26" value="-1" />
  <parameter name="IO_OUTPUT_DELAY32" value="-1" />
  <parameter name="IO_OUTPUT_DELAY8" value="-1" />
  <parameter name="IO_INPUT_DELAY25" value="-1" />
  <parameter name="IO_OUTPUT_DELAY31" value="-1" />
  <parameter name="IO_OUTPUT_DELAY30" value="-1" />
  <parameter name="I3C1_PinMuxing" value="Unused" />
  <parameter name="IO_INPUT_DELAY29" value="-1" />
  <parameter name="IO_INPUT_DELAY20" value="-1" />
  <parameter name="IO_OUTPUT_DELAY1" value="-1" />
  <parameter name="NOC_clk_cs_debug_div" value="4" />
  <parameter name="IO_OUTPUT_DELAY0" value="-1" />
  <parameter
     name="Periph_clk_outputs"
     value="EMAC0,EMAC1,EMAC2,EMAC PTP,GDB Free,GPIO Debounce,PSI Ref,USB 3.1" />
  <parameter name="IO_OUTPUT_DELAY3" value="-1" />
  <parameter name="IO_INPUT_DELAY24" value="-1" />
  <parameter name="IO_OUTPUT_DELAY2" value="-1" />
  <parameter name="IO_INPUT_DELAY23" value="-1" />
  <parameter name="IO_OUTPUT_DELAY5" value="-1" />
  <parameter name="IO_INPUT_DELAY22" value="-1" />
  <parameter name="IO_OUTPUT_DELAY4" value="-1" />
  <parameter name="IO_INPUT_DELAY21" value="-1" />
  <parameter name="EMAC1_PTP" value="false" />
  <parameter name="Periph_psi_src_override" value="7" />
  <parameter name="I2CEMAC1_PinMuxing" value="Unused" />
  <parameter name="H2F_IRQ_PeriphClock_Enable" value="false" />
  <parameter name="MPU_clk_src_override" value="2" />
  <parameter name="IO_OUTPUT_DELAY19" value="-1" />
  <parameter name="F2H_IRQ_Enable" value="true" />
  <parameter name="IO_OUTPUT_DELAY18" value="-1" />
  <parameter name="IO_OUTPUT_DELAY17" value="-1" />
  <parameter name="FPGA_I2C0_sclk_mhz" value="125.0" />
  <parameter name="IO_OUTPUT_DELAY16" value="-1" />
  <parameter name="IO_OUTPUT_DELAY15" value="-1" />
  <parameter name="IO_OUTPUT_DELAY14" value="-1" />
  <parameter name="hps_ioa7_opd_en" value="false" />
  <parameter name="MPLL_C1_Override_mhz" value="800.0" />
  <parameter name="IO_OUTPUT_DELAY13" value="-1" />
  <parameter name="IO_INPUT_DELAY17" value="-1" />
  <parameter name="IO_OUTPUT_DELAY23" value="-1" />
  <parameter name="IO_INPUT_DELAY16" value="-1" />
  <parameter name="IO_OUTPUT_DELAY22" value="-1" />
  <parameter name="IO_INPUT_DELAY15" value="-1" />
  <parameter name="IO_OUTPUT_DELAY21" value="-1" />
  <parameter name="H2F_IRQ_SPIM1_Enable" value="false" />
  <parameter name="IO_INPUT_DELAY14" value="21" />
  <parameter name="IO_OUTPUT_DELAY20" value="-1" />
  <parameter name="EMAC0_PinMuxing" value="IO" />
  <parameter name="IO_INPUT_DELAY19" value="-1" />
  <parameter name="IO_INPUT_DELAY18" value="-1" />
  <parameter name="Pwr_default_mpu_l3_cache_size" value="1MB" />
  <parameter name="H2F_IRQ_SYSTimer_Enable" value="false" />
  <parameter name="Periph_clk_emac1_sel" value="250" />
  <parameter name="FPGA_EMAC0_gtx_clk_mhz" value="125.0" />
  <parameter name="FPGA_EMAC2_gtx_clk_mhz" value="125.0" />
  <parameter name="IO_INPUT_DELAY13" value="-1" />
  <parameter name="IO_INPUT_DELAY12" value="-1" />
  <parameter name="IO_INPUT_DELAY11" value="-1" />
  <parameter name="IO_INPUT_DELAY10" value="-1" />
  <parameter name="hps_ioa16_opd_en" value="false" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/agilex_hps_intel_sundancemesa_hps_100_soonmgi.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/ready_latency_adapter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/ff_macro_p2c.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/ff_macro_c2p.sv"
       attributes="" />
   <file
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       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/scfifo_s_showahead.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/scfifo_s_normal.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/add_a_b_s0_s1.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab.sv"
       attributes="" />
   <file
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       attributes="" />
   <file
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       attributes="" />
   <file
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       attributes="" />
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       attributes="" />
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       attributes="" />
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       attributes="" />
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       attributes="" />
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       attributes="" />
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       attributes="" />
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       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab.sv"
       attributes="" />
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       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_hps_100/synth/agilex_hps_intel_sundancemesa_hps_100_soonmgi.sdc"
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  </messages>
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   name="agilex_hps_intel_sundancemesa_mpfe_100_d7hziti">
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     name="HPS_HANDOFF_STRING"
     value="pinmux_select {
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}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 1
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 0
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 9
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 3
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 4
}
pinmux_select {
  value: 4
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 8
}
pinmux_select {
  value: 5
}
pinmux_select {
  value: 5
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 117
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 117
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
io_delay {
  output_val: 0
  input_val: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocclk.src&quot;
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}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.cspdbgclk&quot;
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}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.cstraceclk&quot;
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}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.csclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.mpuperiphdiv&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.ccudiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.softphydiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4spclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4mpclk&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.nocdiv.l4sysfreeclk&quot;
  reg_value: 2
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.modclkdiv&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.fastrefclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.psrc&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.drefclkdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllglob.arefclkdiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;mainpllgrp.fdbck.fdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;mainpllgrp.pllc0.div&quot;
  reg_value: 4
}
reg {
  reg_name: &quot;mainpllgrp.pllc1.div&quot;
  reg_value: 4
}
reg {
  reg_name: &quot;mainpllgrp.pllc2.div&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;mainpllgrp.pllc3.div&quot;
  reg_value: 8
}
reg {
  reg_name: &quot;mainpllgrp.pllm.mdiv&quot;
  reg_value: 128
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac0sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac1sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.emacctl.emac2sel&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.modclkdiv&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllglob.fstrefclk&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.psrc&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.drefclkdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllglob.arefclkdiv&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;perpllgrp.fdbck.fdiv&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;perpllgrp.pllc0.div&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllc1.div&quot;
  reg_value: 5
}
reg {
  reg_name: &quot;perpllgrp.pllc2.div&quot;
  reg_value: 125
}
reg {
  reg_name: &quot;perpllgrp.pllc3.div&quot;
  reg_value: 6
}
reg {
  reg_name: &quot;perpllgrp.pllm.mdiv&quot;
  reg_value: 120
}
reg {
  reg_name: &quot;ctl.emacactr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacactr.cnt&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacbctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.emacbctr.cnt&quot;
  reg_value: 9
}
reg {
  reg_name: &quot;ctl.emacptpctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.emacptpctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.gpiodbctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.gpiodbctr.cnt&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;perpllgrp.gpiodiv.gpiodbclk&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser0ctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser0ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.s2fuser1ctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.s2fuser1ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.psirefctr.src&quot;
  reg_value: 1
}
reg {
  reg_name: &quot;ctl.psirefctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.usb31ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.usb31ctr.cnt&quot;
  reg_value: 19
}
reg {
  reg_name: &quot;ctl.dsuctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.dsuctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core01ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core01ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core23ctr.src&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core2ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;ctl.core3ctr.cnt&quot;
  reg_value: 0
}
reg {
  reg_name: &quot;hps_osc_clk_hz&quot;
  reg_value: 25000000
}
reg {
  reg_name: &quot;fpga_clk_hz&quot;
  reg_value: 125000000
}
" />
  <parameter
     name="HPS_HANDOFF_OPTION_STRING"
     value="    HPS_PRESENT: true
    HPS_DDR_PRESENT: true
    hps_wachdog_expiration: COLD_RESET
    cores_power_state: 15
    boot_core: 0
    l3_cache_size: HALF_ON
    f2soc_intfcsel: DISABLE
    f2sdram_intfcsel: ENABLE" />
  <parameter name="f2s_mode" value="ace5lite" />
  <parameter name="MPFE_f2s_data_width" value="0" />
  <parameter name="ATB_Enable" value="false" />
  <parameter name="MPFE_f2s_SMMU" value="0" />
  <parameter name="MPFE_ATB_Enable" value="false" />
  <parameter name="MPFE_f2s_address_width" value="32" />
  <parameter name="MPFE_Lite_is_present" value="false" />
  <parameter name="f2sdram_address_width" value="32" />
  <parameter name="device_family" value="Agilex 5" />
  <parameter name="f2s_address_width" value="32" />
  <parameter name="f2sdram_SMMU" value="false" />
  <parameter name="device_name" value="A5EB013BB23BE4SCS" />
  <parameter name="f2s_SMMU" value="false" />
  <parameter name="MPFE_is_present" value="true" />
  <parameter name="f2s_data_width" value="0" />
  <parameter name="MPFE_f2s_mode" value="ace5lite" />
  <parameter name="EMIF_AXI_Enable" value="true" />
  <parameter name="MPFE_f2sdram_address_width" value="32" />
  <parameter name="f2sdram_data_width" value="256" />
  <parameter name="EMIF_Topology" value="1" />
  <parameter name="MPFE_f2sdram_data_width" value="256" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/agilex_hps_intel_sundancemesa_mpfe_100_d7hziti.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/mpfe_ready_latency_adapter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ready_latency_adapter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_c2p.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_p2c.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/scfifo_s.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/scfifo_s_showahead.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/scfifo_s_normal.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/add_a_b_s0_s1.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/generic_mlab.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/generic_m20k.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ready_latency_reset_synchronizer.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/agilex_hps_intel_sundancemesa_mpfe_100_d7hziti.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/mpfe_ready_latency_adapter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ready_latency_adapter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_c2p.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_p2c.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/scfifo_s.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/scfifo_s_showahead.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/scfifo_s_normal.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/add_a_b_s0_s1.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/generic_mlab.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/generic_m20k.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/hps_subsys/agilex_hps/intel_sundancemesa_mpfe_100/synth/ready_latency/ready_latency_reset_synchronizer.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/intel_hps/sm/mpfe/intel_mpfe_sundancemesa_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="agilex_hps_intel_agilex_5_soc_1400_kdgjumq"
     as="sm_mpfe" />
  <messages>
   <message level="Info" culprit="agilex_hps">"Generating: agilex_hps_intel_sundancemesa_mpfe_100_d7hziti"</message>
  </messages>
 </entity>
</deploy>
