<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2026.05.11.21:04:22"
 outputDirectory="/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Agilex 5"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="A5EB013BB23BE4SCS"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_BOARD"
     type="String"
     defaultValue="default"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REFCLK_IN_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REFCLK_IN_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REFCLK_IN_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="refclk_in" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="refclk_in" direction="input" role="clk" width="1" />
  </interface>
  <interface name="refclk_out" kind="clock" start="1">
   <property name="associatedDirectClock" value="" />
   <property name="clockRate" value="0" />
   <property name="clockRateKnown" value="false" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="refclk_out" direction="output" role="clk" width="1" />
  </interface>
  <interface name="refclk_in_gpio" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="refclk_in_gpio" direction="output" role="export" width="1" />
  </interface>
  <interface name="refclk_out_gpio" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="refclk_out_gpio" direction="input" role="export" width="1" />
  </interface>
 </perimeter>
 <entity
   kind="emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"
   version="1.0"
   name="emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge">
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="AUTO_REFCLK_IN_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_REFCLK_IN_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_REFCLK_IN_RESET_DOMAIN" value="-1" />
  <generatedFiles>
   <file
       path="/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.ip" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/altera_lvds/top/ex_design/qsys_interface_bridge/qsys_interface_bridge_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message
       level="Info"
       culprit="emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge">"Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message
       level="Info"
       culprit="emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge">"Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi"</message>
  </messages>
 </entity>
 <entity
   kind="qsys_interface_bridge"
   version="1.0"
   name="emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi">
  <parameter
     name="INTERFACES"
     value="refclk_in        clock    sink,refclk_out       clock    source,refclk_in_gpio   conduit  end,refclk_out_gpio  conduit  start" />
  <parameter
     name="CONNECTIONS"
     value="refclk_in        refclk_in_gpio,refclk_out_gpio  refclk_out" />
  <parameter name="CUSTOM_ELABORATION_COMMANDS" value="" />
  <parameter
     name="PORTS"
     value="refclk_in        refclk_in         clk      input    1,refclk_out       refclk_out        clk      output   1,refclk_in_gpio   refclk_in_gpio    export   output   1,refclk_out_gpio  refclk_out_gpio   export   input    1" />
  <generatedFiles>
   <file
       path="/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/qsys_interface_bridge_10/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/qsys_interface_bridge_10/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/altera_lvds/top/ex_design/qsys_interface_bridge/qsys_interface_bridge_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"
     as="refclk_bridge" />
  <messages>
   <message
       level="Info"
       culprit="emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge">"Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi"</message>
  </messages>
 </entity>
</deploy>
